Remove legacy PostOps code
PostOps was the experimental interface for Dynamic Fusion. It is now
replaced by the new Dynamic Fusion interface with code generation using
the Compute Kernel Writer.
Resolves: COMPMID-6190
Change-Id: I813b48facef2fd6f3aee332588886b4f9b3d33d8
Signed-off-by: Jakub Sujak <jakub.sujak@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10219
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
diff --git a/arm_compute/core/KernelDescriptors.h b/arm_compute/core/KernelDescriptors.h
index 305766e..2bf5dee 100644
--- a/arm_compute/core/KernelDescriptors.h
+++ b/arm_compute/core/KernelDescriptors.h
@@ -21,12 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS
-#define ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS
+#ifndef ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS_H
+#define ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS_H
#include "arm_compute/core/PixelValue.h"
#include "arm_compute/core/Types.h"
-#include "arm_compute/core/experimental/IPostOp.h"
#include "arm_compute/function_info/ActivationLayerInfo.h"
namespace arm_compute
@@ -60,46 +59,43 @@
{
GEMMKernelInfo() = default;
GEMMKernelInfo(
- unsigned int im,
- unsigned int in,
- unsigned int ik,
- unsigned int idepth_output_gemm3d,
- bool ireinterpret_input_as_3d,
- bool ibroadcast_bias,
- bool ifp_mixed_precision,
- bool ihas_pad_y,
- ActivationLayerInfo iactivation_info,
- int inmult_transpose1xW_width,
- int imult_interleave4x4_height,
- GEMMLHSMatrixInfo ilhs_info,
- GEMMRHSMatrixInfo irhs_info,
- int32_t ina_offset,
- int32_t inb_offset,
- const experimental::PostOpList<ITensorInfo *> &ipost_ops = experimental::PostOpList<ITensorInfo *> {})
+ unsigned int im,
+ unsigned int in,
+ unsigned int ik,
+ unsigned int idepth_output_gemm3d,
+ bool ireinterpret_input_as_3d,
+ bool ibroadcast_bias,
+ bool ifp_mixed_precision,
+ bool ihas_pad_y,
+ ActivationLayerInfo iactivation_info,
+ int inmult_transpose1xW_width,
+ int imult_interleave4x4_height,
+ GEMMLHSMatrixInfo ilhs_info,
+ GEMMRHSMatrixInfo irhs_info,
+ int32_t ina_offset,
+ int32_t inb_offset)
: m(im), n(in), k(ik), depth_output_gemm3d(idepth_output_gemm3d), reinterpret_input_as_3d(ireinterpret_input_as_3d), broadcast_bias(ibroadcast_bias), fp_mixed_precision(ifp_mixed_precision),
has_pad_y(ihas_pad_y), activation_info(iactivation_info), mult_transpose1xW_width(inmult_transpose1xW_width), mult_interleave4x4_height(imult_interleave4x4_height), lhs_info(ilhs_info),
- rhs_info(irhs_info), a_offset(ina_offset), b_offset(inb_offset), post_ops(ipost_ops)
+ rhs_info(irhs_info), a_offset(ina_offset), b_offset(inb_offset)
{
}
- unsigned int m{ 0 }; /**< Number of LHS rows*/
- unsigned int n{ 0 }; /**< Number of RHS columns*/
- unsigned int k{ 0 }; /**< Number of LHS columns or RHS rows */
- unsigned int depth_output_gemm3d{ 0 }; /**< Depth of the output tensor in case is reinterpreted as 3D */
- bool reinterpret_input_as_3d{ false }; /**< Flag used to reinterpret the input as 3D */
- bool broadcast_bias{ false }; /**< Flag used to broadcast the bias addition */
- bool fp_mixed_precision{ false }; /**< Flag used to indicate wider accumulators (32 bit instead of 16 for FP16). */
- bool has_pad_y{ false }; /**< Flag used to indicate if the input/output tensors have internal pad on the y direction */
- ActivationLayerInfo activation_info{}; /**< Activation function to perform after the matrix multiplication */
- int mult_transpose1xW_width{ 1 }; /**< Multiplication factor for the width of the 1xW transposed block */
- int mult_interleave4x4_height{ 1 }; /**< Multiplication factor for the height of the 4x4 interleaved block */
- GEMMLHSMatrixInfo lhs_info{}; /**< LHS matrix information used to retrieve the number of rows processed by each thread */
- GEMMRHSMatrixInfo rhs_info{}; /**< RHS matrix information used for reshaping the RHS matrix */
- int32_t a_offset{ 0 }; /**< Offset to be added to each element of the matrix A */
- int32_t b_offset{ 0 }; /**< Offset to be added to each element of the matrix B */
- GEMMLowpOutputStageInfo output_stage{}; /**< GEMMLowp output stage information */
- experimental::PostOpList<ITensorInfo *> post_ops{}; /**< (EXPERIMENTAL_POST_OPS) Specifies a list of post ops to be fused after the main op. Note unsupported post ops would not be executed.
- * If specified, automatically disable the @ref activation_info */
+ unsigned int m{ 0 }; /**< Number of LHS rows*/
+ unsigned int n{ 0 }; /**< Number of RHS columns*/
+ unsigned int k{ 0 }; /**< Number of LHS columns or RHS rows */
+ unsigned int depth_output_gemm3d{ 0 }; /**< Depth of the output tensor in case is reinterpreted as 3D */
+ bool reinterpret_input_as_3d{ false }; /**< Flag used to reinterpret the input as 3D */
+ bool broadcast_bias{ false }; /**< Flag used to broadcast the bias addition */
+ bool fp_mixed_precision{ false }; /**< Flag used to indicate wider accumulators (32 bit instead of 16 for FP16). */
+ bool has_pad_y{ false }; /**< Flag used to indicate if the input/output tensors have internal pad on the y direction */
+ ActivationLayerInfo activation_info{}; /**< Activation function to perform after the matrix multiplication */
+ int mult_transpose1xW_width{ 1 }; /**< Multiplication factor for the width of the 1xW transposed block */
+ int mult_interleave4x4_height{ 1 }; /**< Multiplication factor for the height of the 4x4 interleaved block */
+ GEMMLHSMatrixInfo lhs_info{}; /**< LHS matrix information used to retrieve the number of rows processed by each thread */
+ GEMMRHSMatrixInfo rhs_info{}; /**< RHS matrix information used for reshaping the RHS matrix */
+ int32_t a_offset{ 0 }; /**< Offset to be added to each element of the matrix A */
+ int32_t b_offset{ 0 }; /**< Offset to be added to each element of the matrix B */
+ GEMMLowpOutputStageInfo output_stage{}; /**< GEMMLowp output stage information */
};
/** Compute descriptor used by the depthwise convolution native kernel */
@@ -240,4 +236,4 @@
bool export_rhs_to_cl_image{ false }; /**< Flag to know whether the RHS tensor should be exported to cl_image*/
};
} // namespace arm_compute
-#endif /* ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS */
+#endif // ACL_ARM_COMPUTE_CORE_KERNELDESCRIPTORS_H
diff --git a/arm_compute/core/Types.h b/arm_compute/core/Types.h
index 12d8602..9264cef 100644
--- a/arm_compute/core/Types.h
+++ b/arm_compute/core/Types.h
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ACL_ARM_COMPUTE_CORE_TYPES
-#define ACL_ARM_COMPUTE_CORE_TYPES
+#ifndef ACL_ARM_COMPUTE_CORE_TYPES_H
+#define ACL_ARM_COMPUTE_CORE_TYPES_H
/** The following symbols have been moved to:
* half
@@ -65,7 +65,6 @@
#include "arm_compute/core/Size2D.h"
#include "arm_compute/core/Size3D.h"
#include "arm_compute/core/TensorShape.h"
-#include "arm_compute/core/experimental/IPostOp.h"
#include "arm_compute/core/utils/misc/Macros.h"
#include "support/Bfloat16.h"
@@ -751,14 +750,14 @@
}
private:
- std::vector<float> _min_sizes;
- std::vector<float> _variances;
- float _offset;
- bool _flip;
- bool _clip;
- std::vector<float> _max_sizes;
- std::vector<float> _aspect_ratios;
- Coordinates2D _img_size;
+ std::vector<float> _min_sizes;
+ std::vector<float> _variances;
+ float _offset;
+ bool _flip;
+ bool _clip;
+ std::vector<float> _max_sizes;
+ std::vector<float> _aspect_ratios;
+ Coordinates2D _img_size;
std::array<float, 2> _steps;
};
@@ -1003,15 +1002,15 @@
}
private:
- unsigned int _max_detections;
- unsigned int _max_classes_per_detection;
- float _nms_score_threshold;
- float _iou_threshold;
- unsigned int _num_classes;
+ unsigned int _max_detections;
+ unsigned int _max_classes_per_detection;
+ float _nms_score_threshold;
+ float _iou_threshold;
+ unsigned int _num_classes;
std::array<float, 4> _scales_values;
- bool _use_regular_nms;
- unsigned int _detection_per_class;
- bool _dequantize_scores;
+ bool _use_regular_nms;
+ unsigned int _detection_per_class;
+ bool _dequantize_scores;
};
/** Pooling Layer Information struct*/
@@ -1462,13 +1461,13 @@
}
private:
- float _img_width;
- float _img_height;
- float _scale;
- bool _apply_scale;
- bool _correct_transform_coords;
+ float _img_width;
+ float _img_height;
+ float _scale;
+ bool _apply_scale;
+ bool _correct_transform_coords;
std::array<float, 4> _weights;
- float _bbox_xform_clip;
+ float _bbox_xform_clip;
};
/** Normalization Layer Information class */
@@ -1915,4 +1914,4 @@
/** Class for holding information related to cropping */
using CropInfo = Padding2D;
} // namespace arm_compute
-#endif /* ACL_ARM_COMPUTE_CORE_TYPES */
+#endif // ACL_ARM_COMPUTE_CORE_TYPES_H
diff --git a/arm_compute/core/experimental/IPostOp.h b/arm_compute/core/experimental/IPostOp.h
deleted file mode 100644
index 567a402..0000000
--- a/arm_compute/core/experimental/IPostOp.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef ARM_COMPUTE_EXPERIMENTAL_IPOSTOP
-#define ARM_COMPUTE_EXPERIMENTAL_IPOSTOP
-
-#include <memory>
-#include <numeric>
-#include <vector>
-
-namespace arm_compute
-{
-namespace experimental
-{
-/** Type of Post Op */
-enum class PostOpType
-{
- Activation,
- Eltwise_Add,
- Eltwise_PRelu
-};
-/** An ordered sequence of type of Post Ops */
-using PostOpTypeSequence = std::vector<PostOpType>;
-/** An elementwise n-ary operation that can be appended to and fused with (at kernel-level) other operators
- * It contains:
- * 1. The attributes of the original operator.
- * 2. Any additional tensor argument.
- * 3. The position of the previous op's dst tensor in its argument list ( @ref prev_dst_pos )
- *
- * For example, a series of chained ops:
- *
- * div(src1, relu(conv(src0, weights, bias, conv_info), act_info), div_info)
- *
- * translates to
- *
- * dst = conv(src0, weights, bias, conv_info) // main op
- * dst = relu(dst, act_info) // previous dst is placed in the first (and only) argument
- * dst = div(src1, dst, div_info) // previous dst is placed in the second argument
- *
- * which in turn translates to:
- *
- * main op: conv(src0, weights, bias, conv_info)
- * post op1: relu(act_info, prev_dst_pos = 0)
- * post op2: div(div_info, src1, prev_dst_pos = 1)
- *
- * @note: On Broadcasting
- * For n-ary post ops, the tensor arguments must not "widen" the dst tensor of the main op
- * For example, for a dst of shape [14, 1, 34]:
- * * post_op_arg1 = [1, 1, 34] is allowed: broadcast in dim 0
- * * post_op_arg1 = [14, 1, 34] is allowed: no broadcast
- * * post_op_arg1 = [1, 1, 34] is allowed: broadcast in dims 0 and 1
- * * post_op_arg1 = [14, 15, 34] is NOT allowed: broadcast widens the dst tensor
- *
- * @note: On Data layout
- * All post ops are data layout agnostic. This means post ops do not have an inherent idea of "width", "height" and so on.
- * Should we want to perform a post op with 2 tensors of different data layouts (where data layouts are significant to both),
- * then we need to perform necessary permutation op beforehand to unify their data layout before they can be fused with a post op
- *
- * Note although post ops themselves should be able to support any data layout, the main op they fuse to may impose
- * additional restrictions in the presence of post ops. For example, the implementation of a gemm op may only allow
- * NHWC data layout if post ops are provided. Such restrictions are main op implementation specific.
- *
- * @note: PostOps do not own any resources pointed to by TensorRelatedT if it's a pointer type
- * @note: If TensorRelatedT points to a resource, IPostOp assumes that resource is valid throughout its lifetime
- * and the lifetime of its copies. This is almost guaranteed as IPostOp is only meant to be used at configure time
- * after the ITensor or ITensorInfo objects are already constructed
- */
-template <typename TensorRelatedT>
-struct IPostOp
-{
- /** Get the arity of the post op
- * @note: that this is one fewer than the arity of the original op, because we implicitly pass the previous op's dst
- * tensor as one of the arguments
- */
- size_t arity() const
- {
- return arguments().size();
- }
- /** The position of previous op's dst in current op's argument list */
- virtual int prev_dst_pos() const = 0;
- /** The IPostOp type */
- virtual PostOpType type() const = 0;
- /** The argument tensors
- * The order of the argument tensor is strictly preserved
- */
- virtual std::vector<TensorRelatedT *> arguments() = 0;
- virtual std::vector<const TensorRelatedT *> arguments() const = 0;
- /** Clone method used in cases where PostOps are owned by unique_ptr
- * @note: This performs a shallow copy of the TensorRelatedT if TensorRelatedT points to a resource
- */
- virtual std::unique_ptr<IPostOp<TensorRelatedT>> clone() const = 0;
- virtual ~IPostOp()
- {
- }
-};
-
-/** A sequence of PostOps that can be appended to the end of other operators */
-template <typename TensorRelatedT>
-class PostOpList
-{
-public:
- /** Constructor */
- PostOpList() = default;
- /** Destructor */
- ~PostOpList() = default;
- PostOpList(const PostOpList &other)
- {
- for(const auto &op : other._post_ops)
- {
- this->_post_ops.push_back(op->clone());
- }
- }
- PostOpList &operator=(const PostOpList &other)
- {
- PostOpList tmp{ other };
- std::swap(tmp, *this);
- return *this;
- }
- PostOpList(PostOpList &&other) = default;
- PostOpList &operator=(PostOpList &&other) = default;
-
- /** Add a new post op at the end of the list */
- template <typename OpT, typename... Args>
- void push_back_op(Args &&... args)
- {
- _post_ops.push_back(std::make_unique<OpT>(std::forward<Args>(args)...));
- }
-
- /** Number of post ops */
- size_t size() const
- {
- return _post_ops.size();
- }
-
- /** Total number of post ops */
- size_t total_num_arguments() const
- {
- return std::accumulate(_post_ops.begin(), _post_ops.end(), 0, [](size_t op1_arity, const auto & op2)
- {
- return op1_arity + op2->arity();
- });
- }
-
- /** Get the underlying post op list */
- std::vector<std::unique_ptr<IPostOp<TensorRelatedT>>> &get_list()
- {
- return _post_ops;
- }
- const std::vector<std::unique_ptr<IPostOp<TensorRelatedT>>> &get_list() const
- {
- return _post_ops;
- }
-
-private:
- std::vector<std::unique_ptr<IPostOp<TensorRelatedT>>> _post_ops{};
-};
-
-} // namespace experimental
-} // namespace arm_compute
-#endif //ARM_COMPUTE_EXPERIMENTAL_IPOSTOP
diff --git a/arm_compute/core/experimental/PostOps.h b/arm_compute/core/experimental/PostOps.h
deleted file mode 100644
index a5585ba..0000000
--- a/arm_compute/core/experimental/PostOps.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2021, 2023 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef ARM_COMPUTE_EXPERIMENTAL_POSTOPS
-#define ARM_COMPUTE_EXPERIMENTAL_POSTOPS
-
-#include "arm_compute/core/experimental/IPostOp.h"
-
-#include "arm_compute/core/Types.h"
-#include "arm_compute/function_info/ActivationLayerInfo.h"
-
-#include <vector>
-
-namespace arm_compute
-{
-namespace experimental
-{
-/** (EXPERIMENTAL_POST_OPS)
- * Implementation of specific IPostOps
-*/
-
-template <typename TensorRelatedT>
-struct PostOpAct : public IPostOp<TensorRelatedT>
-{
-public:
- PostOpAct(const ActivationLayerInfo &act_info)
- : _act_info{ act_info }
- {
- }
- // NOTE: PostOps do not own any resources pointed to by TensorRelatedT if it's a pointer type, thus allow shallow copy
- ~PostOpAct() override = default;
- PostOpAct(const PostOpAct &) = default;
- PostOpAct &operator=(const PostOpAct &) = default;
- PostOpAct(PostOpAct &&) = default;
- PostOpAct &operator=(PostOpAct &&) = default;
-
- int prev_dst_pos() const override
- {
- return 0;
- }
- PostOpType type() const override
- {
- return PostOpType::Activation;
- }
- std::vector<TensorRelatedT *> arguments() override
- {
- return {};
- }
- std::vector<const TensorRelatedT *> arguments() const override
- {
- return {};
- }
- std::unique_ptr<IPostOp<TensorRelatedT>> clone() const override
- {
- return std::make_unique<PostOpAct<TensorRelatedT>>(*this);
- }
- ActivationLayerInfo _act_info;
-};
-
-template <typename TensorRelatedT>
-struct PostOpEltwiseAdd : public IPostOp<TensorRelatedT>
-{
-public:
- PostOpEltwiseAdd(TensorRelatedT addend, int prev_dst_pos, ConvertPolicy policy)
- : _addend{ addend },
- _prev_dst_pos{ prev_dst_pos },
- _policy{ policy }
- {
- }
- // NOTE: PostOps do not own any resources pointed to by TensorRelatedT if it's a pointer type, thus allow shallow copy
- ~PostOpEltwiseAdd() override = default;
- PostOpEltwiseAdd(const PostOpEltwiseAdd &) = default;
- PostOpEltwiseAdd &operator=(const PostOpEltwiseAdd &) = default;
- PostOpEltwiseAdd(PostOpEltwiseAdd &&) = default;
- PostOpEltwiseAdd &operator=(PostOpEltwiseAdd &&) = default;
- int prev_dst_pos() const override
- {
- return _prev_dst_pos;
- }
- PostOpType type() const override
- {
- return PostOpType::Eltwise_Add;
- }
- std::vector<TensorRelatedT *> arguments() override
- {
- return { &_addend };
- }
- std::vector<const TensorRelatedT *> arguments() const override
- {
- return { &_addend };
- }
- std::unique_ptr<IPostOp<TensorRelatedT>> clone() const override
- {
- return std::make_unique<PostOpEltwiseAdd<TensorRelatedT>>(*this);
- }
- TensorRelatedT _addend;
- int _prev_dst_pos;
- ConvertPolicy _policy;
-};
-
-template <typename TensorRelatedT>
-struct PostOpEltwisePRelu : public IPostOp<TensorRelatedT>
-{
-public:
- PostOpEltwisePRelu(TensorRelatedT alpha_param, int prev_dst_pos, ConvertPolicy policy)
- : _alpha_param{ alpha_param },
- _prev_dst_pos{ prev_dst_pos },
- _policy{ policy }
- {
- }
- // NOTE: PostOps do not own any resources pointed to by TensorRelatedT if it's a pointer type, thus allow shallow copy
- ~PostOpEltwisePRelu() override = default;
- PostOpEltwisePRelu(const PostOpEltwisePRelu &) = default;
- PostOpEltwisePRelu &operator=(const PostOpEltwisePRelu &) = default;
- PostOpEltwisePRelu(PostOpEltwisePRelu &&) = default;
- PostOpEltwisePRelu &operator=(PostOpEltwisePRelu &&) = default;
- int prev_dst_pos() const override
- {
- return _prev_dst_pos;
- }
- PostOpType type() const override
- {
- return PostOpType::Eltwise_PRelu;
- }
- std::vector<TensorRelatedT *> arguments() override
- {
- return { &_alpha_param };
- }
- std::vector<const TensorRelatedT *> arguments() const override
- {
- return { &_alpha_param };
- }
- std::unique_ptr<IPostOp<TensorRelatedT>> clone() const override
- {
- return std::make_unique<PostOpEltwisePRelu<TensorRelatedT>>(*this);
- }
- TensorRelatedT _alpha_param;
- int _prev_dst_pos;
- ConvertPolicy _policy;
-};
-} // namespace experimental
-} // namespace arm_compute
-#endif //ARM_COMPUTE_EXPERIMENTAL_POSTOPS
diff --git a/arm_compute/core/experimental/Types.h b/arm_compute/core/experimental/Types.h
index 1995ab0..8dd6812 100644
--- a/arm_compute/core/experimental/Types.h
+++ b/arm_compute/core/experimental/Types.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022 Arm Limited.
+ * Copyright (c) 2020-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_EXPERIMENTAL_TYPES_H
-#define ARM_COMPUTE_EXPERIMENTAL_TYPES_H
+#ifndef ACL_ARM_COMPUTE_CORE_EXPERIMENTAL_TYPES_H
+#define ACL_ARM_COMPUTE_CORE_EXPERIMENTAL_TYPES_H
#include "arm_compute/core/ITensorPack.h"
#include "arm_compute/core/TensorShape.h"
@@ -78,11 +78,6 @@
ACL_VEC_COL_SUM = ACL_SRC_4,
ACL_SHIFTS = ACL_SRC_5,
ACL_MULTIPLIERS = ACL_SRC_6,
-
- // (EXPERIMENTAL_POST_OPS) Post ops arguments begin after everything else
- EXPERIMENTAL_ACL_POST_OP_ARG = 2048,
- EXPERIMENTAL_ACL_POST_OP_ARG_FIRST = EXPERIMENTAL_ACL_POST_OP_ARG,
- EXPERIMENTAL_ACL_POST_OP_ARG_LAST = EXPERIMENTAL_ACL_POST_OP_ARG_FIRST + 1024, // Max number of post op arguments
};
namespace experimental
@@ -134,4 +129,4 @@
using MemoryRequirements = std::vector<MemoryInfo>;
} // namespace experimental
} // namespace arm_compute
-#endif /* ARM_COMPUTE_EXPERIMENTAL_TYPES_H */
+#endif // ACL_ARM_COMPUTE_CORE_EXPERIMENTAL_TYPES_H
diff --git a/arm_compute/function_info/GEMMInfo.h b/arm_compute/function_info/GEMMInfo.h
index daaf862..29a57a0 100644
--- a/arm_compute/function_info/GEMMInfo.h
+++ b/arm_compute/function_info/GEMMInfo.h
@@ -21,11 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO
-#define ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO
+#ifndef ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO_H
+#define ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO_H
#include "arm_compute/core/CoreTypes.h"
-#include "arm_compute/core/experimental/IPostOp.h"
#include "arm_compute/function_info/ActivationLayerInfo.h"
#include <vector>
@@ -79,7 +78,6 @@
_pretranspose_A(false),
_pretranspose_B(false),
_activation_info(),
- _post_ops(),
_fixed_format(false),
_weight_format(arm_compute::WeightFormat::UNSPECIFIED)
{
@@ -99,14 +97,12 @@
* @param[in] fast_math (Optional) Use a data type of shorter width to improve performance
* @param[in] broadcast_bias (Optional) Broadcast the shape of the bias tensor from a vector to a matrix.
* @param[in] activation_info (Optional) Activation to apply after the matrix multiplication
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
* @param[in] fixed_format (Optional) Specify the selection of fixed format kernels for variable weights support in GEMM. These kernels expect the weights tensor to be in amemory format that is fixed by the kernel itself. For more information, see arm_compute::WeightFormat.
* @param[in] weight_format (Optional) arm_gemm:WeightFormat enumeration requested by the user. Default is arm_compute::WeightFormat::UNSPECIFIED.
*/
GEMMInfo(bool is_a_reshaped, bool is_b_reshaped, bool reshape_b_only_on_first_run, int depth_output_gemm3d = 0, bool reinterpret_input_as_3d = false, bool retain_internal_weights = false,
GEMMLowpOutputStageInfo gemmlowp_output_stage = GEMMLowpOutputStageInfo(), bool fp_mixed_precision = false, bool fast_math = false, bool broadcast_bias = false,
- const ActivationLayerInfo &activation_info = ActivationLayerInfo(), const experimental::PostOpList<ITensorInfo *> &post_ops = experimental::PostOpList<ITensorInfo *>(),
- bool fixed_format = false, arm_compute::WeightFormat weight_format = arm_compute::WeightFormat::UNSPECIFIED) noexcept
+ const ActivationLayerInfo &activation_info = ActivationLayerInfo(), bool fixed_format = false, arm_compute::WeightFormat weight_format = arm_compute::WeightFormat::UNSPECIFIED) noexcept
: _is_a_reshaped(is_a_reshaped),
_is_b_reshaped(is_b_reshaped),
_reshape_b_only_on_first_run(reshape_b_only_on_first_run),
@@ -120,7 +116,6 @@
_pretranspose_A(false),
_pretranspose_B(false),
_activation_info(activation_info),
- _post_ops(post_ops),
_fixed_format(fixed_format),
_weight_format(weight_format)
{
@@ -271,22 +266,6 @@
{
_activation_info = activation_info;
}
- /** Post operations to apply after the matrix multiplication
- *
- * @return experimental::PostOpList object
- */
- const experimental::PostOpList<ITensorInfo *> &post_ops() const
- {
- return _post_ops;
- }
- /** Set post ops
- *
- * @param[in] post_ops experimental::PostOpList object to set
- */
- void set_post_ops(const experimental::PostOpList<ITensorInfo *> &post_ops)
- {
- _post_ops = post_ops;
- }
/** Flag which specifies if the GEMM operation is running fixed-format kernels.
*
* @return True if the GEMM operation is running fixed-format kernel else false.
@@ -320,22 +299,21 @@
}
private:
- bool _is_a_reshaped;
- bool _is_b_reshaped;
- bool _reshape_b_only_on_first_run;
- int _depth_output_gemm3d;
- bool _reinterpret_input_as_3d;
- bool _retain_internal_weights;
- GEMMLowpOutputStageInfo _gemmlowp_output_stage;
- bool _fast_math;
- bool _fp_mixed_precision;
- bool _broadcast_bias;
- bool _pretranspose_A;
- bool _pretranspose_B;
- ActivationLayerInfo _activation_info;
- experimental::PostOpList<ITensorInfo *> _post_ops;
- bool _fixed_format;
- arm_compute::WeightFormat _weight_format;
+ bool _is_a_reshaped;
+ bool _is_b_reshaped;
+ bool _reshape_b_only_on_first_run;
+ int _depth_output_gemm3d;
+ bool _reinterpret_input_as_3d;
+ bool _retain_internal_weights;
+ GEMMLowpOutputStageInfo _gemmlowp_output_stage;
+ bool _fast_math;
+ bool _fp_mixed_precision;
+ bool _broadcast_bias;
+ bool _pretranspose_A;
+ bool _pretranspose_B;
+ ActivationLayerInfo _activation_info;
+ bool _fixed_format;
+ arm_compute::WeightFormat _weight_format;
};
} //namespace arm_compute
-#endif /* ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO */
+#endif // ACL_ARM_COMPUTE_FUNCTION_INFO_GEMMINFO_H
diff --git a/arm_compute/graph/DataLayerVisitor.h b/arm_compute/graph/DataLayerVisitor.h
index ac7f1c8..11d9f1d 100644
--- a/arm_compute/graph/DataLayerVisitor.h
+++ b/arm_compute/graph/DataLayerVisitor.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_DATALAYERPRINTER_H
-#define ARM_COMPUTE_GRAPH_DATALAYERPRINTER_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_DATALAYERVISITOR_H
+#define ACL_ARM_COMPUTE_GRAPH_DATALAYERVISITOR_H
#include "arm_compute/graph/IGraphPrinter.h"
#include "arm_compute/graph/INodeVisitor.h"
@@ -48,7 +48,6 @@
void visit(ConvolutionLayerNode &n) override;
void visit(DepthwiseConvolutionLayerNode &n) override;
void visit(FusedConvolutionBatchNormalizationNode &n) override;
- void visit(FusedConvolutionBatchNormalizationWithPostOpsNode &n) override;
void visit(FusedDepthwiseConvolutionBatchNormalizationNode &n) override;
void visit(OutputNode &n) override;
@@ -59,4 +58,4 @@
};
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_DATALAYERPRINTER_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_DATALAYERVISITOR_H
diff --git a/arm_compute/graph/INode.h b/arm_compute/graph/INode.h
index becd672..5646ea8 100644
--- a/arm_compute/graph/INode.h
+++ b/arm_compute/graph/INode.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019,2021 Arm Limited.
+ * Copyright (c) 2018-2019,2021,2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_INODE_H
-#define ARM_COMPUTE_GRAPH_INODE_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_INODE_H
+#define ACL_ARM_COMPUTE_GRAPH_INODE_H
#include "arm_compute/core/Error.h"
#include "arm_compute/graph/LayerDescriptors.h"
@@ -241,30 +241,19 @@
* @return Assigned target of this node
*/
Target assigned_target() const;
- /** Post operator info list
- *
- * @return Post operator info list
- */
- const std::list<std::unique_ptr<ConvPostOpInfo>> &post_op_info_list() const;
- /** Post operator info list
- *
- * @return Post operator info list
- */
- std::list<std::unique_ptr<ConvPostOpInfo>> &post_op_info_list();
protected:
friend class Graph;
protected:
- Graph *_graph; /**< Backward reference to graph owning the node */
- NodeID _id; /**< Node ID */
- NodeParams _common_params; /**< Node common params */
- std::vector<TensorID> _outputs; /**< Output of the node */
- std::vector<EdgeID> _input_edges; /**< Inputs edge set */
- std::set<EdgeID> _output_edges; /**< Output edge set */
- Target _assigned_target; /**< Assigned target by the Graph executor */
- std::list<std::unique_ptr<ConvPostOpInfo>> _post_op_info_list; /**< Post operator info list */
+ Graph *_graph; /**< Backward reference to graph owning the node */
+ NodeID _id; /**< Node ID */
+ NodeParams _common_params; /**< Node common params */
+ std::vector<TensorID> _outputs; /**< Output of the node */
+ std::vector<EdgeID> _input_edges; /**< Inputs edge set */
+ std::set<EdgeID> _output_edges; /**< Output edge set */
+ Target _assigned_target; /**< Assigned target by the Graph executor */
};
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_INODE_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_INODE_H
diff --git a/arm_compute/graph/INodeVisitor.h b/arm_compute/graph/INodeVisitor.h
index 97e9533..efe191a 100644
--- a/arm_compute/graph/INodeVisitor.h
+++ b/arm_compute/graph/INodeVisitor.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_INODEVISITOR_H
-#define ARM_COMPUTE_GRAPH_INODEVISITOR_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_INODEVISITOR_H
+#define ACL_ARM_COMPUTE_GRAPH_INODEVISITOR_H
#include "arm_compute/graph/nodes/NodesFwd.h"
@@ -106,16 +106,6 @@
* @param[in] n Node to visit.
*/
virtual void visit(FusedConvolutionBatchNormalizationNode &n) = 0;
- /** Visit FusedConvolutionBatchNormalizationWithPostOpsNode.
- *
- * @param[in] n Node to visit.
- */
- virtual void visit(FusedConvolutionBatchNormalizationWithPostOpsNode &n) = 0;
- /** Visit FusedConvolutionWithPostOpNode.
- *
- * @param[in] n Node to visit.
- */
- virtual void visit(FusedConvolutionWithPostOpNode &n) = 0;
/** Visit FusedDepthwiseConvolutionBatchNormalizationNode.
*
* @param[in] n Node to visit.
@@ -215,8 +205,6 @@
virtual void visit(FlattenLayerNode &n) override;
virtual void visit(FullyConnectedLayerNode &n) override;
virtual void visit(FusedConvolutionBatchNormalizationNode &n) override;
- virtual void visit(FusedConvolutionBatchNormalizationWithPostOpsNode &n) override;
- virtual void visit(FusedConvolutionWithPostOpNode &n) override;
virtual void visit(FusedDepthwiseConvolutionBatchNormalizationNode &n) override;
virtual void visit(InputNode &n) override;
virtual void visit(NormalizationLayerNode &n) override;
@@ -240,4 +228,4 @@
};
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_INODEVISITOR_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_INODEVISITOR_H
diff --git a/arm_compute/graph/TypePrinter.h b/arm_compute/graph/TypePrinter.h
index 8f97bbf..9df4eba 100644
--- a/arm_compute/graph/TypePrinter.h
+++ b/arm_compute/graph/TypePrinter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_TYPE_PRINTER_H
-#define ARM_COMPUTE_GRAPH_TYPE_PRINTER_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_TYPEPRINTER_H
+#define ACL_ARM_COMPUTE_GRAPH_TYPEPRINTER_H
#include "arm_compute/core/Error.h"
#include "arm_compute/core/Types.h"
@@ -116,12 +116,6 @@
case NodeType::FusedConvolutionBatchNormalizationLayer:
os << "FusedConvolutionBatchNormalizationLayer";
break;
- case NodeType::FusedConvolutionBatchNormalizationLayerWithPostOpsLayer:
- os << "FusedConvolutionBatchNormalizationLayerWithPostOpsLayer";
- break;
- case NodeType::FusedConvolutionWithPostOp:
- os << "FusedConvolutionWithPostOp";
- break;
case NodeType::FusedDepthwiseConvolutionBatchNormalizationLayer:
os << "FusedDepthwiseConvolutionBatchNormalizationLayer";
break;
@@ -295,4 +289,4 @@
}
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_TYPE_PRINTER_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_TYPEPRINTER_H
diff --git a/arm_compute/graph/Types.h b/arm_compute/graph/Types.h
index 167f738..8d49340 100644
--- a/arm_compute/graph/Types.h
+++ b/arm_compute/graph/Types.h
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_TYPES_H
-#define ARM_COMPUTE_GRAPH_TYPES_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_TYPES_H
+#define ACL_ARM_COMPUTE_GRAPH_TYPES_H
#include "arm_compute/core/Error.h"
#include "arm_compute/core/PixelValue.h"
@@ -41,32 +41,31 @@
{
namespace graph
{
-using arm_compute::CLTunerMode;
using arm_compute::CLBackendType;
+using arm_compute::CLTunerMode;
using arm_compute::Status;
using arm_compute::Coordinates;
-using arm_compute::DataType;
using arm_compute::DataLayout;
using arm_compute::DataLayoutDimension;
-using arm_compute::TensorShape;
-using arm_compute::Size2D;
+using arm_compute::DataType;
using arm_compute::PermutationVector;
using arm_compute::PixelValue;
+using arm_compute::Size2D;
+using arm_compute::TensorShape;
using arm_compute::ActivationLayerInfo;
using arm_compute::DetectionOutputLayerInfo;
using arm_compute::DetectionPostProcessLayerInfo;
-using arm_compute::NormType;
-using arm_compute::NormalizationLayerInfo;
+using arm_compute::DimensionRoundingType;
using arm_compute::FullyConnectedLayerInfo;
+using arm_compute::InterpolationPolicy;
+using arm_compute::NormalizationLayerInfo;
+using arm_compute::NormType;
using arm_compute::PadStrideInfo;
using arm_compute::PoolingLayerInfo;
using arm_compute::PoolingType;
using arm_compute::PriorBoxLayerInfo;
-using arm_compute::DimensionRoundingType;
-using arm_compute::InterpolationPolicy;
-using arm_compute::experimental::PostOpType;
using GraphID = unsigned int;
using TensorID = unsigned int;
@@ -150,55 +149,6 @@
Disabled, /**< Fast math disabled for Convolution layer */
};
-/** Convolution post operator info */
-class ConvPostOpInfo
-{
-public:
- /** Returns post op type
- *
- * @return Post op type
- */
- virtual PostOpType type() const = 0;
- virtual ~ConvPostOpInfo()
- {
- }
-};
-
-class ConvPostOpInfoActivation : public ConvPostOpInfo
-{
-public:
- ConvPostOpInfoActivation(const ActivationLayerInfo &act)
- : _act(act)
- {
- }
- ~ConvPostOpInfoActivation() override
- {
- }
- PostOpType type() const override
- {
- return PostOpType::Activation;
- }
- ActivationLayerInfo _act;
-};
-
-class ConvPostOpInfoEltwiseAdd : public ConvPostOpInfo
-{
-public:
- ConvPostOpInfoEltwiseAdd(int arg_pos, const ConvertPolicy &policy)
- : _prev_op_dst_pos(arg_pos), _policy(policy)
- {
- }
- PostOpType type() const override
- {
- return PostOpType::Eltwise_Add;
- }
- ~ConvPostOpInfoEltwiseAdd() override
- {
- }
- int _prev_op_dst_pos;
- ConvertPolicy _policy;
-};
-
/** Supported nodes */
enum class NodeType
{
@@ -219,8 +169,6 @@
FlattenLayer,
FullyConnectedLayer,
FusedConvolutionBatchNormalizationLayer,
- FusedConvolutionWithPostOp,
- FusedConvolutionBatchNormalizationLayerWithPostOpsLayer,
FusedDepthwiseConvolutionBatchNormalizationLayer,
GenerateProposalsLayer,
L2NormalizeLayer,
@@ -278,4 +226,4 @@
};
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_TYPES_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_TYPES_H
diff --git a/arm_compute/graph/backends/FunctionHelpers.h b/arm_compute/graph/backends/FunctionHelpers.h
index 803283e..a567427 100644
--- a/arm_compute/graph/backends/FunctionHelpers.h
+++ b/arm_compute/graph/backends/FunctionHelpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,18 +21,15 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_FUNCTION_HELPERS_H
-#define ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_FUNCTION_HELPERS_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_BACKENDS_FUNCTIONHELPERS_H
+#define ACL_ARM_COMPUTE_GRAPH_BACKENDS_FUNCTIONHELPERS_H
-#include "arm_compute/core/experimental/IPostOp.h"
-#include "arm_compute/core/experimental/PostOps.h"
#include "arm_compute/graph/Logger.h"
#include "arm_compute/graph/Tensor.h"
#include "arm_compute/graph/TypePrinter.h"
#include "arm_compute/graph/Types.h"
#include "arm_compute/graph/Utils.h"
#include "arm_compute/graph/backends/FusedConvolutionBatchNormalizationFunction.h"
-#include "arm_compute/graph/backends/FusedConvolutionBatchNormalizationWithPostOpsFunction.h"
#include "arm_compute/graph/backends/FusedDepthwiseConvolutionBatchNormalizationFunction.h"
#include "arm_compute/graph/backends/Utils.h"
#include "arm_compute/graph/nodes/Nodes.h"
@@ -541,183 +538,6 @@
return std::move(func);
}
-/** Create a backend convolution layer function with post operator
- *
- * @tparam ConvolutionLayerFunctions Backend convolution functions
- * @tparam TargetInfo Target-specific information
- *
- * @param[in] node Node to create the backend function for
- * @param[in] ctx Graph context
- *
- * @return Backend convolution layer function
- */
-template <typename ConvolutionLayerFunctions, typename TargetInfo>
-std::unique_ptr<IFunction> create_fused_convolution_with_post_op(FusedConvolutionWithPostOpNode &node, GraphContext &ctx)
-{
- validate_node<TargetInfo>(node, 4 /* expected inputs */, 1 /* expected outputs */);
-
- // Extract IO and info
- typename TargetInfo::TensorType *input = get_backing_tensor<TargetInfo>(node.input(0));
- typename TargetInfo::TensorType *weights = get_backing_tensor<TargetInfo>(node.input(1));
- typename TargetInfo::TensorType *biases = get_backing_tensor<TargetInfo>(node.input(2));
- typename TargetInfo::TensorType *output = get_backing_tensor<TargetInfo>(node.output(0));
-
- const bool is_quantized = is_data_type_quantized_asymmetric(input->info()->data_type());
-
- if(is_quantized)
- {
- biases->info()->set_data_type(DataType::S32);
- }
-
- const PadStrideInfo conv_info = node.convolution_info();
- const unsigned int num_groups = node.num_groups();
- const ActivationLayerInfo fused_act = node.fused_activation();
-
- experimental::PostOpList<typename TargetInfo::TensorType *> post_ops;
-
- auto &post_op_info_list = node.post_op_info_list();
- for(const auto &post_op_info : post_op_info_list)
- {
- switch(post_op_info->type())
- {
- case PostOpType::Activation:
- {
- const auto act_info = utils::cast::polymorphic_downcast<const ConvPostOpInfoActivation *>(post_op_info.get());
- post_ops.template push_back_op<experimental::PostOpAct<typename TargetInfo::TensorType *>>(act_info->_act);
- break;
- }
- case PostOpType::Eltwise_Add:
- {
- typename TargetInfo::TensorType *add_input = get_backing_tensor<TargetInfo>(node.input(3));
- const auto eltwise_info = utils::cast::polymorphic_downcast<const ConvPostOpInfoEltwiseAdd *>(post_op_info.get());
- post_ops.template push_back_op<experimental::PostOpEltwiseAdd<typename TargetInfo::TensorType *>>(add_input, eltwise_info->_prev_op_dst_pos, eltwise_info->_policy);
- break;
- }
- default:
- {
- ARM_COMPUTE_ERROR("Unsupported PostOpType");
- }
- }
- }
-
- // Create and configure function (we assume that functions have been validated before creation)
- std::shared_ptr<IMemoryManager> mm = get_memory_manager(ctx, TargetInfo::TargetType);
- std::unique_ptr<IFunction> func;
- std::string func_name;
-
- // Fuse convolution with post ops is only supported for conv1x1, which is only implemented as gemmconv2d
- std::tie(func, func_name) = create_named_memory_managed_function<typename ConvolutionLayerFunctions::GEMMConvolutionLayer>(
- std::string("GEMMConvolutionLayer"), mm,
- input, weights, biases, output, conv_info,
- WeightsInfo(), Size2D(1U, 1U), fused_act, num_groups, post_ops);
-
- // Log info
- std::ostringstream qss;
- if(is_quantized)
- {
- qss << " Input QuantInfo: " << input->info()->quantization_info()
- << " Weights QuantInfo: " << weights->info()->quantization_info()
- << " Output QuantInfo: " << output->info()->quantization_info();
- }
- ARM_COMPUTE_LOG_GRAPH_INFO("Instantiated "
- << node.name()
- << " Type: " << func_name
- << " Target: " << TargetInfo::TargetType
- << " Data Type: " << input->info()->data_type()
- << " Groups: " << num_groups
- << " Input shape: " << input->info()->tensor_shape()
- << " Weights shape: " << weights->info()->tensor_shape()
- << " Output shape: " << output->info()->tensor_shape()
- << qss.str()
- << (fused_act.enabled() ? " " + to_string(fused_act.activation()) : "")
- << " Post ops" << post_ops
- << std::endl);
- return std::move(func);
-}
-
-/** Create a backend convolution batch normalization layer function with post operator
- *
- * @tparam FusedLayerTypes Backend convolution functions
- * @tparam TargetInfo Target-specific information
- *
- * @param[in] node Node to create the backend function for
- * @param[in] ctx Graph context
- *
- * @return Backend fused convolution with batch normalization layer function
- */
-template <typename FusedLayerTypes, typename TargetInfo>
-std::unique_ptr<IFunction> create_fused_convolution_batch_normalization_with_post_op(FusedConvolutionBatchNormalizationWithPostOpsNode &node, GraphContext &ctx)
-{
- validate_node<TargetInfo>(node, 8 /* expected inputs */, 1 /* expected outputs */);
-
- // Extract IO and info
- typename TargetInfo::TensorType *input = get_backing_tensor<TargetInfo>(node.input(0));
- typename TargetInfo::TensorType *weights = get_backing_tensor<TargetInfo>(node.input(1));
- typename TargetInfo::TensorType *biases = get_backing_tensor<TargetInfo>(node.input(2));
- typename TargetInfo::TensorType *mean = get_backing_tensor<TargetInfo>(node.input(3));
- typename TargetInfo::TensorType *var = get_backing_tensor<TargetInfo>(node.input(4));
- typename TargetInfo::TensorType *beta = get_backing_tensor<TargetInfo>(node.input(5));
- typename TargetInfo::TensorType *gamma = get_backing_tensor<TargetInfo>(node.input(6));
-
- typename TargetInfo::TensorType *output = get_backing_tensor<TargetInfo>(node.output(0));
-
- const PadStrideInfo conv_info = node.convolution_info();
- const unsigned int num_groups = node.num_groups();
- const bool fast_math = node.fast_math_hint() == FastMathHint::Enabled;
- const float epsilon = node.epsilon();
-
- experimental::PostOpList<typename TargetInfo::TensorType *> post_ops;
-
- auto &post_op_info_list = node.post_op_info_list();
- for(const auto &post_op_info : post_op_info_list)
- {
- switch(post_op_info->type())
- {
- case PostOpType::Activation:
- {
- const auto act_info = utils::cast::polymorphic_downcast<const ConvPostOpInfoActivation *>(post_op_info.get());
- post_ops.template push_back_op<experimental::PostOpAct<typename TargetInfo::TensorType *>>(act_info->_act);
- break;
- }
- case PostOpType::Eltwise_Add:
- {
- typename TargetInfo::TensorType *add_input = get_backing_tensor<TargetInfo>(node.input(3));
- const auto eltwise_info = utils::cast::polymorphic_downcast<const ConvPostOpInfoEltwiseAdd *>(post_op_info.get());
- post_ops.template push_back_op<experimental::PostOpEltwiseAdd<typename TargetInfo::TensorType *>>(add_input, eltwise_info->_prev_op_dst_pos, eltwise_info->_policy);
- break;
- }
- default:
- {
- ARM_COMPUTE_ERROR("Unsupported PostOpType");
- }
- }
- }
-
- // Create and configure function (we assume that functions have been validated before creation)
- std::shared_ptr<IMemoryManager> mm = get_memory_manager(ctx, TargetInfo::TargetType);
- std::unique_ptr<IFunction> func;
- std::string func_name;
-
- using FType = FusedConvolutionBatchNormalizationWithPostOpsFunction<TargetInfo, FusedLayerTypes>;
-
- // Create and configure function
- std::tie(func, func_name) = create_named_memory_managed_function<FType>(
- std::string("FusedConvolutionBatchNormalizationLayerWithPostOpsLayer"), mm, input, weights, biases, output, mean, var, beta, gamma, epsilon, conv_info, num_groups, fast_math, post_ops);
-
- // Log info
- ARM_COMPUTE_LOG_GRAPH_INFO("Instantiated "
- << node.name()
- << " Type: " << node.type()
- << " Target: " << TargetInfo::TargetType
- << " Data Type: " << input->info()->data_type()
- << " Input shape: " << input->info()->tensor_shape()
- << " Weights shape: " << weights->info()->tensor_shape()
- << " Output shape: " << output->info()->tensor_shape()
- << " Post Ops:" << post_ops
- << std::endl);
- return std::move(func);
-}
-
/** Create a backend deconvolution layer function
*
* @tparam DeconvolutionLayerFunction Backend deconvolution function
@@ -2025,4 +1845,4 @@
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_FUNCTION_HELPERS_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_BACKENDS_FUNCTIONHELPERS_H
diff --git a/arm_compute/graph/backends/FusedConvolutionBatchNormalizationWithPostOpsFunction.h b/arm_compute/graph/backends/FusedConvolutionBatchNormalizationWithPostOpsFunction.h
deleted file mode 100644
index 10f2e5c..0000000
--- a/arm_compute/graph/backends/FusedConvolutionBatchNormalizationWithPostOpsFunction.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef ARM_COMPUTE_GRAPH_BACKENDS_FUSED_CONVOLUTION_BATCH_NORMAZLIZATION_WITH_POST_OPS_FUNCTION_H
-#define ARM_COMPUTE_GRAPH_BACKENDS_FUSED_CONVOLUTION_BATCH_NORMAZLIZATION_WITH_POST_OPS_FUNCTION_H
-
-#include "arm_compute/core/Types.h"
-#include "arm_compute/core/experimental/IPostOp.h"
-#include "arm_compute/runtime/IFunction.h"
-
-namespace arm_compute
-{
-namespace graph
-{
-namespace backends
-{
-/** Wrapper function to first apply {NE, CL}BatchNormalizationLayer on the weights and then run {NE, CL}ConvolutionLayer with the modified weights */
-template <typename TargetInfo, typename FusedLayerTypes>
-class FusedConvolutionBatchNormalizationWithPostOpsFunction : public IFunction
-{
-public:
- using TensorType = typename TargetInfo::TensorType;
- using TensorConcreteType = typename TargetInfo::TensorConcreteType;
-
- FusedConvolutionBatchNormalizationWithPostOpsFunction(std::shared_ptr<IMemoryManager> memory_manager = nullptr)
- : _conv_layer(memory_manager), _fused_batch_norm_layer(), _fused_bias(), _is_prepared(false)
- {
- }
-
- /** Set the input and output tensors.
- *
- * @param[in] input Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
- * while every optional dimension from 4 and above represent a batch of inputs.
- * Data types supported: QASYMM8/F16/F32.
- * @param[in] weights Weights tensor. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. Data type supported: Same as @p input.
- * @param[in] bias Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM].
- * Data type supported: Should match @p input data type.
- * @param[out] output Destination tensor. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs.
- * Data types supported: Same as @p input.
- * @param[in] mean Mean values tensor. 1 dimension with size equal to the feature maps [FM]. Data types supported: Same as @p input
- * @param[in] var Variance values tensor. 1 dimension with size equal to the feature maps [FM]. Data types supported: Same as @p input
- * @param[in] beta Beta values tensor info. 1 dimension with size equal to the feature maps [FM]. If not provided, default value for beta is 0. Data types supported: Same as @p input
- * @param[in] gamma Gamma values tensor info. 1 dimension with size equal to the feature maps [FM]. If not provided, default value for gamma is 1. Data types supported: Same as @p input
- * @param[in] epsilon Small value to avoid division with zero. Default value is 0.001f.
- * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
- * @param[in] num_groups Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] fast_math Enable fast math computation. In case this flag were set, the function could dispatch the fastest implementation
- * available which may introduce a drop of accuracy as well. Default is false
- * @param[in] post_ops A sequence of post operations that are performed after the main operation.
- *
- */
- void configure(TensorType *input,
- TensorType *weights,
- TensorType *bias,
- TensorType *output,
- const TensorType *mean,
- const TensorType *var,
- const TensorType *beta,
- const TensorType *gamma,
- float epsilon, const PadStrideInfo &conv_info, unsigned int num_groups, bool fast_math,
- const arm_compute::experimental::PostOpList<TensorType *> &post_ops = experimental::PostOpList<TensorType *> {})
- {
- // We don't run any validate, as we assume that the layers have been already validated
- const bool has_bias = (bias != nullptr);
- const TensorType *bias_to_use;
-
- // We check if the layer has a bias. If yes, use it in-place. If not, we need to create one
- // as batch normalization might end up with a bias != 0
- if(has_bias)
- {
- _fused_batch_norm_layer.configure(weights, mean, var, nullptr, nullptr, bias, beta, gamma, epsilon);
- bias_to_use = bias;
- }
- else
- {
- _fused_batch_norm_layer.configure(weights, mean, var, nullptr, &_fused_bias, nullptr, beta, gamma, epsilon);
- bias_to_use = &_fused_bias;
- }
-
- ActivationLayerInfo fused_act = ActivationLayerInfo(); // Passing an empty ActivationLayerInfo.
- _conv_layer.configure(input, weights, bias_to_use, output, conv_info, WeightsInfo(), Size2D(1U, 1U), fused_act, fast_math, num_groups, post_ops);
-
- if(!has_bias)
- {
- _fused_bias.allocator()->allocate();
- }
- }
-
- // Inherited methods overridden:
- void run()
- {
- prepare();
- _conv_layer.run();
- }
-
- void prepare()
- {
- if(!_is_prepared)
- {
- _fused_batch_norm_layer.run();
- _is_prepared = true;
- }
- }
-
-private:
- typename FusedLayerTypes::ConvolutionLayer _conv_layer;
- typename FusedLayerTypes::FuseBatchNormalization _fused_batch_norm_layer;
- TensorConcreteType _fused_bias;
- bool _is_prepared;
-};
-} // namespace backends
-} // namespace graph
-} // namespace arm_compute
-
-#endif /* ARM_COMPUTE_GRAPH_BACKENDS_FUSED_CONVOLUTION_BATCH_NORMAZLIZATION_WITH_POST_OPS_FUNCTION_H */
diff --git a/arm_compute/graph/backends/ValidateHelpers.h b/arm_compute/graph/backends/ValidateHelpers.h
index 89dccd8..71a6201 100644
--- a/arm_compute/graph/backends/ValidateHelpers.h
+++ b/arm_compute/graph/backends/ValidateHelpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_VALIDATE_HELPERS_H
-#define ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_VALIDATE_HELPERS_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_BACKENDS_VALIDATEHELPERS_H
+#define ACL_ARM_COMPUTE_GRAPH_BACKENDS_VALIDATEHELPERS_H
#include "arm_compute/graph/Logger.h"
#include "arm_compute/graph/Tensor.h"
@@ -183,42 +183,6 @@
return status;
}
-/** Validates a Convolution layer node
- *
- * @tparam GEMMConvolutionLayer GEMM Convolution layer function type
- *
- * @param[in] node Node to validate
- *
- * @return Status
- */
-template <typename GEMMConvolutionLayer>
-Status validate_fused_convolution_with_post_op(FusedConvolutionWithPostOpNode &node)
-{
- ARM_COMPUTE_LOG_GRAPH_VERBOSE("Validating fused ConvolutionLayer node with ID : " << node.id() << " and Name: " << node.name() << std::endl);
- ARM_COMPUTE_RETURN_ERROR_ON(node.num_inputs() != 4);
- ARM_COMPUTE_RETURN_ERROR_ON(node.num_outputs() != 1);
-
- // Extract IO and info
- arm_compute::ITensorInfo *input = get_backing_tensor_info(node.input(0));
- arm_compute::ITensorInfo *weights = get_backing_tensor_info(node.input(1));
- arm_compute::ITensorInfo *biases = get_backing_tensor_info(node.input(2));
- arm_compute::ITensorInfo *output = get_backing_tensor_info(node.output(0));
-
- if(is_data_type_quantized_asymmetric(input->data_type()))
- {
- biases->set_data_type(DataType::S32);
- }
-
- const PadStrideInfo conv_info = node.convolution_info();
- //const ConvolutionMethod conv_algorithm = node.convolution_method();
- //const bool fast_math = node.fast_math_hint() == FastMathHint::Enabled;
- const unsigned int num_groups = node.num_groups();
-
- // Validate function
- return GEMMConvolutionLayer::validate(input, weights, biases, output, conv_info,
- WeightsInfo(), Size2D(1, 1), ActivationLayerInfo(), num_groups);
-}
-
/** Validates a Depthwise Convolution layer node
*
* @tparam DepthwiseConvolutionLayer Default Depthwise Convolution layer type
@@ -775,4 +739,4 @@
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_BACKENDS_DETAIL_VALIDATE_HELPERS_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_BACKENDS_VALIDATEHELPERS_H
diff --git a/arm_compute/graph/nodes/FusedConvolutionBatchNormalizationWithPostOpsNode.h b/arm_compute/graph/nodes/FusedConvolutionBatchNormalizationWithPostOpsNode.h
deleted file mode 100644
index a42e06d..0000000
--- a/arm_compute/graph/nodes/FusedConvolutionBatchNormalizationWithPostOpsNode.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef ARM_COMPUTE_GRAPH_FUSED_CONVOLUTION_BATCH_NORMALIZATION_WITH_POST_OPS_NODE_H
-#define ARM_COMPUTE_GRAPH_FUSED_CONVOLUTION_BATCH_NORMALIZATION_WITH_POST_OPS_NODE_H
-
-#include "arm_compute/graph/INode.h"
-
-namespace arm_compute
-{
-namespace graph
-{
-/** Batch Normalization node */
-class FusedConvolutionBatchNormalizationWithPostOpsNode final : public INode
-{
-public:
- /** Constructor
- *
- * @param[in] epsilon Epsilon parameter.
- * @param[in] info Convolution layer attributes.
- * @param[in] num_groups (Optional) Number of groups (Defaults to 1)
- * @param[in] method (Optional) Convolution method to use
- * @param[in] fast_math_hint (Optional) Fast math hint
- */
- FusedConvolutionBatchNormalizationWithPostOpsNode(float epsilon, PadStrideInfo info,
- unsigned int num_groups = 1,
- ConvolutionMethod method = ConvolutionMethod::Default,
- FastMathHint fast_math_hint = FastMathHint::Disabled);
-
- /** Epsilon parameter accessor
- *
- * @return Epsilon parameter
- */
- float epsilon() const;
-
- /** Computes convolution output descriptor
- *
- * @param[in] input_descriptor Input descriptor
- * @param[in] weights_descriptor Weights descriptor
- * @param[in] info Convolution operation attributes
- *
- * @return Output descriptor
- */
- static TensorDescriptor compute_output_descriptor(const TensorDescriptor &input_descriptor,
- const TensorDescriptor &weights_descriptor,
- const PadStrideInfo &info);
-
- /** Sets the convolution layer method to use
- *
- * @param[in] method Method to use for convolution
- */
- void set_convolution_method(ConvolutionMethod method);
-
- /** Number of groups in convolution accessor
- *
- * @return Number of groups in convolution
- */
- unsigned int num_groups() const;
-
- /** Convolution layer method accessor
- *
- * @note This is an indication on which convolution layer implementation to use,
- * if it fails to be created the library's heuristic approach will be used
- *
- * @return Convolution layer method to be used by the node
- */
- ConvolutionMethod convolution_method() const;
-
- /** Sets the fast math hint
- *
- * @param[in] hint Hint to use for convolution
- */
- void set_fast_math_hint(FastMathHint hint);
-
- /** Fast math hint accessor
- *
- * @return Fast math hint to be used by the node
- */
- FastMathHint fast_math_hint() const;
-
- /** Convolution metadata accessor
- *
- * @return Convolution information
- */
- PadStrideInfo convolution_info() const;
-
- // Inherited overridden methods:
- NodeType type() const override;
- bool forward_descriptors() override;
- TensorDescriptor configure_output(size_t idx) const override;
- void accept(INodeVisitor &v) override;
-
-public:
- static constexpr NodeType node_type = NodeType::FusedConvolutionBatchNormalizationLayerWithPostOpsLayer;
-
-private:
- float _epsilon;
-
- PadStrideInfo _info;
- unsigned int _num_groups;
- ConvolutionMethod _method;
- FastMathHint _fast_math_hint;
-};
-
-} // namespace graph
-} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_BATCH_NORMALIZATION_LAYER_NODE_H */
diff --git a/arm_compute/graph/nodes/FusedConvolutionWithPostOpNode.h b/arm_compute/graph/nodes/FusedConvolutionWithPostOpNode.h
deleted file mode 100644
index 6048994..0000000
--- a/arm_compute/graph/nodes/FusedConvolutionWithPostOpNode.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef ARM_COMPUTE_GRAPH_FUSED_CONVOLUTION_WITH_POST_OP_NODE_H
-#define ARM_COMPUTE_GRAPH_FUSED_CONVOLUTION_WITH_POST_OP_NODE_H
-
-#include "arm_compute/graph/INode.h"
-
-#include <list>
-
-namespace arm_compute
-{
-namespace graph
-{
-/** Convolution node */
-class FusedConvolutionWithPostOpNode final : public INode
-{
-public:
- /** Constructor
- *
- * @param[in] info Convolution layer attributes
- * @param[in] num_groups (Optional) Number of groups (Defaults to 1)
- * @param[in] method (Optional) Convolution method to use
- * @param[in] fast_math_hint (Optional) Fast math hint
- * @param[in] out_quant_info (Optional) Output quantization info
- */
- FusedConvolutionWithPostOpNode(PadStrideInfo info,
- unsigned int num_groups = 1,
- ConvolutionMethod method = ConvolutionMethod::Default,
- FastMathHint fast_math_hint = FastMathHint::Disabled,
- QuantizationInfo out_quant_info = QuantizationInfo());
- /** Sets the convolution layer method to use
- *
- * @param[in] method Method to use for convolution
- */
- void set_convolution_method(ConvolutionMethod method);
- /** Convolution layer method accessor
- *
- * @note This is an indication on which convolution layer implementation to use,
- * if it fails to be created the library's heuristic approach will be used
- *
- * @return Convolution layer method to be used by the node
- */
- ConvolutionMethod convolution_method() const;
- /** Sets the fast math fast hint
- *
- * @param[in] hint Hint to use for convolution
- */
- void set_fast_math_hint(FastMathHint hint);
- /** Fast math hint accessor
- *
- * @return Fast math hint to be used by the node
- */
- FastMathHint fast_math_hint() const;
- /** Convolution metadata accessor
- *
- * @return Convolution information
- */
- PadStrideInfo convolution_info() const;
- /** Number of groups in convolution accessor
- *
- * @return Number of groups in convolution
- */
- unsigned int num_groups() const;
- /** Returns fused activation
- *
- * @return Fused activation
- */
- ActivationLayerInfo fused_activation() const;
- /** Sets fused activation
- *
- * @param[in] fused_activation Fused activation to set
- */
- void set_fused_activation(ActivationLayerInfo fused_activation);
- /** Sets convolution info
- *
- * @param[in] info Convolution info to set
- */
- void set_convolution_info(PadStrideInfo info);
- /** Computes convolution output descriptor
- *
- * @param[in] input_descriptor Input descriptor
- * @param[in] weights_descriptor Weights descriptor
- * @param[in] info Convolution operation attributes
- *
- * @return Output descriptor
- */
- static TensorDescriptor compute_output_descriptor(const TensorDescriptor &input_descriptor,
- const TensorDescriptor &weights_descriptor,
- const PadStrideInfo &info);
-
- // Inherited overridden methods:
- NodeType type() const override;
- bool forward_descriptors() override;
- TensorDescriptor configure_output(size_t idx) const override;
- void accept(INodeVisitor &v) override;
-
-public:
- static constexpr NodeType node_type = NodeType::FusedConvolutionWithPostOp;
-
-private:
- PadStrideInfo _info;
- unsigned int _num_groups;
- ConvolutionMethod _method;
- FastMathHint _fast_math_hint;
- QuantizationInfo _out_quant_info;
- ActivationLayerInfo _fused_activation;
-};
-} // namespace graph
-} // namespace arm_compute
-
-#endif /* ARM_COMPUTE_GRAPH_FUSED_CONVOLUTION_WITH_POST_OP_NODE_H */
diff --git a/arm_compute/graph/nodes/Nodes.h b/arm_compute/graph/nodes/Nodes.h
index 3887eae..ae9f177 100644
--- a/arm_compute/graph/nodes/Nodes.h
+++ b/arm_compute/graph/nodes/Nodes.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_NODES_H
-#define ARM_COMPUTE_GRAPH_NODES_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_NODES_NODES_H
+#define ACL_ARM_COMPUTE_GRAPH_NODES_NODES_H
#include "arm_compute/graph/nodes/ActivationLayerNode.h"
#include "arm_compute/graph/nodes/ArgMinMaxLayerNode.h"
@@ -43,8 +43,6 @@
#include "arm_compute/graph/nodes/FlattenLayerNode.h"
#include "arm_compute/graph/nodes/FullyConnectedLayerNode.h"
#include "arm_compute/graph/nodes/FusedConvolutionBatchNormalizationNode.h"
-#include "arm_compute/graph/nodes/FusedConvolutionBatchNormalizationWithPostOpsNode.h"
-#include "arm_compute/graph/nodes/FusedConvolutionWithPostOpNode.h"
#include "arm_compute/graph/nodes/FusedDepthwiseConvolutionBatchNormalizationNode.h"
#include "arm_compute/graph/nodes/GenerateProposalsLayerNode.h"
#include "arm_compute/graph/nodes/InputNode.h"
@@ -70,4 +68,4 @@
#include "arm_compute/graph/nodes/StackLayerNode.h"
#include "arm_compute/graph/nodes/StridedSliceLayerNode.h"
-#endif /* ARM_COMPUTE_GRAPH_NODES_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_NODES_NODES_H
diff --git a/arm_compute/graph/nodes/NodesFwd.h b/arm_compute/graph/nodes/NodesFwd.h
index f1576d6..580f339 100644
--- a/arm_compute/graph/nodes/NodesFwd.h
+++ b/arm_compute/graph/nodes/NodesFwd.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_NODES_FWD_H
-#define ARM_COMPUTE_GRAPH_NODES_FWD_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_NODES_NODESFWD_H
+#define ACL_ARM_COMPUTE_GRAPH_NODES_NODESFWD_H
namespace arm_compute
{
@@ -49,9 +49,7 @@
class FlattenLayerNode;
class FullyConnectedLayerNode;
class FusedConvolutionBatchNormalizationNode;
-class FusedConvolutionWithPostOpNode;
class FusedDepthwiseConvolutionBatchNormalizationNode;
-class FusedConvolutionBatchNormalizationWithPostOpsNode;
class GenerateProposalsLayerNode;
class InputNode;
class L2NormalizeLayerNode;
@@ -77,4 +75,4 @@
class StridedSliceLayerNode;
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_NODES_FWD_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_NODES_NODESFWD_H
diff --git a/arm_compute/graph/printers/DotGraphPrinter.h b/arm_compute/graph/printers/DotGraphPrinter.h
index 63b8927..564aecf 100644
--- a/arm_compute/graph/printers/DotGraphPrinter.h
+++ b/arm_compute/graph/printers/DotGraphPrinter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019,2021 Arm Limited.
+ * Copyright (c) 2018-2019,2021,2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_GRAPH_DOTGRAPHPRINTER_H
-#define ARM_COMPUTE_GRAPH_DOTGRAPHPRINTER_H
+#ifndef ACL_ARM_COMPUTE_GRAPH_PRINTERS_DOTGRAPHPRINTER_H
+#define ACL_ARM_COMPUTE_GRAPH_PRINTERS_DOTGRAPHPRINTER_H
#include "arm_compute/graph/IGraphPrinter.h"
@@ -57,8 +57,6 @@
void visit(DepthwiseConvolutionLayerNode &n) override;
void visit(EltwiseLayerNode &n) override;
void visit(FusedConvolutionBatchNormalizationNode &n) override;
- void visit(FusedConvolutionBatchNormalizationWithPostOpsNode &n) override;
- void visit(FusedConvolutionWithPostOpNode &n) override;
void visit(FusedDepthwiseConvolutionBatchNormalizationNode &n) override;
void visit(NormalizationLayerNode &n) override;
void visit(PoolingLayerNode &n) override;
@@ -106,4 +104,4 @@
};
} // namespace graph
} // namespace arm_compute
-#endif /* ARM_COMPUTE_GRAPH_DOTGRAPHPRINTER_H */
+#endif // ACL_ARM_COMPUTE_GRAPH_PRINTERS_DOTGRAPHPRINTER_H
diff --git a/arm_compute/runtime/CL/functions/CLConvolutionLayer.h b/arm_compute/runtime/CL/functions/CLConvolutionLayer.h
index 8c9e45d..77bf48d 100644
--- a/arm_compute/runtime/CL/functions/CLConvolutionLayer.h
+++ b/arm_compute/runtime/CL/functions/CLConvolutionLayer.h
@@ -21,12 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_CLCONVOLUTIONLAYER_H
-#define ARM_COMPUTE_CLCONVOLUTIONLAYER_H
+#ifndef ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLCONVOLUTIONLAYER_H
+#define ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLCONVOLUTIONLAYER_H
#include "arm_compute/core/CL/CLCompileContext.h"
#include "arm_compute/core/Types.h"
-#include "arm_compute/core/experimental/IPostOp.h"
#include "arm_compute/function_info/ActivationLayerInfo.h"
#include "arm_compute/runtime/CL/CLTensor.h"
#include "arm_compute/runtime/IFunction.h"
@@ -120,11 +119,9 @@
* @param[in] enable_fast_math (Optional) Enable fast math computation. In case this flag were set, the function could dispatch the fastest implementation
* available which may introduce a drop of accuracy as well. Default is false
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*/
void configure(ICLTensor *input, const ICLTensor *weights, const ICLTensor *biases, ICLTensor *output, const PadStrideInfo &conv_info, const WeightsInfo &weights_info = WeightsInfo(),
- const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), bool enable_fast_math = false, unsigned int num_groups = 1,
- const experimental::PostOpList<ICLTensor *> &post_ops = experimental::PostOpList<ICLTensor *> {});
+ const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), bool enable_fast_math = false, unsigned int num_groups = 1);
/** Set the input and output tensors.
*
* @param[in] compile_context The compile context to be used.
@@ -144,11 +141,10 @@
* @param[in] enable_fast_math (Optional) Enable fast math computation. In case this flag were set, the function could dispatch the fastest implementation
* available which may introduce a drop of accuracy as well. Default is false
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*/
void configure(const CLCompileContext &compile_context, ICLTensor *input, const ICLTensor *weights, const ICLTensor *biases, ICLTensor *output, const PadStrideInfo &conv_info,
const WeightsInfo &weights_info = WeightsInfo(), const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), bool enable_fast_math = false,
- unsigned int num_groups = 1, const experimental::PostOpList<ICLTensor *> &post_ops = experimental::PostOpList<ICLTensor *> {});
+ unsigned int num_groups = 1);
/** Static function to check if given info will lead to a valid configuration of @ref CLConvolutionLayer
*
* @param[in] input Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
@@ -167,13 +163,12 @@
* @param[in] enable_fast_math (Optional) Enable fast math computation. In case this flag were set, the function could dispatch the fastest implementation
* available which may introduce a drop of accuracy as well. Default is false
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*
* @return a status
*/
static Status validate(const ITensorInfo *input, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *output, const PadStrideInfo &conv_info,
const WeightsInfo &weights_info = WeightsInfo(), const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), bool enable_fast_math = false,
- unsigned int num_groups = 1, const experimental::PostOpList<ITensorInfo *> &post_ops = experimental::PostOpList<ITensorInfo *> {});
+ unsigned int num_groups = 1);
/** Static function to check if given info will return the convolution called by @ref CLConvolutionLayer
*
* @param[in] input Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
@@ -203,5 +198,5 @@
struct Impl;
std::unique_ptr<Impl> _impl;
};
-}
-#endif /* ARM_COMPUTE_CLCONVOLUTIONLAYER_H */
+} // namespace arm_compute
+#endif // ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLCONVOLUTIONLAYER_H
diff --git a/arm_compute/runtime/CL/functions/CLGEMMConvolutionLayer.h b/arm_compute/runtime/CL/functions/CLGEMMConvolutionLayer.h
index 9827340..4bafef2 100644
--- a/arm_compute/runtime/CL/functions/CLGEMMConvolutionLayer.h
+++ b/arm_compute/runtime/CL/functions/CLGEMMConvolutionLayer.h
@@ -21,10 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_CLGEMMCONVOLUTIONLAYER_H
-#define ARM_COMPUTE_CLGEMMCONVOLUTIONLAYER_H
+#ifndef ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLGEMMCONVOLUTIONLAYER_H
+#define ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLGEMMCONVOLUTIONLAYER_H
-#include "arm_compute/core/experimental/IPostOp.h"
#include "arm_compute/function_info/ActivationLayerInfo.h"
#include "arm_compute/runtime/CL/CLTensor.h"
#include "arm_compute/runtime/CL/CLTypes.h"
@@ -95,11 +94,9 @@
* @param[in] dilation (Optional) Dilation, in elements, across x and y. Defaults to (1, 1).
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*/
void configure(const ICLTensor *input, const ICLTensor *weights, const ICLTensor *biases, ICLTensor *output, const PadStrideInfo &conv_info, const WeightsInfo &weights_info = WeightsInfo(),
- const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1,
- const experimental::PostOpList<ICLTensor *> &post_ops = experimental::PostOpList<ICLTensor *> {});
+ const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1);
/** Set the input and output tensors.
*
* @param[in] compile_context The compile context to be used.
@@ -118,12 +115,10 @@
* @param[in] dilation (Optional) Dilation, in elements, across x and y. Defaults to (1, 1).
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*/
void configure(const CLCompileContext &compile_context, const ICLTensor *input, const ICLTensor *weights, const ICLTensor *biases, ICLTensor *output, const PadStrideInfo &conv_info,
const WeightsInfo &weights_info = WeightsInfo(),
- const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1,
- const experimental::PostOpList<ICLTensor *> &post_ops = experimental::PostOpList<ICLTensor *> {});
+ const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1);
/** Static function to check if given info will lead to a valid configuration of @ref CLGEMMConvolutionLayer.
*
* @param[in] input Source tensor. 3 lower dimensions represent a single input [width, height, IFM],
@@ -141,13 +136,11 @@
* @param[in] dilation (Optional) Dilation, in elements, across x and y. Defaults to (1, 1).
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
* @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is only supported for NCHW data layout
- * @param[in] post_ops (Optional) A sequence of post operations that are performed after the main operation.
*
* @return a status
*/
static Status validate(const ITensorInfo *input, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *output, const PadStrideInfo &conv_info,
- const WeightsInfo &weights_info = WeightsInfo(), const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1,
- const experimental::PostOpList<ITensorInfo *> &post_ops = experimental::PostOpList<ITensorInfo *> {});
+ const WeightsInfo &weights_info = WeightsInfo(), const Size2D &dilation = Size2D(1U, 1U), const ActivationLayerInfo &act_info = ActivationLayerInfo(), unsigned int num_groups = 1);
// Inherited methods overridden:
void run() override;
@@ -158,4 +151,4 @@
std::unique_ptr<Impl> _impl;
};
} // namespace arm_compute
-#endif /* ARM_COMPUTE_CLGEMMCONVOLUTIONLAYER_H */
+#endif // ACL_ARM_COMPUTE_RUNTIME_CL_FUNCTIONS_CLGEMMCONVOLUTIONLAYER_H
diff --git a/arm_compute/runtime/FunctionDescriptors.h b/arm_compute/runtime/FunctionDescriptors.h
index 630f533..05f172b 100644
--- a/arm_compute/runtime/FunctionDescriptors.h
+++ b/arm_compute/runtime/FunctionDescriptors.h
@@ -21,8 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-#ifndef ARM_COMPUTE_RUNTIME_FUNCTION_DESCRIPTORS_H
-#define ARM_COMPUTE_RUNTIME_FUNCTION_DESCRIPTORS_H
+#ifndef ACL_ARM_COMPUTE_RUNTIME_FUNCTIONDESCRIPTORS_H
+#define ACL_ARM_COMPUTE_RUNTIME_FUNCTIONDESCRIPTORS_H
#include "arm_compute/core/Types.h"
#include "arm_compute/function_info/ActivationLayerInfo.h"
@@ -58,24 +58,22 @@
{
Conv2dInfo() = default;
- Conv2dInfo(const PadStrideInfo &conv_info,
- const Size2D &dilation,
- const ActivationLayerInfo &act_info,
- bool enable_fast_math,
- unsigned int num_groups,
- const experimental::PostOpList<ITensorInfo *> &post_ops = experimental::PostOpList<ITensorInfo *> {},
- const WeightsInfo &weights_info = WeightsInfo())
- : conv_info(conv_info), dilation(dilation), act_info(act_info), enable_fast_math(enable_fast_math), num_groups(num_groups), post_ops(post_ops), weights_info(weights_info)
+ Conv2dInfo(const PadStrideInfo &conv_info,
+ const Size2D &dilation,
+ const ActivationLayerInfo &act_info,
+ bool enable_fast_math,
+ unsigned int num_groups,
+ const WeightsInfo &weights_info = WeightsInfo())
+ : conv_info(conv_info), dilation(dilation), act_info(act_info), enable_fast_math(enable_fast_math), num_groups(num_groups), weights_info(weights_info)
{
}
- PadStrideInfo conv_info{};
- Size2D dilation{ 1U, 1U };
- ActivationLayerInfo act_info{};
- bool enable_fast_math{ false };
- unsigned int num_groups{ 1 };
- experimental::PostOpList<ITensorInfo *> post_ops{};
- WeightsInfo weights_info{};
+ PadStrideInfo conv_info{};
+ Size2D dilation{ 1U, 1U };
+ ActivationLayerInfo act_info{};
+ bool enable_fast_math{ false };
+ unsigned int num_groups{ 1 };
+ WeightsInfo weights_info{};
};
/** Descriptor used by the 3d Convolution function */
@@ -102,4 +100,4 @@
};
} // namespace arm_compute
-#endif /* ARM_COMPUTE_RUNTIME_FUNCTION_DESCRIPTORS_H */
+#endif // ACL_ARM_COMPUTE_RUNTIME_FUNCTIONDESCRIPTORS_H