commit 12f2b8c316155660f1e612fe7e8fab7861decc03
author Gian Marco Iodice <gianmarco.iodice@arm.com> Thu Feb 13 12:27:37 2020 +0000
committer Georgios Pinitas <georgios.pinitas@arm.com> Wed Feb 26 11:06:48 2020 +0000
tree 2bab7a855ce2f52b7e9a59fc60c5e032a7b95176
parent e620a83da59b9f835642d1dd0b68663556dbf379

COMPMID-3202: Add support for Valhall architecture in GEMM

Change-Id: I2cd0b5ee0ae2e3c65a04c7be70478b0452e55132
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/2730
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>

src/core/CL/gemm/reshaped_only_rhs/CLGEMMReshapedOnlyRHSKernelConfigurationBifrost.cpp

diff --git a/src/core/CL/gemm/reshaped_only_rhs/CLGEMMReshapedOnlyRHSKernelConfigurationBifrost.cpp b/src/core/CL/gemm/reshaped_only_rhs/CLGEMMReshapedOnlyRHSKernelConfigurationBifrost.cpp
index 5955bac..8e79811 100644
--- a/src/core/CL/gemm/reshaped_only_rhs/CLGEMMReshapedOnlyRHSKernelConfigurationBifrost.cpp
+++ b/src/core/CL/gemm/reshaped_only_rhs/CLGEMMReshapedOnlyRHSKernelConfigurationBifrost.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited.
+ * Copyright (c) 2019-2020 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -35,8 +35,8 @@
 {
 namespace cl_gemm
 {
-CLGEMMReshapedOnlyRHSKernelConfigurationBifrost::CLGEMMReshapedOnlyRHSKernelConfigurationBifrost(GPUTarget arch)
-    : ICLGEMMKernelConfiguration(arch)
+CLGEMMReshapedOnlyRHSKernelConfigurationBifrost::CLGEMMReshapedOnlyRHSKernelConfigurationBifrost(GPUTarget gpu)
+    : ICLGEMMKernelConfiguration(gpu)
 {
 }
 
@@ -72,7 +72,7 @@
     switch(_target)
     {
         case GPUTarget::G76:
-            if (gemm_configs_G76.find(data_type) != gemm_configs_G76.end())
+            if(gemm_configs_G76.find(data_type) != gemm_configs_G76.end())
             {
                 return (this->*gemm_configs_G76[data_type])(m, n, k, b);
             }
@@ -81,7 +81,7 @@
                 ARM_COMPUTE_ERROR("Not supported data type");
             }
         case GPUTarget::G51:
-            if (gemm_configs_G51.find(data_type) != gemm_configs_G51.end())
+            if(gemm_configs_G51.find(data_type) != gemm_configs_G51.end())
             {
                 return (this->*gemm_configs_G51[data_type])(m, n, k, b);
             }
@@ -90,7 +90,7 @@
                 ARM_COMPUTE_ERROR("Not supported data type");
             }
         default:
-            if (gemm_configs_G7x.find(data_type) != gemm_configs_G7x.end())
+            if(gemm_configs_G7x.find(data_type) != gemm_configs_G7x.end())
             {
                 return (this->*gemm_configs_G7x[data_type])(m, n, k, b);
             }
@@ -148,7 +148,7 @@
 
     if(m == 1)
     {
-        const unsigned int n0 = n < 1280? 2 : 4;
+        const unsigned int n0 = n < 1280 ? 2 : 4;
         const unsigned int h0 = std::max(n / n0, 1U);
         return configure_lhs_rhs_info(m, n, 1, n0, 4, 1, h0, false, true, false, true);
     }
@@ -205,7 +205,7 @@
 
     if(m == 1)
     {
-        const unsigned int n0 = n < 1280? 2 : 4;
+        const unsigned int n0 = n < 1280 ? 2 : 4;
         const unsigned int h0 = std::max(n / n0, 1U);
         return configure_lhs_rhs_info(m, n, 1, n0, 8, 1, h0, false, true, false, true);
     }
@@ -280,5 +280,6 @@
         return configure_lhs_rhs_info(m, n, 4, 2, 16, 1, h0, false, true, false, true);
     }
 }
+
 } // namespace cl_gemm
-} // namespace arm_compute
\ No newline at end of file
+} // namespace arm_compute