Port MaxUnpoolingLayer kernel and add KernelSelect vaidation test
Resolves COMPMID-4958
Change-Id: Ibed5155f2e3ece46635f6ea9617bf11cefc402b1
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7028
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
diff --git a/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.cpp b/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.cpp
new file mode 100644
index 0000000..604f22f
--- /dev/null
+++ b/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.cpp
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020-2022 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h"
+
+#include "arm_compute/core/TensorInfo.h"
+#include "arm_compute/core/Validate.h"
+#include "arm_compute/core/Window.h"
+#include "arm_compute/core/utils/misc/ShapeCalculator.h"
+#include "src/core/CPP/Validate.h"
+#include "src/core/common/Registrars.h"
+#include "src/core/helpers/AutoConfiguration.h"
+#include "src/core/helpers/WindowHelpers.h"
+#include "src/cpu/kernels/maxunpool/list.h"
+#include "support/ToolchainSupport.h"
+
+namespace arm_compute
+{
+namespace cpu
+{
+namespace kernels
+{
+using namespace misc::shape_calculator;
+
+namespace
+{
+static const std::vector<CpuMaxUnpoolingLayerKernel::MaxUnpoolingKernel> available_kernels =
+{
+ {
+ "neon_fp32_maxunpooling",
+ [](const DataTypeISASelectorData & data) { return data.dt == DataType::F32; },
+ REGISTER_FP32_NEON(neon_fp32_maxunpooling)
+ },
+ {
+ "neon_fp16_maxunpooling",
+ [](const DataTypeISASelectorData & data) { return data.dt == DataType::F16 && data.isa.fp16; },
+ REGISTER_FP16_NEON(neon_fp16_maxunpooling)
+ },
+ {
+ "neon_qu8_maxunpooling",
+ [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8; },
+ REGISTER_QASYMM8_NEON(neon_qs8_maxunpooling)
+ },
+ {
+ "neon_qs8_maxunpooling",
+ [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED; },
+ REGISTER_QASYMM8_SIGNED_NEON(neon_qu8_maxunpooling)
+ },
+};
+
+Status validate_arguments(const ITensorInfo *src, const ITensorInfo *indices, const ITensorInfo *dst, const PoolingLayerInfo &pool_info)
+{
+ ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, indices, dst);
+ ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src);
+ ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::F16, DataType::F32);
+ ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(indices, 1, DataType::U32);
+ ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_SHAPES(src, indices);
+
+ int pool_stride_x = 0;
+ int pool_stride_y = 0;
+ PoolingType pool_type = pool_info.pool_type;
+ const PadStrideInfo pad_stride_info = pool_info.pad_stride_info;
+ std::tie(pool_stride_x, pool_stride_y) = pad_stride_info.stride();
+ const int pool_size_x = pool_info.pool_size.width;
+ const int pool_size_y = pool_info.pool_size.height;
+ const Size2D pool_size(pool_size_x, pool_size_y);
+
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG(pool_type != PoolingType::MAX, "Pooling indices only supported for MAX pooling method");
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG((pool_size != Size2D(2, 2)), "Pooling indices only supported for pool size 2x2");
+ if(dst->total_size() != 0)
+ {
+ ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
+ ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, dst);
+ }
+
+ return Status{};
+}
+} // namespace
+
+void CpuMaxUnpoolingLayerKernel::configure(const ITensorInfo *src, const ITensorInfo *indices, ITensorInfo *dst, const PoolingLayerInfo &pool_info)
+{
+ ARM_COMPUTE_ERROR_ON_NULLPTR(src, dst, indices);
+ ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src, indices, dst, pool_info));
+ ARM_COMPUTE_UNUSED(indices);
+
+ const auto uk = CpuMaxUnpoolingLayerKernel::get_implementation(DataTypeISASelectorData{ src->data_type(), CPUInfo::get().get_isa() });
+ ARM_COMPUTE_ERROR_ON_NULLPTR(uk);
+ _run_method = uk->ukernel;
+
+ const TensorShape output_shape = compute_unpool_shape(*src, pool_info);
+ auto_init_if_empty(*dst, src->clone()->set_tensor_shape(output_shape));
+
+ auto window = calculate_max_window(*src, Steps());
+ ICpuKernel::configure(window);
+}
+
+Status CpuMaxUnpoolingLayerKernel::validate(const ITensorInfo *src, const ITensorInfo *indices, const ITensorInfo *dst, const PoolingLayerInfo &pool_info)
+{
+ ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, indices, dst);
+ ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src, indices, dst, pool_info));
+ return Status{};
+}
+
+void CpuMaxUnpoolingLayerKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
+{
+ ARM_COMPUTE_UNUSED(info);
+ ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
+ ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
+
+ const auto src = tensors.get_const_tensor(TensorType::ACL_SRC_0);
+ const auto indices = tensors.get_const_tensor(TensorType::ACL_SRC_1);
+ const auto dst = tensors.get_tensor(TensorType::ACL_DST);
+
+ _run_method(src, indices, dst, window);
+}
+
+const char *CpuMaxUnpoolingLayerKernel::name() const
+{
+ return "CpuMaxUnpoolingLayerKernel";
+}
+
+const std::vector<CpuMaxUnpoolingLayerKernel::MaxUnpoolingKernel> &CpuMaxUnpoolingLayerKernel::get_available_kernels()
+{
+ return available_kernels;
+}
+} // namespace kernels
+} // namespace cpu
+} // namespace arm_compute
\ No newline at end of file
diff --git a/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h b/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h
new file mode 100644
index 0000000..d0c1347
--- /dev/null
+++ b/src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020-2022 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_CPUMAXUNPOOLINGLAYERKERNEL_H
+#define ARM_COMPUTE_CPUMAXUNPOOLINGLAYERKERNEL_H
+
+#include "src/core/common/Macros.h"
+#include "src/cpu/ICpuKernel.h"
+
+namespace arm_compute
+{
+namespace cpu
+{
+namespace kernels
+{
+/** Interface for the pooling layer kernel */
+class CpuMaxUnpoolingLayerKernel : public ICpuKernel<CpuMaxUnpoolingLayerKernel>
+{
+private:
+ using MaxUnpoolingUKernelPtr = std::add_pointer<void(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)>::type;
+
+public:
+ /** Default constructor */
+ CpuMaxUnpoolingLayerKernel() = default;
+ ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuMaxUnpoolingLayerKernel);
+
+ /** Configure kernel for a given list of arguments
+ *
+ * @note Dst shape must be equal to the shape of the original src to pool.
+ *
+ * @param[in] src Source tensor to permute. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
+ * @param[in] indices Tensor containing the offset to store the src elements in the dst tensor.
+ * @ref CpuMaxUnpooling with indices should precede this function in order to
+ * properly reconstruct the output tensor.
+ * The tensor shape of this tensor has to be equal to the src tensor shape. Data type supported: U32.
+ * @param[out] dst Destination tensor. Data types supported: Same as @p src
+ * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo.
+ */
+ void configure(const ITensorInfo *src, const ITensorInfo *indices, ITensorInfo *dst, const PoolingLayerInfo &pool_info);
+ /** Static function to check if given info will lead to a valid configuration of @ref CpuMaxUnpoolingLayerKernel
+ *
+ * @param[in] src Source tensor to permute. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
+ * @param[in] indices Tensor info of the indices of the maximal values. Data type supported: U32.
+ * @param[out] dst Destination tensor. Data types supported: Same as @p src
+ * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo.
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *src, const ITensorInfo *indices, const ITensorInfo *dst, const PoolingLayerInfo &pool_info);
+
+ // Inherited methods overridden:
+ void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override;
+
+ struct MaxUnpoolingKernel
+ {
+ const char *name;
+ const DataTypeISASelectorPtr is_selected;
+ MaxUnpoolingUKernelPtr ukernel;
+ };
+
+ static const std::vector<MaxUnpoolingKernel> &get_available_kernels();
+
+ const char *name() const override;
+
+private:
+ MaxUnpoolingUKernelPtr _run_method{ nullptr };
+};
+
+} // namespace kernels
+} // namespace cpu
+} // namespace arm_compute
+#endif /*ARM_COMPUTE_CPUMAXUNPOOLINGLAYERKERNEL_H */
diff --git a/src/cpu/kernels/maxunpool/generic/neon/fp16.cpp b/src/cpu/kernels/maxunpool/generic/neon/fp16.cpp
index d43503a..e81ff92 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/fp16.cpp
+++ b/src/cpu/kernels/maxunpool/generic/neon/fp16.cpp
@@ -27,9 +27,9 @@
{
namespace cpu
{
-void neon_fp16_maxunpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+void neon_fp16_maxunpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
{
- return max_unpooling<float16_t>(input, output, indices, window);
+ return max_unpooling<float16_t>(input, indices, output, window);
}
} // namespace cpu
} // namespace arm_compute
diff --git a/src/cpu/kernels/maxunpool/generic/neon/fp32.cpp b/src/cpu/kernels/maxunpool/generic/neon/fp32.cpp
index 2f96e86..ba0d785 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/fp32.cpp
+++ b/src/cpu/kernels/maxunpool/generic/neon/fp32.cpp
@@ -26,9 +26,9 @@
{
namespace cpu
{
-void neon_fp32_maxunpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+void neon_fp32_maxunpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
{
- return max_unpooling<float>(input, output, indices, window);
+ return max_unpooling<float>(input, indices, output, window);
}
} // namespace cpu
} // namespace arm_compute
diff --git a/src/cpu/kernels/maxunpool/generic/neon/impl.cpp b/src/cpu/kernels/maxunpool/generic/neon/impl.cpp
index 8bbc8d1..77e3b85 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/impl.cpp
+++ b/src/cpu/kernels/maxunpool/generic/neon/impl.cpp
@@ -29,7 +29,7 @@
namespace cpu
{
template <typename T>
-void max_unpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+void max_unpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
{
Iterator input_itr(input, window);
Iterator indices_itr(indices, window);
@@ -43,12 +43,12 @@
},
input_itr, indices_itr);
}
-template void max_unpooling<float>(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window);
-template void max_unpooling<int8_t>(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window);
-template void max_unpooling<uint8_t>(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window);
+template void max_unpooling<float>(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window);
+template void max_unpooling<int8_t>(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window);
+template void max_unpooling<uint8_t>(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window);
#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS)
-template void max_unpooling<float16_t>(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window);
+template void max_unpooling<float16_t>(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window);
#endif //defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS)
} // namespace cpu
} // namespace arm_compute
diff --git a/src/cpu/kernels/maxunpool/generic/neon/impl.h b/src/cpu/kernels/maxunpool/generic/neon/impl.h
index 6a14c66..3fea9cf 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/impl.h
+++ b/src/cpu/kernels/maxunpool/generic/neon/impl.h
@@ -33,7 +33,7 @@
namespace cpu
{
template <typename T>
-void max_unpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window);
+void max_unpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window);
} // namespace cpu
} // namespace arm_compute
#endif //define SRC_CORE_SVE_KERNELS_MAXUNPOOLING_IMPL_H
diff --git a/src/cpu/kernels/maxunpool/generic/neon/qasymm8.cpp b/src/cpu/kernels/maxunpool/generic/neon/qasymm8.cpp
index b6d0f48..53e601b 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/qasymm8.cpp
+++ b/src/cpu/kernels/maxunpool/generic/neon/qasymm8.cpp
@@ -26,9 +26,9 @@
{
namespace cpu
{
-void neon_qs8_maxunpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+void neon_qs8_maxunpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
{
- return max_unpooling<int8_t>(input, output, indices, window);
+ return max_unpooling<int8_t>(input, indices, output, window);
}
} // namespace cpu
} // namespace arm_compute
diff --git a/src/cpu/kernels/maxunpool/generic/neon/qasymm8_signed.cpp b/src/cpu/kernels/maxunpool/generic/neon/qasymm8_signed.cpp
index 79f3013..a3c346f 100644
--- a/src/cpu/kernels/maxunpool/generic/neon/qasymm8_signed.cpp
+++ b/src/cpu/kernels/maxunpool/generic/neon/qasymm8_signed.cpp
@@ -26,9 +26,9 @@
{
namespace cpu
{
-void neon_qu8_maxunpooling(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+void neon_qu8_maxunpooling(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
{
- return max_unpooling<uint8_t>(input, output, indices, window);
+ return max_unpooling<uint8_t>(input, indices, output, window);
}
} // namespace cpu
} // namespace arm_compute
diff --git a/src/cpu/kernels/maxunpool/list.h b/src/cpu/kernels/maxunpool/list.h
index 0f9bb49..2c4fe94 100644
--- a/src/cpu/kernels/maxunpool/list.h
+++ b/src/cpu/kernels/maxunpool/list.h
@@ -28,7 +28,7 @@
namespace cpu
{
#define DECLARE_MAXUNPOOL_KERNEL(func_name) \
- void func_name(const ITensor *input, ITensor *output, const ITensor *indices, const Window &window)
+ void func_name(const ITensor *input, const ITensor *indices, ITensor *output, const Window &window)
DECLARE_MAXUNPOOL_KERNEL(neon_fp32_maxunpooling);
DECLARE_MAXUNPOOL_KERNEL(neon_fp16_maxunpooling);
DECLARE_MAXUNPOOL_KERNEL(neon_qs8_maxunpooling);
diff --git a/src/cpu/operators/CpuMaxUnpooling.cpp b/src/cpu/operators/CpuMaxUnpooling.cpp
new file mode 100644
index 0000000..24e9fd6
--- /dev/null
+++ b/src/cpu/operators/CpuMaxUnpooling.cpp
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018-2022 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "src/cpu/operators/CpuMaxUnpooling.h"
+#include "src/common/utils/Log.h"
+#include "src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h"
+
+namespace arm_compute
+{
+namespace cpu
+{
+void CpuMaxUnpooling::configure(const ITensorInfo *src, const ITensorInfo *indices, ITensorInfo *dst, const PoolingLayerInfo &pool_info)
+{
+ ARM_COMPUTE_LOG_PARAMS(src, indices, dst, pool_info);
+ auto k = std::make_unique<kernels::CpuMaxUnpoolingLayerKernel>();
+ k->configure(src, indices, dst, pool_info);
+ _kernel = std::move(k);
+}
+
+Status CpuMaxUnpooling::validate(const ITensorInfo *src, const ITensorInfo *indices, const ITensorInfo *dst, const PoolingLayerInfo &pool_info)
+{
+ return kernels::CpuMaxUnpoolingLayerKernel::validate(src, indices, dst, pool_info);
+}
+} // namesapce cpu
+} // namespace arm_compute
diff --git a/src/cpu/operators/CpuMaxUnpooling.h b/src/cpu/operators/CpuMaxUnpooling.h
new file mode 100644
index 0000000..aa1f107
--- /dev/null
+++ b/src/cpu/operators/CpuMaxUnpooling.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_CPU_MAXUNPOOLING_H
+#define ARM_COMPUTE_CPU_MAXUNPOOLING_H
+
+#include "src/cpu/ICpuOperator.h"
+
+namespace arm_compute
+{
+namespace cpu
+{
+/** Basic function to run @ref kernels::CpuMaxUnpoolingLayerKernel */
+class CpuMaxUnpooling : public ICpuOperator
+{
+public:
+ /** Configure operator for a given list of arguments
+ *
+ * @param[in] src Source tensor to permute. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
+ * @param[in] indices Tensor containing the offset to store the src elements in the dst tensor.
+ * @ref CpuMaxUnpooling with indices should precede this function in order to
+ * properly reconstruct the output tensor.
+ * The tensor shape of this tensor has to be equal to the src tensor shape. Data type supported: U32.
+ * @param[out] dst Destination tensor. Data types supported: Same as @p src
+ * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo.
+ */
+ void configure(const ITensorInfo *src, const ITensorInfo *indices, ITensorInfo *dst, const PoolingLayerInfo &pool_info);
+ /** Static function to check if given info will lead to a valid configuration
+ *
+ * Similar to @ref CpuMaxUnpooling::configure()
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *src, const ITensorInfo *indices, const ITensorInfo *dst, const PoolingLayerInfo &pool_info);
+};
+} // namespace cpu
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_CPU_MAXUNPOOLING_H */