Add CPU Pool3d FP16/32 implementation
- Add implementation for the CPU pooling 3d layer.
- NDHWC data layout support
- Support FP32/FP16.
- Add Pool3d to the operator list.
- Fix CL Pool3d kernel comments to generate the operator list.
Resolves: COMPMID-4671
Signed-off-by: Adnan AlSinan <adnan.alsinan@arm.com>
Change-Id: I92478a154beb12541525b648ed3dd5a58c8f27fa
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7311
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
(cherry picked from commit 572659a0e5dd1086b1c7d16fe331ff73d2acd93a)
diff --git a/docs/user_guide/operator_list.dox b/docs/user_guide/operator_list.dox
index 1dfbdf6..ee337d4 100644
--- a/docs/user_guide/operator_list.dox
+++ b/docs/user_guide/operator_list.dox
@@ -1,5 +1,5 @@
///
-/// Copyright (c) 2021 Arm Limited.
+/// Copyright (c) 2021-2022 Arm Limited.
///
/// SPDX-License-Identifier: MIT
///
@@ -2300,6 +2300,36 @@
<tr><td>F32<td>F32
</table>
<tr>
+ <td rowspan="2">Pooling3dLayer
+ <td rowspan="2" style="width:200px;"> Function to perform pooling 3D with the specified pooling operation.
+ <td rowspan="2">
+ <ul>
+ <li>N/A
+ </ul>
+ <td>NEPooling3dLayer
+ <td>
+ <ul>
+ <li>NDHWC
+ </ul>
+ <td>
+ <table>
+ <tr><th>src<th>dst
+ <tr><td>F16<td>F16
+ <tr><td>F32<td>F32
+ </table>
+<tr>
+ <td>CLPooling3dLayer
+ <td>
+ <ul>
+ <li>NDHWC
+ </ul>
+ <td>
+ <table>
+ <tr><th>src<th>dst
+ <tr><td>F16<td>F16
+ <tr><td>F32<td>F32
+ </table>
+<tr>
<td rowspan="2">PReluLayer
<td rowspan="2" style="width:200px;"> Function to compute the activation layer with the PRELU activation function.
<td rowspan="2">