| commit | 17812ba9f7cf2c8f5121c11760ac45fbbdb7aeaf | [log] [tgz] |
|---|---|---|
| author | Georgios Pinitas <georgios.pinitas@arm.com> | Mon Jun 04 19:27:13 2018 +0100 |
| committer | Anthony Barbier <anthony.barbier@arm.com> | Fri Nov 02 16:52:54 2018 +0000 |
| tree | 28c7bb65a8306e82de91a644fdcc1c0947c6f6d7 | |
| parent | f8d8f3aff04faf731f20411ecb91027eab4365c5 [diff] [blame] |
COMPMID-817: Tuner: Port kernels to new design. Change-Id: Iaabb1153c2abe0400ec79d51a21347debe92d642 Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/134062 Tested-by: Jenkins <bsgcomp@arm.com> Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
diff --git a/arm_compute/core/CL/kernels/CLPoolingLayerKernel.h b/arm_compute/core/CL/kernels/CLPoolingLayerKernel.h index e9ce28b..c135077 100644 --- a/arm_compute/core/CL/kernels/CLPoolingLayerKernel.h +++ b/arm_compute/core/CL/kernels/CLPoolingLayerKernel.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited. + * Copyright (c) 2017-2018 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -72,7 +72,7 @@ void run(const Window &window, cl::CommandQueue &queue) override; BorderSize border_size() const override; -private: +public: const ICLTensor *_input; ICLTensor *_output; PoolingLayerInfo _pool_info;