commit 4a95bba6ca61ce99995ece6fd237b5498c9f322c
author Giorgio Arena <giorgio.arena@arm.com> Mon Jun 28 11:00:27 2021 +0100
committer Giorgio Arena <giorgio.arena@arm.com> Tue Jun 29 11:06:10 2021 +0000
tree 04ef2dee1cdc015ce14ce6b664d9a956a96c3a05
parent 731fe667e3009bfbfee8b0eb74ecb68b291e4311

Set up the framework to choose the default LWS

Resolve COMPMID-4486

Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Change-Id: Ib38b7943bd776a6d75d1da163908724c49eae73d
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5864
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>

src/core/CL/kernels/CLFFTRadixStageKernel.cpp

diff --git a/src/core/CL/kernels/CLFFTRadixStageKernel.cpp b/src/core/CL/kernels/CLFFTRadixStageKernel.cpp
index 779bf43..0ee247f 100644
--- a/src/core/CL/kernels/CLFFTRadixStageKernel.cpp
+++ b/src/core/CL/kernels/CLFFTRadixStageKernel.cpp
@@ -78,6 +78,7 @@
 CLFFTRadixStageKernel::CLFFTRadixStageKernel()
     : _input(nullptr), _output(nullptr), _run_in_place(false)
 {
+    _type = CLKernelType::ELEMENTWISE;
 }
 
 void CLFFTRadixStageKernel::configure(ICLTensor *input, ICLTensor *output, const FFTRadixStageKernelInfo &config)