COMPMID-1451: Fix CL/NEPermuteKernel PermuteVection check
COMPMID-1690: Add tests for NEPermute with PermutationVector dimension > 3
Change-Id: I4bfc6ff88cd46863c2e39975b5663c624db1a63d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155316
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
diff --git a/tests/validation/NEON/Permute.cpp b/tests/validation/NEON/Permute.cpp
index 872a16b..8c172dd 100644
--- a/tests/validation/NEON/Permute.cpp
+++ b/tests/validation/NEON/Permute.cpp
@@ -60,6 +60,8 @@
TensorInfo(TensorShape(1U, 7U), 1, DataType::U8), // invalid input size
TensorInfo(TensorShape(7U, 7U, 5U, 3U), 1, DataType::U16), // valid
TensorInfo(TensorShape(27U, 13U, 37U, 2U), 1, DataType::F32), // valid
+ TensorInfo(TensorShape(7U, 7U, 5U, 3U), 1, DataType::U16), // permutation not supported
+ TensorInfo(TensorShape(27U, 13U, 37U, 2U), 1, DataType::F32), // permutation not supported
}),
framework::dataset::make("OutputInfo", {
TensorInfo(TensorShape(5U, 7U, 7U, 3U), 1, DataType::U16),
@@ -68,6 +70,8 @@
TensorInfo(TensorShape(5U, 7U), 1, DataType::U8),
TensorInfo(TensorShape(5U, 7U, 7U, 3U), 1, DataType::U16),
TensorInfo(TensorShape(13U, 37U, 27U, 2U), 1, DataType::F32),
+ TensorInfo(TensorShape(5U, 7U, 7U, 3U), 1, DataType::U16),
+ TensorInfo(TensorShape(13U, 37U, 27U, 2U), 1, DataType::F32),
})),
framework::dataset::make("PermutationVector", {
PermutationVector(2U, 1U, 0U),
@@ -76,8 +80,10 @@
PermutationVector(2U, 0U, 1U),
PermutationVector(2U, 0U, 1U),
PermutationVector(1U, 2U, 0U),
+ PermutationVector(3U, 2U, 0U, 1U),
+ PermutationVector(2U, 3U, 1U, 0U)
})),
- framework::dataset::make("Expected", { false, false, false, false, true, true })),
+ framework::dataset::make("Expected", { false, false, false, false, true, true, false, false })),
input_info, output_info, perm_vect, expected)
{
ARM_COMPUTE_EXPECT(bool(NEPermute::validate(&input_info.clone()->set_is_resizable(false), &output_info.clone()->set_is_resizable(false), perm_vect)) == expected, framework::LogLevel::ERRORS);