commit 9aa153ae5d60fd08ec165280621f1e4fa7602048
author Pablo Marquez Tello <pablo.tello@arm.com> Tue Oct 10 12:18:48 2023 +0100
committer Pablo Marquez Tello <pablo.tello@arm.com> Tue Oct 10 13:11:38 2023 +0000
tree f5729dbbdaef555915a12a9fc28cf41ba9793a99
parent dfd56a630f7981100078b62adc37d65e48bc6d08

Fix build error

* Build error when using data_layout_support=nhwc

* Some kernels need to be guarded by ENABLE_NCHW_KERNELS

Change-Id: I9fb6cf0e204531f81b0dff3572a1740ba94cde0e
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10460
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>

src/cpu/kernels/pool2d/neon/fp16.cpp

diff --git a/src/cpu/kernels/pool2d/neon/fp16.cpp b/src/cpu/kernels/pool2d/neon/fp16.cpp
index 95ff7b7..9d24d79 100644
--- a/src/cpu/kernels/pool2d/neon/fp16.cpp
+++ b/src/cpu/kernels/pool2d/neon/fp16.cpp
@@ -37,6 +37,8 @@
 {
 namespace cpu
 {
+#ifdef ENABLE_NCHW_KERNELS
+
 namespace
 {
 float16x4_t
@@ -148,6 +150,7 @@
         },
         in, out);
 }
+#endif // ENABLE_NCHW_KERNELS
 
 void pooling2_f16_maxpool_indices(const ITensor    *src,
                                   ITensor          *dst0,
@@ -278,6 +281,7 @@
         },
         in, out, indices);
 }
+#ifdef ENABLE_NCHW_KERNELS
 
 void pooling2_fp16_neon_nchw(const ITensor    *src,
                              ITensor          *dst0,
@@ -461,6 +465,7 @@
         },
         in, out);
 }
+#endif // ENABLE_NCHW_KERNELS
 
 void poolingMxN_fp16_neon_nhwc(const ITensor    *src,
                                ITensor          *dst0,