Apply clang-format on repository
Code is formatted as per a revised clang format configuration
file(not part of this delivery). Version 14.0.6 is used.
Exclusion List:
- files with .cl extension
- files that are not strictly C/C++ (e.g. Android.bp, Sconscript ...)
And the following directories
- compute_kernel_writer/validation/
- tests/
- include/
- src/core/NEON/kernels/convolution/
- src/core/NEON/kernels/arm_gemm/
- src/core/NEON/kernels/arm_conv/
- data/
There will be a follow up for formatting of .cl files and the
files under tests/ and compute_kernel_writer/validation/.
Signed-off-by: Felix Thomasmathibalan <felixjohnny.thomasmathibalan@arm.com>
Change-Id: Ib7eb1fcf4e7537b9feaefcfc15098a804a3fde0a
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10391
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
diff --git a/src/common/cpuinfo/CpuInfo.cpp b/src/common/cpuinfo/CpuInfo.cpp
index cdcdea9..23a4773 100644
--- a/src/common/cpuinfo/CpuInfo.cpp
+++ b/src/common/cpuinfo/CpuInfo.cpp
@@ -25,6 +25,7 @@
#include "arm_compute/core/Error.h"
#include "arm_compute/core/Log.h"
+
#include "support/StringSupport.h"
#include "support/ToolchainSupport.h"
@@ -53,16 +54,16 @@
#endif /* defined(__APPLE__) && defined(__aarch64__)) */
#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID (1 << 11)
-#define ARM_COMPUTE_GET_FEATURE_REG(var, freg) __asm __volatile("MRS %0, " #freg \
- : "=r"(var))
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID (1 << 11)
+#define ARM_COMPUTE_GET_FEATURE_REG(var, freg) __asm __volatile("MRS %0, " #freg : "=r"(var))
namespace arm_compute
{
namespace cpuinfo
{
namespace
{
-#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__))
+#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && \
+ (defined(__arm__) || defined(__aarch64__))
/** Extract MIDR using CPUID information that are exposed to user-space
*
* @param[in] max_num_cpus Maximum number of possible CPUs
@@ -72,15 +73,15 @@
std::vector<uint32_t> midr_from_cpuid(uint32_t max_num_cpus)
{
std::vector<uint32_t> cpus;
- for(unsigned int i = 0; i < max_num_cpus; ++i)
+ for (unsigned int i = 0; i < max_num_cpus; ++i)
{
std::stringstream str;
str << "/sys/devices/system/cpu/cpu" << i << "/regs/identification/midr_el1";
std::ifstream file(str.str(), std::ios::in);
- if(file.is_open())
+ if (file.is_open())
{
std::string line;
- if(bool(getline(file, line)))
+ if (bool(getline(file, line)))
{
cpus.emplace_back(support::cpp11::stoul(line, nullptr, support::cpp11::NumericBase::BASE_16));
}
@@ -122,34 +123,35 @@
ARM_COMPUTE_ERROR_ON_MSG(ret_status != 0, "Regex compilation failed.");
std::ifstream file("/proc/cpuinfo", std::ios::in);
- if(file.is_open())
+ if (file.is_open())
{
std::string line;
int midr = 0;
int curcpu = -1;
- while(bool(getline(file, line)))
+ while (bool(getline(file, line)))
{
std::array<regmatch_t, 2> match;
ret_status = regexec(&proc_regex, line.c_str(), 2, match.data(), 0);
- if(ret_status == 0)
+ if (ret_status == 0)
{
std::string id = line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so));
int newcpu = support::cpp11::stoi(id, nullptr);
- if(curcpu >= 0 && midr == 0)
+ if (curcpu >= 0 && midr == 0)
{
// Matched a new CPU ID without any description of the previous one - looks like old format.
return {};
}
- if(curcpu >= 0 && curcpu < max_num_cpus)
+ if (curcpu >= 0 && curcpu < max_num_cpus)
{
cpus.emplace_back(midr);
}
else
{
- ARM_COMPUTE_LOG_INFO_MSG_CORE("Trying to populate a core id with id greater than the expected number of cores!");
+ ARM_COMPUTE_LOG_INFO_MSG_CORE(
+ "Trying to populate a core id with id greater than the expected number of cores!");
}
midr = 0;
@@ -159,7 +161,7 @@
}
ret_status = regexec(&imp_regex, line.c_str(), 2, match.data(), 0);
- if(ret_status == 0)
+ if (ret_status == 0)
{
std::string subexp = line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so));
int impv = support::cpp11::stoi(subexp, nullptr, support::cpp11::NumericBase::BASE_16);
@@ -169,7 +171,7 @@
}
ret_status = regexec(&var_regex, line.c_str(), 2, match.data(), 0);
- if(ret_status == 0)
+ if (ret_status == 0)
{
std::string subexp = line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so));
int varv = support::cpp11::stoi(subexp, nullptr, support::cpp11::NumericBase::BASE_16);
@@ -179,7 +181,7 @@
}
ret_status = regexec(&part_regex, line.c_str(), 2, match.data(), 0);
- if(ret_status == 0)
+ if (ret_status == 0)
{
std::string subexp = line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so));
int partv = support::cpp11::stoi(subexp, nullptr, support::cpp11::NumericBase::BASE_16);
@@ -189,7 +191,7 @@
}
ret_status = regexec(&rev_regex, line.c_str(), 2, match.data(), 0);
- if(ret_status == 0)
+ if (ret_status == 0)
{
std::string subexp = line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so));
int regv = support::cpp11::stoi(subexp, nullptr);
@@ -200,13 +202,14 @@
}
}
- if(curcpu >= 0 && curcpu < max_num_cpus)
+ if (curcpu >= 0 && curcpu < max_num_cpus)
{
cpus.emplace_back(midr);
}
else
{
- ARM_COMPUTE_LOG_INFO_MSG_CORE("Trying to populate a core id with id greater than the expected number of cores!");
+ ARM_COMPUTE_LOG_INFO_MSG_CORE(
+ "Trying to populate a core id with id greater than the expected number of cores!");
}
}
@@ -231,11 +234,11 @@
CPUspresent.open("/sys/devices/system/cpu/present", std::ios::in);
bool success = false;
- if(CPUspresent.is_open())
+ if (CPUspresent.is_open())
{
std::string line;
- if(bool(getline(CPUspresent, line)))
+ if (bool(getline(CPUspresent, line)))
{
/* The content of this file is a list of ranges or single values, e.g.
* 0-5, or 1-3,5,7 or similar. As we are interested in the
@@ -244,9 +247,9 @@
*/
auto startfrom = line.begin();
- for(auto i = line.begin(); i < line.end(); ++i)
+ for (auto i = line.begin(); i < line.end(); ++i)
{
- if(*i == '-' || *i == ',')
+ if (*i == '-' || *i == ',')
{
startfrom = i + 1;
}
@@ -260,13 +263,14 @@
}
// Return std::thread::hardware_concurrency() as a fallback.
- if(!success)
+ if (!success)
{
max_cpus = std::thread::hardware_concurrency();
}
return max_cpus;
}
-#elif defined(__aarch64__) && defined(__APPLE__) /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
+#elif defined(__aarch64__) && \
+ defined(__APPLE__) /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
/** Query features through sysctlbyname
*
* @return int value queried
@@ -278,46 +282,45 @@
sysctlbyname(cap.c_str(), &result, &size, NULL, 0);
return result;
}
-#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
+#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
#if defined(BARE_METAL) && defined(__aarch64__)
uint64_t get_sve_feature_reg()
{
uint64_t svefr0 = 0;
- __asm __volatile(
- ".inst 0xd5380483 // mrs x3, ID_AA64ZFR0_EL1\n"
- "MOV %0, X3"
- : "=r"(svefr0)
- :
- : "x3");
+ __asm __volatile(".inst 0xd5380483 // mrs x3, ID_AA64ZFR0_EL1\n"
+ "MOV %0, X3"
+ : "=r"(svefr0)
+ :
+ : "x3");
return svefr0;
}
#endif /* defined(BARE_METAL) && defined(__aarch64__) */
} // namespace
-CpuInfo::CpuInfo(CpuIsaInfo isa, std::vector<CpuModel> cpus)
- : _isa(std::move(isa)), _cpus(std::move(cpus))
+CpuInfo::CpuInfo(CpuIsaInfo isa, std::vector<CpuModel> cpus) : _isa(std::move(isa)), _cpus(std::move(cpus))
{
}
CpuInfo CpuInfo::build()
{
-#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__))
+#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && \
+ (defined(__arm__) || defined(__aarch64__))
const uint32_t hwcaps = getauxval(AT_HWCAP);
const uint32_t hwcaps2 = getauxval(AT_HWCAP2);
const uint32_t max_cpus = get_max_cpus();
// Populate midr values
std::vector<uint32_t> cpus_midr;
- if(hwcaps & ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID)
+ if (hwcaps & ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID)
{
cpus_midr = midr_from_cpuid(max_cpus);
}
- if(cpus_midr.empty())
+ if (cpus_midr.empty())
{
cpus_midr = midr_from_proc_cpuinfo(max_cpus);
}
- if(cpus_midr.empty())
+ if (cpus_midr.empty())
{
cpus_midr.resize(max_cpus, 0);
}
@@ -333,7 +336,9 @@
CpuInfo info(isa, cpus_model);
return info;
-#elif(BARE_METAL) && defined(__aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
+#elif (BARE_METAL) && \
+ defined( \
+ __aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
// Assume single CPU in bare metal mode. Just read the ID register and feature bits directly.
uint64_t isar0 = 0, isar1 = 0, pfr0 = 0, pfr1 = 0, svefr0 = 0, midr = 0;
@@ -342,7 +347,7 @@
ARM_COMPUTE_GET_FEATURE_REG(pfr0, ID_AA64PFR0_EL1);
ARM_COMPUTE_GET_FEATURE_REG(pfr1, ID_AA64PFR1_EL1);
ARM_COMPUTE_GET_FEATURE_REG(midr, MIDR_EL1);
- if((pfr0 >> 32) & 0xf)
+ if ((pfr0 >> 32) & 0xf)
{
svefr0 = get_sve_feature_reg();
}
@@ -361,14 +366,14 @@
CpuInfo info(isainfo, cpus_model);
return info;
#else /* #elif defined(__aarch64__) && defined(__APPLE__) */
- CpuInfo info(CpuIsaInfo(), { CpuModel::GENERIC });
+ CpuInfo info(CpuIsaInfo(), {CpuModel::GENERIC});
return info;
-#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
+#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
}
CpuModel CpuInfo::cpu_model(uint32_t cpuid) const
{
- if(cpuid < _cpus.size())
+ if (cpuid < _cpus.size())
{
return _cpus[cpuid];
}
@@ -377,9 +382,10 @@
CpuModel CpuInfo::cpu_model() const
{
-#if defined(_WIN64) || defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__))
+#if defined(_WIN64) || defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || \
+ (!defined(__arm__) && !defined(__aarch64__))
return cpu_model(0);
-#else /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */
+#else /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */
return cpu_model(sched_getcpu());
#endif /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */
}
@@ -406,13 +412,13 @@
// Read cpuinfo and get occurrence of each core
std::ifstream cpuinfo_file("/proc/cpuinfo", std::ios::in);
- if(cpuinfo_file.is_open())
+ if (cpuinfo_file.is_open())
{
std::string line;
- while(bool(getline(cpuinfo_file, line)))
+ while (bool(getline(cpuinfo_file, line)))
{
std::array<regmatch_t, 2> match;
- if(regexec(&cpu_part_rgx, line.c_str(), 2, match.data(), 0) == 0)
+ if (regexec(&cpu_part_rgx, line.c_str(), 2, match.data(), 0) == 0)
{
cpus.emplace_back(line.substr(match[1].rm_so, (match[1].rm_eo - match[1].rm_so)));
}
@@ -425,13 +431,13 @@
auto least_frequent_cpu_occurences = [](const std::vector<std::string> &cpus) -> uint32_t
{
std::unordered_map<std::string, uint32_t> cpus_freq;
- for(const auto &cpu : cpus)
+ for (const auto &cpu : cpus)
{
cpus_freq[cpu]++;
}
uint32_t vmin = cpus.size() + 1;
- for(const auto &cpu_freq : cpus_freq)
+ for (const auto &cpu_freq : cpus_freq)
{
vmin = std::min(vmin, cpu_freq.second);
}
diff --git a/src/common/cpuinfo/CpuIsaInfo.cpp b/src/common/cpuinfo/CpuIsaInfo.cpp
index 23da54a..5977685 100644
--- a/src/common/cpuinfo/CpuIsaInfo.cpp
+++ b/src/common/cpuinfo/CpuIsaInfo.cpp
@@ -24,6 +24,7 @@
#include "src/common/cpuinfo/CpuIsaInfo.h"
#include "arm_compute/core/Error.h"
+
#include "src/common/cpuinfo/CpuModel.h"
/* Arm Feature flags */
@@ -31,18 +32,18 @@
#define ARM_COMPUTE_CPU_FEATURE_HWCAP_NEON (1 << 12)
/* Arm64 Feature flags */
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD (1 << 1)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP (1 << 9)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP (1 << 10)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP (1 << 20)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE (1 << 22)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2 (1 << 1)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM (1 << 9)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD (1 << 1)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP (1 << 9)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP (1 << 10)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP (1 << 20)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE (1 << 22)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2 (1 << 1)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM (1 << 9)
#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM (1 << 10)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16 (1 << 12)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM (1 << 13)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16 (1 << 14)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME (1 << 23)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16 (1 << 12)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM (1 << 13)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16 (1 << 14)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME (1 << 23)
namespace arm_compute
{
@@ -71,12 +72,12 @@
isa.sve2 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2);
// Detection of SME from type HWCAP2 in the auxillary vector
- isa.sme = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME);
- isa.sme2 = isa.sme; // Needs to be set properly
+ isa.sme = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME);
+ isa.sme2 = isa.sme; // Needs to be set properly
// Data-type support
- isa.fp16 = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP | ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP);
- isa.bf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16);
+ isa.fp16 = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP | ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP);
+ isa.bf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16);
isa.svebf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16);
// Instruction extensions
@@ -92,12 +93,15 @@
}
#endif /* defined(__aarch64__) */
-void decode_regs(CpuIsaInfo &isa, const uint64_t isar0, const uint64_t isar1, const uint64_t pfr0, const uint64_t pfr1, const uint64_t svefr0)
+void decode_regs(CpuIsaInfo &isa,
+ const uint64_t isar0,
+ const uint64_t isar1,
+ const uint64_t pfr0,
+ const uint64_t pfr1,
+ const uint64_t svefr0)
{
auto is_supported = [](uint64_t feature_reg, uint8_t feature_pos) -> bool
- {
- return ((feature_reg >> feature_pos) & 0xf);
- };
+ { return ((feature_reg >> feature_pos) & 0xf); };
// High-level SIMD support
isa.sve = is_supported(pfr0, 32);
@@ -124,11 +128,11 @@
*/
void allowlisted_model_features(CpuIsaInfo &isa, CpuModel model)
{
- if(isa.dot == false)
+ if (isa.dot == false)
{
isa.dot = model_supports_dot(model);
}
- if(isa.fp16 == false)
+ if (isa.fp16 == false)
{
isa.fp16 = model_supports_fp16(model);
}
@@ -147,7 +151,8 @@
return isa;
}
-CpuIsaInfo init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr)
+CpuIsaInfo
+init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr)
{
CpuIsaInfo isa;
diff --git a/src/common/cpuinfo/CpuIsaInfo.h b/src/common/cpuinfo/CpuIsaInfo.h
index b92b653..9d6bc07 100644
--- a/src/common/cpuinfo/CpuIsaInfo.h
+++ b/src/common/cpuinfo/CpuIsaInfo.h
@@ -37,22 +37,22 @@
struct CpuIsaInfo
{
/* SIMD extension support */
- bool neon{ false };
- bool sve{ false };
- bool sve2{ false };
- bool sme{ false };
- bool sme2{ false };
+ bool neon{false};
+ bool sve{false};
+ bool sve2{false};
+ bool sme{false};
+ bool sme2{false};
/* Data-type extensions support */
- bool fp16{ false };
- bool bf16{ false };
- bool svebf16{ false };
+ bool fp16{false};
+ bool bf16{false};
+ bool svebf16{false};
/* Instruction support */
- bool dot{ false };
- bool i8mm{ false };
- bool svei8mm{ false };
- bool svef32mm{ false };
+ bool dot{false};
+ bool i8mm{false};
+ bool svei8mm{false};
+ bool svef32mm{false};
};
/** Identify ISA related information through system information
@@ -76,7 +76,8 @@
*
* @return CpuIsaInfo A populated ISA feature structure
*/
-CpuIsaInfo init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr);
+CpuIsaInfo
+init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr);
} // namespace cpuinfo
} // namespace arm_compute
diff --git a/src/common/cpuinfo/CpuModel.cpp b/src/common/cpuinfo/CpuModel.cpp
index d6d91df..0455670 100644
--- a/src/common/cpuinfo/CpuModel.cpp
+++ b/src/common/cpuinfo/CpuModel.cpp
@@ -29,12 +29,12 @@
{
std::string cpu_model_to_string(CpuModel model)
{
- switch(model)
+ switch (model)
{
#define X(MODEL) \
-case CpuModel::MODEL: \
- return #MODEL;
- ARM_COMPUTE_CPU_MODEL_LIST
+ case CpuModel::MODEL: \
+ return #MODEL;
+ ARM_COMPUTE_CPU_MODEL_LIST
#undef X
default:
{
@@ -45,7 +45,7 @@
bool model_supports_fp16(CpuModel model)
{
- switch(model)
+ switch (model)
{
case CpuModel::GENERIC_FP16:
case CpuModel::GENERIC_FP16_DOT:
@@ -63,7 +63,7 @@
bool model_supports_dot(CpuModel model)
{
- switch(model)
+ switch (model)
{
case CpuModel::GENERIC_FP16_DOT:
case CpuModel::A55r1:
@@ -87,16 +87,16 @@
const int cpunum = (midr >> 4) & 0xFFF;
// Only CPUs we have code paths for are detected. All other CPUs can be safely classed as "GENERIC"
- if(implementer == 0x41) // Arm CPUs
+ if (implementer == 0x41) // Arm CPUs
{
- switch(cpunum)
+ switch (cpunum)
{
case 0xd03: // A53
case 0xd04: // A35
model = CpuModel::A53;
break;
case 0xd05: // A55
- if(variant != 0)
+ if (variant != 0)
{
model = CpuModel::A55r1;
}
@@ -109,7 +109,7 @@
model = CpuModel::A73;
break;
case 0xd0a: // A75
- if(variant != 0)
+ if (variant != 0)
{
model = CpuModel::GENERIC_FP16_DOT;
}
@@ -144,9 +144,9 @@
break;
}
}
- else if(implementer == 0x46)
+ else if (implementer == 0x46)
{
- switch(cpunum)
+ switch (cpunum)
{
case 0x001: // A64FX
model = CpuModel::A64FX;
@@ -156,9 +156,9 @@
break;
}
}
- else if(implementer == 0x48)
+ else if (implementer == 0x48)
{
- switch(cpunum)
+ switch (cpunum)
{
case 0xd40: // A76
model = CpuModel::GENERIC_FP16_DOT;
@@ -168,9 +168,9 @@
break;
}
}
- else if(implementer == 0x51)
+ else if (implementer == 0x51)
{
- switch(cpunum)
+ switch (cpunum)
{
case 0x800: // A73
model = CpuModel::A73;
@@ -196,4 +196,4 @@
return model;
}
} // namespace cpuinfo
-} // namespace arm_compute
\ No newline at end of file
+} // namespace arm_compute
diff --git a/src/common/cpuinfo/CpuModel.h b/src/common/cpuinfo/CpuModel.h
index 4fe6c29..3b9d9e3 100644
--- a/src/common/cpuinfo/CpuModel.h
+++ b/src/common/cpuinfo/CpuModel.h
@@ -24,11 +24,11 @@
#ifndef SRC_COMMON_CPUINFO_CPUMODEL_H
#define SRC_COMMON_CPUINFO_CPUMODEL_H
+#include "arm_compute/core/CPP/CPPTypes.h"
+
#include <cstdint>
#include <string>
-#include "arm_compute/core/CPP/CPPTypes.h"
-
namespace arm_compute
{
namespace cpuinfo