Update CPU kernels to remove x19
Resolves: COMPMID-5805
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Change-Id: I250f64531e209625e4ff176dd5a552c1c34bc484
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8909
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
diff --git a/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_16_1x8.hpp b/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_16_1x8.hpp
index f52fbba..fa45f4f 100644
--- a/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_16_1x8.hpp
+++ b/src/core/NEON/kernels/arm_gemm/transforms/a64_transpose_interleave_16_1x8.hpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -10,16 +10,16 @@
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
#pragma once
@@ -41,222 +41,222 @@
__asm__ __volatile__(
"1:" // Main row loop: Head
- "mov x28, %x[in]\n"
- "mov x27, %x[out]\n"
- "add x26, x28, %x[in_stride]\n"
+ "mov x9, %x[in]\n"
+ "add x28, x9, %x[in_stride]\n"
+ "add x27, x28, %x[in_stride]\n"
+ "add x26, x27, %x[in_stride]\n"
"add x25, x26, %x[in_stride]\n"
"add x24, x25, %x[in_stride]\n"
"add x23, x24, %x[in_stride]\n"
"add x22, x23, %x[in_stride]\n"
- "add x21, x22, %x[in_stride]\n"
- "add x20, x21, %x[in_stride]\n"
- "add %x[in], x20, %x[in_stride]\n"
"cmp %x[height], #0x7\n"
- "csel x20, x20, %x[pad_row], GT\n"
- "csel x21, x21, %x[pad_row], GE\n"
- "cmp %x[height], #0x5\n"
+ "add %x[in], x22, %x[in_stride]\n"
"csel x22, x22, %x[pad_row], GT\n"
"csel x23, x23, %x[pad_row], GE\n"
- "cmp %x[height], #0x3\n"
+ "cmp %x[height], #0x5\n"
+ "mov x21, %x[width]\n"
"csel x24, x24, %x[pad_row], GT\n"
"csel x25, x25, %x[pad_row], GE\n"
- "cmp %x[height], #0x1\n"
+ "cmp %x[height], #0x3\n"
"csel x26, x26, %x[pad_row], GT\n"
+ "csel x27, x27, %x[pad_row], GE\n"
+ "cmp %x[height], #0x1\n"
+ "csel x28, x28, %x[pad_row], GT\n"
+ "cmp x21, #0x20\n"
+ "mov x20, %x[out]\n"
"sub %x[height], %x[height], #0x8\n"
- "mov x19, %x[width]\n"
- "cmp x19, #0x20\n"
"blt 3f\n"
"2:" // Main row loop: Unroll column loop
- "ldr q17, [x28], #0x10\n"
- "sub x19, x19, #0x20\n"
- "ldr q19, [x26], #0x10\n"
- "cmp x19, #0x20\n"
- "ldr q4, [x25], #0x10\n"
- "ldr q3, [x24], #0x10\n"
- "ldr q16, [x23], #0x10\n"
- "zip1 v2.16b, v17.16b, v16.16b\n"
- "ldr q18, [x28], #0x10\n"
- "zip2 v1.16b, v17.16b, v16.16b\n"
- "ldr q0, [x26], #0x10\n"
- "ldr q31, [x25], #0x10\n"
- "ldr q30, [x24], #0x10\n"
+ "ldr q23, [x9], #0x10\n"
+ "ldr q22, [x28], #0x10\n"
+ "sub x21, x21, #0x20\n"
+ "cmp x21, #0x20\n"
+ "ldr q20, [x27], #0x10\n"
+ "ldr q21, [x26], #0x10\n"
+ "ldr q19, [x25], #0x10\n"
+ "ldr q18, [x24], #0x10\n"
+ "zip1 v5.16b, v23.16b, v19.16b\n"
+ "zip1 v4.16b, v22.16b, v18.16b\n"
"ldr q17, [x23], #0x10\n"
- "zip1 v29.16b, v18.16b, v17.16b\n"
"ldr q16, [x22], #0x10\n"
- "zip2 v28.16b, v18.16b, v17.16b\n"
- "ldr q27, [x21], #0x10\n"
- "ldr q26, [x20], #0x10\n"
- "zip1 v25.16b, v19.16b, v16.16b\n"
- "ldr q24, [x22], #0x10\n"
- "zip2 v21.16b, v19.16b, v16.16b\n"
- "ldr q23, [x21], #0x10\n"
- "zip1 v20.16b, v4.16b, v27.16b\n"
- "ldr q22, [x20], #0x10\n"
- "zip1 v18.16b, v2.16b, v20.16b\n"
- "zip1 v19.16b, v3.16b, v26.16b\n"
- "zip1 v17.16b, v25.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x0]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x10]\n"
- "zip2 v18.16b, v2.16b, v20.16b\n"
- "zip2 v17.16b, v25.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x20]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x30]\n"
- "zip2 v20.16b, v4.16b, v27.16b\n"
- "zip1 v18.16b, v1.16b, v20.16b\n"
- "zip2 v19.16b, v3.16b, v26.16b\n"
- "zip1 v17.16b, v21.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x40]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x50]\n"
- "zip2 v18.16b, v1.16b, v20.16b\n"
- "zip2 v17.16b, v21.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x60]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x70]\n"
- "add x27, x27, %x[out_stride]\n"
- "zip1 v21.16b, v31.16b, v23.16b\n"
- "zip1 v20.16b, v0.16b, v24.16b\n"
- "zip1 v18.16b, v29.16b, v21.16b\n"
- "zip1 v19.16b, v30.16b, v22.16b\n"
- "zip1 v17.16b, v20.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x0]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x10]\n"
- "zip2 v18.16b, v29.16b, v21.16b\n"
- "zip2 v17.16b, v20.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x20]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x30]\n"
- "zip2 v21.16b, v31.16b, v23.16b\n"
- "zip1 v18.16b, v28.16b, v21.16b\n"
- "zip2 v20.16b, v0.16b, v24.16b\n"
- "zip2 v19.16b, v30.16b, v22.16b\n"
- "zip1 v17.16b, v20.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x40]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x50]\n"
- "zip2 v18.16b, v28.16b, v21.16b\n"
- "zip2 v17.16b, v20.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x60]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x70]\n"
- "add x27, x27, %x[out_stride]\n"
+ "zip1 v3.16b, v20.16b, v17.16b\n"
+ "zip1 v31.16b, v21.16b, v16.16b\n"
+ "ldr q25, [x9], #0x10\n"
+ "ldr q24, [x28], #0x10\n"
+ "zip2 v2.16b, v23.16b, v19.16b\n"
+ "zip2 v30.16b, v20.16b, v17.16b\n"
+ "ldr q23, [x27], #0x10\n"
+ "ldr q20, [x26], #0x10\n"
+ "zip2 v22.16b, v22.16b, v18.16b\n"
+ "zip2 v21.16b, v21.16b, v16.16b\n"
+ "ldr q19, [x25], #0x10\n"
+ "ldr q18, [x24], #0x10\n"
+ "zip1 v29.16b, v25.16b, v19.16b\n"
+ "zip1 v28.16b, v24.16b, v18.16b\n"
+ "ldr q17, [x23], #0x10\n"
+ "ldr q16, [x22], #0x10\n"
+ "zip1 v27.16b, v23.16b, v17.16b\n"
+ "zip1 v26.16b, v20.16b, v16.16b\n"
+ "zip2 v1.16b, v25.16b, v19.16b\n"
+ "zip2 v25.16b, v23.16b, v17.16b\n"
+ "zip2 v24.16b, v24.16b, v18.16b\n"
+ "zip2 v16.16b, v20.16b, v16.16b\n"
+ "zip1 v0.16b, v5.16b, v3.16b\n"
+ "zip1 v17.16b, v4.16b, v31.16b\n"
+ "zip2 v20.16b, v5.16b, v3.16b\n"
+ "zip2 v19.16b, v4.16b, v31.16b\n"
+ "zip1 v31.16b, v2.16b, v30.16b\n"
+ "zip1 v18.16b, v22.16b, v21.16b\n"
+ "zip2 v30.16b, v2.16b, v30.16b\n"
+ "zip2 v23.16b, v22.16b, v21.16b\n"
+ "zip1 v22.16b, v29.16b, v27.16b\n"
+ "zip1 v21.16b, v28.16b, v26.16b\n"
+ "zip2 v29.16b, v29.16b, v27.16b\n"
+ "zip2 v28.16b, v28.16b, v26.16b\n"
+ "zip1 v27.16b, v1.16b, v25.16b\n"
+ "zip1 v26.16b, v24.16b, v16.16b\n"
+ "zip2 v25.16b, v1.16b, v25.16b\n"
+ "zip2 v24.16b, v24.16b, v16.16b\n"
+ "zip1 v16.16b, v0.16b, v17.16b\n"
+ "zip2 v17.16b, v0.16b, v17.16b\n"
+ "str q16, [x20, #0x0]\n"
+ "zip1 v16.16b, v20.16b, v19.16b\n"
+ "zip2 v20.16b, v20.16b, v19.16b\n"
+ "str q17, [x20, #0x10]\n"
+ "zip1 v19.16b, v31.16b, v18.16b\n"
+ "zip2 v18.16b, v31.16b, v18.16b\n"
+ "str q16, [x20, #0x20]\n"
+ "zip1 v17.16b, v30.16b, v23.16b\n"
+ "zip2 v16.16b, v30.16b, v23.16b\n"
+ "str q20, [x20, #0x30]\n"
+ "str q19, [x20, #0x40]\n"
+ "zip1 v23.16b, v22.16b, v21.16b\n"
+ "zip2 v22.16b, v22.16b, v21.16b\n"
+ "str q18, [x20, #0x50]\n"
+ "zip1 v21.16b, v29.16b, v28.16b\n"
+ "zip2 v20.16b, v29.16b, v28.16b\n"
+ "str q17, [x20, #0x60]\n"
+ "zip1 v19.16b, v27.16b, v26.16b\n"
+ "zip2 v18.16b, v27.16b, v26.16b\n"
+ "str q16, [x20, #0x70]\n"
+ "add x20, x20, %x[out_stride]\n"
+ "zip1 v17.16b, v25.16b, v24.16b\n"
+ "zip2 v16.16b, v25.16b, v24.16b\n"
+ "str q23, [x20, #0x0]\n"
+ "str q22, [x20, #0x10]\n"
+ "str q21, [x20, #0x20]\n"
+ "str q20, [x20, #0x30]\n"
+ "str q19, [x20, #0x40]\n"
+ "str q18, [x20, #0x50]\n"
+ "str q17, [x20, #0x60]\n"
+ "str q16, [x20, #0x70]\n"
+ "add x20, x20, %x[out_stride]\n"
"bge 2b\n"
"3:" // Main row loop: Unroll column loop skip
- "cmp x19, #0x10\n"
+ "cmp x21, #0x10\n"
"blt 5f\n"
"4:" // Main row loop: Column loop
- "ldr q19, [x28], #0x10\n"
- "sub x19, x19, #0x10\n"
- "ldr q18, [x26], #0x10\n"
- "cmp x19, #0x10\n"
- "ldr q28, [x25], #0x10\n"
- "ldr q27, [x24], #0x10\n"
+ "ldr q25, [x9], #0x10\n"
+ "ldr q27, [x28], #0x10\n"
+ "sub x21, x21, #0x10\n"
+ "cmp x21, #0x10\n"
+ "ldr q26, [x27], #0x10\n"
+ "ldr q24, [x26], #0x10\n"
+ "ldr q22, [x25], #0x10\n"
+ "ldr q21, [x24], #0x10\n"
+ "zip1 v20.16b, v25.16b, v22.16b\n"
+ "zip1 v23.16b, v27.16b, v21.16b\n"
"ldr q17, [x23], #0x10\n"
- "zip1 v26.16b, v19.16b, v17.16b\n"
"ldr q16, [x22], #0x10\n"
- "zip2 v25.16b, v19.16b, v17.16b\n"
- "ldr q24, [x21], #0x10\n"
- "ldr q23, [x20], #0x10\n"
- "zip1 v22.16b, v18.16b, v16.16b\n"
- "zip2 v21.16b, v18.16b, v16.16b\n"
- "zip1 v20.16b, v28.16b, v24.16b\n"
- "zip1 v18.16b, v26.16b, v20.16b\n"
- "zip1 v19.16b, v27.16b, v23.16b\n"
- "zip1 v17.16b, v22.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x0]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x10]\n"
- "zip2 v18.16b, v26.16b, v20.16b\n"
- "zip2 v17.16b, v22.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x20]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x30]\n"
- "zip2 v20.16b, v28.16b, v24.16b\n"
- "zip1 v18.16b, v25.16b, v20.16b\n"
- "zip2 v19.16b, v27.16b, v23.16b\n"
- "zip1 v17.16b, v21.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x40]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x50]\n"
- "zip2 v18.16b, v25.16b, v20.16b\n"
- "zip2 v17.16b, v21.16b, v19.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x60]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x70]\n"
- "add x27, x27, %x[out_stride]\n"
+ "zip1 v19.16b, v26.16b, v17.16b\n"
+ "zip1 v18.16b, v24.16b, v16.16b\n"
+ "zip2 v25.16b, v25.16b, v22.16b\n"
+ "zip2 v22.16b, v26.16b, v17.16b\n"
+ "zip2 v21.16b, v27.16b, v21.16b\n"
+ "zip2 v16.16b, v24.16b, v16.16b\n"
+ "zip1 v24.16b, v20.16b, v19.16b\n"
+ "zip1 v17.16b, v23.16b, v18.16b\n"
+ "zip2 v20.16b, v20.16b, v19.16b\n"
+ "zip2 v19.16b, v23.16b, v18.16b\n"
+ "zip1 v23.16b, v25.16b, v22.16b\n"
+ "zip1 v18.16b, v21.16b, v16.16b\n"
+ "zip2 v22.16b, v25.16b, v22.16b\n"
+ "zip2 v21.16b, v21.16b, v16.16b\n"
+ "zip1 v16.16b, v24.16b, v17.16b\n"
+ "zip2 v17.16b, v24.16b, v17.16b\n"
+ "str q16, [x20, #0x0]\n"
+ "zip1 v16.16b, v20.16b, v19.16b\n"
+ "zip2 v20.16b, v20.16b, v19.16b\n"
+ "str q17, [x20, #0x10]\n"
+ "zip1 v19.16b, v23.16b, v18.16b\n"
+ "zip2 v18.16b, v23.16b, v18.16b\n"
+ "str q16, [x20, #0x20]\n"
+ "zip1 v17.16b, v22.16b, v21.16b\n"
+ "zip2 v16.16b, v22.16b, v21.16b\n"
+ "str q20, [x20, #0x30]\n"
+ "str q19, [x20, #0x40]\n"
+ "str q18, [x20, #0x50]\n"
+ "str q17, [x20, #0x60]\n"
+ "str q16, [x20, #0x70]\n"
+ "add x20, x20, %x[out_stride]\n"
"bge 4b\n"
"5:" // Main row loop: Column loop skip
- "cmp x19, #0x4\n"
+ "cmp x21, #0x4\n"
"blt 7f\n"
"6:" // Main row loop: width 4 loop: loop
- "ldr s17, [x28], #0x4\n"
- "sub x19, x19, #0x4\n"
- "ldr s21, [x26], #0x4\n"
- "cmp x19, #0x4\n"
- "ldr s18, [x25], #0x4\n"
- "ldr s20, [x24], #0x4\n"
- "ldr s16, [x23], #0x4\n"
- "zip1 v19.16b, v17.16b, v16.16b\n"
- "ldr s17, [x22], #0x4\n"
- "ldr s16, [x21], #0x4\n"
- "zip1 v18.16b, v18.16b, v16.16b\n"
- "ldr s16, [x20], #0x4\n"
+ "ldr s18, [x9], #0x4\n"
+ "ldr s19, [x28], #0x4\n"
+ "sub x21, x21, #0x4\n"
+ "cmp x21, #0x4\n"
+ "ldr s21, [x27], #0x4\n"
+ "ldr s20, [x26], #0x4\n"
+ "ldr s17, [x25], #0x4\n"
+ "ldr s16, [x24], #0x4\n"
+ "zip1 v18.16b, v18.16b, v17.16b\n"
+ "zip1 v19.16b, v19.16b, v16.16b\n"
+ "ldr s17, [x23], #0x4\n"
+ "ldr s16, [x22], #0x4\n"
"zip1 v17.16b, v21.16b, v17.16b\n"
- "zip1 v18.16b, v19.16b, v18.16b\n"
"zip1 v16.16b, v20.16b, v16.16b\n"
- "zip1 v17.16b, v17.16b, v16.16b\n"
- "zip1 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x0]\n"
- "zip2 v16.16b, v18.16b, v17.16b\n"
- "str q16, [x27, #0x10]\n"
- "add x27, x27, #0x20\n"
+ "zip1 v18.16b, v18.16b, v17.16b\n"
+ "zip1 v16.16b, v19.16b, v16.16b\n"
+ "zip1 v17.16b, v18.16b, v16.16b\n"
+ "zip2 v16.16b, v18.16b, v16.16b\n"
+ "str q17, [x20, #0x0]\n"
+ "str q16, [x20, #0x10]\n"
+ "add x20, x20, #0x20\n"
"bge 6b\n"
"7:" // Main row loop: width 4 loop: skip
- "cmp x19, #0x1\n"
+ "cmp x21, #0x1\n"
"blt 9f\n"
"8:" // Main row loop: width 1 loop: loop
+ "ldr b19, [x9], #0x1\n"
"ldr b18, [x28], #0x1\n"
- "sub x19, x19, #0x1\n"
- "ldr b21, [x26], #0x1\n"
- "cmp x19, #0x1\n"
+ "sub x21, x21, #0x1\n"
+ "cmp x21, #0x1\n"
+ "ldr b21, [x27], #0x1\n"
+ "ldr b20, [x26], #0x1\n"
"ldr b17, [x25], #0x1\n"
- "ldr b20, [x24], #0x1\n"
- "ldr b16, [x23], #0x1\n"
- "zip1 v19.16b, v18.16b, v16.16b\n"
- "ldr b18, [x22], #0x1\n"
- "ldr b16, [x21], #0x1\n"
- "zip1 v17.16b, v17.16b, v16.16b\n"
- "ldr b16, [x20], #0x1\n"
- "zip1 v18.16b, v21.16b, v18.16b\n"
- "zip1 v17.16b, v19.16b, v17.16b\n"
+ "ldr b16, [x24], #0x1\n"
+ "zip1 v19.16b, v19.16b, v17.16b\n"
+ "zip1 v18.16b, v18.16b, v16.16b\n"
+ "ldr b17, [x23], #0x1\n"
+ "ldr b16, [x22], #0x1\n"
+ "zip1 v17.16b, v21.16b, v17.16b\n"
"zip1 v16.16b, v20.16b, v16.16b\n"
+ "zip1 v17.16b, v19.16b, v17.16b\n"
"zip1 v16.16b, v18.16b, v16.16b\n"
"zip1 v16.16b, v17.16b, v16.16b\n"
- "str d16, [x27, #0x0]\n"
- "add x27, x27, #0x8\n"
+ "str d16, [x20, #0x0]\n"
+ "add x20, x20, #0x8\n"
"bge 8b\n"
"9:" // Main row loop: width 1 loop: skip
- "add %x[out], %x[out], #0x80\n"
"cmp %x[height], #0x1\n"
+ "add %x[out], %x[out], #0x80\n"
"bge 1b\n"
: [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out)
: [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width)
- : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}