commit c4f2743951473f8d97f5a43767fdbb31a4df967c
author Gunes Bayir <gunes.bayir@arm.com> Sun Sep 11 15:59:19 2022 +0100
committer Gunes Bayir <gunes.bayir@arm.com> Fri Sep 16 12:38:59 2022 +0000
tree 26c49b1af8113bb169931f3af5e502904d455a25
parent 0d05b6690fe69c57f63ca43d59b551f074613062

Optimize Quantized/Integer Bilinear Scale for Neon™

This patch introduces several performance optimizations regarding the Bilinear Scale operator with REPLICATE Border mode. Changes apply only to NHWC.

This patch
   - Reduces the memory footprint by disabling precomputation of indices and weights when they're not used
   - Rewrites the kernels for QASYMM8/QASYMM8_SIGNED/U8(Uint8)
   - Adds S8(Int8) Bilinear Scale for Border mode REPLICATE
   - Removes Bilinear Scale SVE kernels for Quantized and Integer types and adjust the heuristics to choose the Neon™ implementation
   - Adds new test cases where the input and output of the Bilinear Scale operator have different quantization scale and offset

Resolves: COMPMID-5453, COMPMID-5454

Change-Id: I3d251e76e0c6978fd5a0a1795ec62ab536bec93c
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8250
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

src/cpu/operators/CpuScale.cpp

diff --git a/src/cpu/operators/CpuScale.cpp b/src/cpu/operators/CpuScale.cpp
index fdb52e5..a13a0f5 100644
--- a/src/cpu/operators/CpuScale.cpp
+++ b/src/cpu/operators/CpuScale.cpp
@@ -215,9 +215,9 @@
                                             _scale_info.interpolation_policy;
         const SamplingPolicy sampling_policy = _scale_info.sampling_policy;
 
-        bool precompute_indices_weights = arm_compute::scale_utils::is_precomputation_required(_data_layout, src->info()->data_type(), policy_to_use);
+        bool precompute_indices_weights = arm_compute::scale_utils::is_precomputation_required(_data_layout, src->info()->data_type(), policy_to_use, _scale_info.border_mode);
 
-        if(precompute_indices_weights == true)
+        if(precompute_indices_weights)
         {
             switch(policy_to_use)
             {

src/cpu/operators/CpuScale.h

diff --git a/src/cpu/operators/CpuScale.h b/src/cpu/operators/CpuScale.h
index f605af6..ee7c523 100644
--- a/src/cpu/operators/CpuScale.h
+++ b/src/cpu/operators/CpuScale.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021-2022 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -45,6 +45,8 @@
      * @param[in, out] src  Source tensor info. Data type supported: QASYMM8/QASYMM8_SIGNED/U8/S16/F16/F32. (Written to only for @p border_mode != UNDEFINED)
      * @param[out]     dst  Destination tensor info. Data type supported: Same as @p src. All but the lowest two dimensions must be the same size as in the input tensor, i.e. scaling is only performed within the XY-plane.
      * @param[in]      info @ref ScaleKernelInfo to be used for configuration
+     *
+     * @note Using S8 data type only supports NHWC, @p border_mode Replicate, and @p policy Bilinear
      */
     void configure(ITensorInfo *src, ITensorInfo *dst, const ScaleKernelInfo &info);
     /** Static function to check if given info will lead to a valid configuration