commit f727ef49e2109bdac105dd6575d2e336adf780a3
author Freddie Liardet <frederick.liardet@arm.com> Mon Oct 18 13:28:57 2021 +0100
committer Sheri Zhang <sheri.zhang@arm.com> Fri Oct 22 13:54:17 2021 +0000
tree bc7e9381fab039cd1281bf189188ece318a4a955
parent 00ff6641b70382a7882b8a04fe67fb4a93ee5675

Add uint8/int8 support to cpu conv3d

Add support for qasymm8/qasymm8_signed in cpu conv3d.

Resolves: COMPMID-4665

Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I2450bb6f24969745c8b936f4b657bd406b788c57
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6478
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>

docs/user_guide/operator_list.dox

diff --git a/docs/user_guide/operator_list.dox b/docs/user_guide/operator_list.dox
index 55bfe38..1dfbdf6 100644
--- a/docs/user_guide/operator_list.dox
+++ b/docs/user_guide/operator_list.dox
@@ -617,6 +617,8 @@
     <tr><th>src0<th>src1<th>src2<th>dst
     <tr><td>F16<td>F16<td>F16<td>F16
     <tr><td>F32<td>F32<td>F32<td>F32
+    <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8
+    <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED
     </table>
 <tr>
   <td>CLConv3D