commit fc94f4d23abd4bc427b701f54ad85282e9ec7872
author Michael Tyler <michael.tyler@arm.com> Tue Jun 04 15:47:37 2024 +0100
committer Michael Tyler <michael.tyler@arm.com> Tue Jun 25 09:10:13 2024 +0000
tree 5e2980599256e2b2f4374e5beb61596fc95c9d5a
parent c2237ec4094c7824f8f7e61bc89504d01c5b59ff

Update CPU kernels and add mixed sign GEMM support

 - Add support for mixed sign quantized convolution.
 - Add support for mixed sign dequantized GEMM.
 - Add SME FP16 GEMV kernel.
 - Change SME vector length function to use RDSVL instead of static variable.
 - Add GEMM dilation support internally (not exposed yet).
 - Remove unused "get_default_activation_values" functions.
 - Add SVE fixed format interleaved BF16 DOT kernel.
 - Updates and optimizations to assembly kernels.

Resolves COMPMID-6926

Change-Id: I227f502502611d4cc4111c89e30c53ce94079544
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11570
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

docs/user_guide/operator_list.dox

diff --git a/docs/user_guide/operator_list.dox b/docs/user_guide/operator_list.dox
index e7f1823..8e828e8 100644
--- a/docs/user_guide/operator_list.dox
+++ b/docs/user_guide/operator_list.dox
@@ -602,6 +602,7 @@
     <tr><td>F16<td>F16<td>F16<td>F16
     <tr><td>F32<td>F32<td>F32<td>F32
     <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8
+    <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>S32<td>QASYMM8
     <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8
     <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED
     <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED
@@ -1762,11 +1763,13 @@
     <table>
     <tr><th>src0<th>src1<th>src2<th>dst
     <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8
+    <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>S32<td>QASYMM8
     <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8
     <tr><td>QASYMM8<td>QSYMM8<td>S32<td>QASYMM8
     <tr><td>QASYMM8<td>QASYMM8<td>S32<td>S32
     <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>S32
     <tr><td>QASYMM8<td>QSYMM8<td>S32<td>S32
+    <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>F32<td>F32
     <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED
     <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED
     <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>QASYMM8_SIGNED