Update CPU kernels and add mixed sign GEMM support
- Add support for mixed sign quantized convolution.
- Add support for mixed sign dequantized GEMM.
- Add SME FP16 GEMV kernel.
- Change SME vector length function to use RDSVL instead of static variable.
- Add GEMM dilation support internally (not exposed yet).
- Remove unused "get_default_activation_values" functions.
- Add SVE fixed format interleaved BF16 DOT kernel.
- Updates and optimizations to assembly kernels.
Resolves COMPMID-6926
Change-Id: I227f502502611d4cc4111c89e30c53ce94079544
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11570
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
diff --git a/docs/user_guide/release_version_and_change_log.dox b/docs/user_guide/release_version_and_change_log.dox
index 16664c8..a82520a 100644
--- a/docs/user_guide/release_version_and_change_log.dox
+++ b/docs/user_guide/release_version_and_change_log.dox
@@ -41,6 +41,15 @@
@section S2_2_changelog Changelog
+v24.07 Public major release
+ - Add support for mixed sign quantized convolution.
+ - Add support for mixed sign dequantized GEMM.
+ - Add SME FP16 GEMV kernel.
+ - Change SME vector length function to use RDSVL instead of static variable.
+ - Remove unused "get_default_activation_values" functions.
+ - Add SVE fixed format interleaved BF16 DOT kernel.
+ - Updates and optimizations to assembly kernels.
+
v24.06 Public minor release
- Enable FP16 in multiple Neon™ kernels for multi_isa + v8a
- Fix OpenMP® thread scheduling for large machine