Georgios Pinitas | 08302c1 | 2021-06-09 10:08:27 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef SRC_COMMON_CPUINFO_CPUISAINFO_H |
| 25 | #define SRC_COMMON_CPUINFO_CPUISAINFO_H |
| 26 | |
| 27 | #include <cstdint> |
| 28 | |
| 29 | namespace arm_compute |
| 30 | { |
| 31 | namespace cpuinfo |
| 32 | { |
| 33 | /** CPU ISA (Instruction Set Architecture) information |
| 34 | * |
| 35 | * Contains ISA related information around the Arm architecture |
| 36 | */ |
| 37 | struct CpuIsaInfo |
| 38 | { |
| 39 | /* SIMD extension support */ |
| 40 | bool neon{ false }; |
| 41 | bool sve{ false }; |
| 42 | bool sve2{ false }; |
| 43 | |
| 44 | /* Data-type extensions support */ |
| 45 | bool fp16{ false }; |
| 46 | bool bf16{ false }; |
Michalis Spyrou | 20fca52 | 2021-06-07 14:23:57 +0100 | [diff] [blame] | 47 | bool svebf16{ false }; |
Georgios Pinitas | 08302c1 | 2021-06-09 10:08:27 +0100 | [diff] [blame] | 48 | |
| 49 | /* Instruction support */ |
| 50 | bool dot{ false }; |
Michalis Spyrou | 20fca52 | 2021-06-07 14:23:57 +0100 | [diff] [blame] | 51 | bool i8mm{ false }; |
| 52 | bool svei8mm{ false }; |
| 53 | bool svef32mm{ false }; |
Georgios Pinitas | 08302c1 | 2021-06-09 10:08:27 +0100 | [diff] [blame] | 54 | }; |
| 55 | |
| 56 | /** Identify ISA related information through system information |
| 57 | * |
| 58 | * @param[in] hwcaps HWCAPS feature information |
| 59 | * @param[in] hwcaps2 HWCAPS2 feature information |
| 60 | * @param[in] midr MIDR value |
| 61 | * |
| 62 | * @return CpuIsaInfo A populated ISA feature structure |
| 63 | */ |
| 64 | CpuIsaInfo init_cpu_isa_from_hwcaps(uint32_t hwcaps, uint32_t hwcaps2, uint32_t midr); |
| 65 | |
| 66 | /** Identify ISA related information through register information |
| 67 | * |
| 68 | * @param[in] isar0 Value of Instruction Set Attribute Register 0 (ID_AA64ISAR0_EL1) |
| 69 | * @param[in] isar1 Value of Instruction Set Attribute Register 1 (ID_AA64ISAR1_EL1) |
| 70 | * @param[in] pfr0 Value of Processor Feature Register 0 (ID_AA64PFR0_EL1) |
| 71 | * @param[in] svefr0 Value of SVE feature ID register 0 (ID_AA64ZFR0_EL1) |
| 72 | * @param[in] midr Value of Main ID Register (MIDR) |
| 73 | * |
| 74 | * @return CpuIsaInfo A populated ISA feature structure |
| 75 | */ |
| 76 | CpuIsaInfo init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t svefr0, uint64_t midr); |
| 77 | } // namespace cpuinfo |
| 78 | } // namespace arm_compute |
| 79 | |
| 80 | #endif /* SRC_COMMON_CPUINFO_CPUISAINFO_H */ |