Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1 | /* |
Pablo Marquez Tello | 2676424 | 2024-02-22 15:52:59 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2021-2024 Arm Limited. |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "arm_gemm.hpp" |
| 26 | |
| 27 | #include <cstddef> |
| 28 | #include <cstdint> |
| 29 | |
| 30 | #if defined(__aarch64__) |
| 31 | |
| 32 | namespace arm_conv { |
| 33 | namespace depthwise { |
| 34 | |
| 35 | void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( |
| 36 | const unsigned int n_channels, |
| 37 | const uint8_t *const *const inptrs, |
| 38 | const int8_t *const weights, |
| 39 | const int32_t *const bias, |
| 40 | const arm_gemm::Requantize32 &qp, |
| 41 | const int32_t *const requant_muls, |
| 42 | const int32_t *const requant_shifts, |
| 43 | uint8_t *const *const outptrs |
| 44 | ) |
| 45 | { |
| 46 | struct Params |
| 47 | { |
Pablo Marquez Tello | 2676424 | 2024-02-22 15:52:59 +0000 | [diff] [blame^] | 48 | uint64_t n_channels; |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 49 | const void *weights; |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 50 | const int32_t *bias; |
| 51 | const arm_gemm::Requantize32 *requant; |
| 52 | const int32_t *const requant_muls; |
| 53 | const int32_t *const requant_shifts; |
| 54 | uint8_t *const *const outptrs; |
| 55 | const uint8_t *inptrs[16]; |
| 56 | |
| 57 | Params( |
| 58 | long unsigned int n_channels, |
| 59 | const uint8_t *const *inptrs_raw, |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 60 | const void *const weights, |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 61 | const int32_t *const bias, |
| 62 | const arm_gemm::Requantize32 &qp, |
| 63 | const int32_t *const requant_muls, |
| 64 | const int32_t *const requant_shifts, |
| 65 | uint8_t *const *outptrs |
| 66 | ) : n_channels(n_channels), weights(weights), bias(bias), |
| 67 | requant(&qp), requant_muls(requant_muls), |
| 68 | requant_shifts(requant_shifts), outptrs(outptrs) |
| 69 | { |
| 70 | inptrs[0] = inptrs_raw[5]; |
| 71 | inptrs[1] = inptrs_raw[0]; |
| 72 | inptrs[2] = inptrs_raw[3]; |
| 73 | inptrs[3] = inptrs_raw[6]; |
| 74 | inptrs[4] = inptrs_raw[9]; |
| 75 | inptrs[5] = inptrs_raw[12]; |
| 76 | inptrs[6] = inptrs_raw[15]; |
| 77 | inptrs[7] = inptrs_raw[1]; |
| 78 | inptrs[8] = inptrs_raw[2]; |
| 79 | inptrs[9] = inptrs_raw[10]; |
| 80 | inptrs[10] = inptrs_raw[4]; |
| 81 | inptrs[11] = inptrs_raw[7]; |
| 82 | inptrs[12] = inptrs_raw[8]; |
| 83 | inptrs[13] = inptrs_raw[11]; |
| 84 | inptrs[14] = inptrs_raw[13]; |
| 85 | inptrs[15] = inptrs_raw[14]; |
| 86 | |
| 87 | } |
| 88 | }; |
| 89 | |
| 90 | const Params params(n_channels, inptrs, weights, bias, qp, |
| 91 | requant_muls, requant_shifts, outptrs); |
| 92 | |
| 93 | __asm__ __volatile__( |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 94 | "ldr x7, [%x[params], %[offsetof_Params_n_channels]]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 95 | "ldr x23, [%x[params], %[offsetof_Params_requant]]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 96 | "lsr x8, x7, #0x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 97 | "add x20, x23, %[offsetof_Requantize32_a_offset]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 98 | "ld1r { v14.16b }, [x20]\n" |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 99 | "ldr x22, [%x[params], %[offsetof_Params_outptrs]]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 100 | "add x21, x23, %[offsetof_Requantize32_b_offset]\n" |
| 101 | "add x20, x23, %[offsetof_Requantize32_c_offset]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 102 | "ld1r { v19.16b }, [x21]\n" |
| 103 | "ld1r { v13.8h }, [x20]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 104 | "add x21, x23, %[offsetof_Requantize32_minval]\n" |
| 105 | "add x20, x23, %[offsetof_Requantize32_maxval]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 106 | "ld1r { v29.8h }, [x21]\n" |
| 107 | "ld1r { v12.8h }, [x20]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 108 | "mov x17, #0x0\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 109 | "mov x16, #0x0\n" |
| 110 | "add x15, %x[params], %[offsetof_Params_inptrs]\n" |
| 111 | "ldr x14, [%x[params], %[offsetof_Params_weights]]\n" |
| 112 | "ldr x13, [%x[params], %[offsetof_Params_requant_muls]]\n" |
| 113 | "ldr x12, [%x[params], %[offsetof_Params_requant_shifts]]\n" |
| 114 | "ldp x11, x10, [x22, #0x0]\n" |
| 115 | "ldp x9, x28, [x22, #0x10]\n" |
| 116 | "cbz x8, 3f\n" |
| 117 | "ldr d23, [x14, #0x0]\n" |
| 118 | "ldr d16, [x14, #0x8]\n" |
| 119 | "subs x8, x8, #0x1\n" |
| 120 | "ssubl v23.8h, v23.8b, v19.8b\n" |
| 121 | "ldr d1, [x14, #0x10]\n" |
| 122 | "ldr d5, [x14, #0x18]\n" |
| 123 | "ssubl v16.8h, v16.8b, v19.8b\n" |
| 124 | "ssubl v1.8h, v1.8b, v19.8b\n" |
| 125 | "ldr d26, [x14, #0x20]\n" |
| 126 | "ldr d18, [x14, #0x28]\n" |
| 127 | "ssubl v5.8h, v5.8b, v19.8b\n" |
| 128 | "ssubl v26.8h, v26.8b, v19.8b\n" |
| 129 | "ldr d31, [x14, #0x30]\n" |
| 130 | "ldr d25, [x14, #0x38]\n" |
| 131 | "ssubl v18.8h, v18.8b, v19.8b\n" |
| 132 | "ssubl v31.8h, v31.8b, v19.8b\n" |
| 133 | "ldr d20, [x14, #0x40]\n" |
| 134 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 135 | "ssubl v25.8h, v25.8b, v19.8b\n" |
| 136 | "ssubl v20.8h, v20.8b, v19.8b\n" |
| 137 | "ldr q9, [x20, #0x0]\n" |
| 138 | "ldr q24, [x20, #0x10]\n" |
| 139 | "add x20, x20, #0x20\n" |
| 140 | "str x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 141 | "ldp x23, x22, [x15, #0x0]\n" |
| 142 | "ldp x21, x20, [x15, #0x10]\n" |
| 143 | "mov v7.16b, v9.16b\n" |
| 144 | "mov v0.16b, v24.16b\n" |
| 145 | "ldr d22, [x23, x17]\n" |
| 146 | "ldr d4, [x22, x17]\n" |
| 147 | "mov v2.16b, v9.16b\n" |
| 148 | "mov v30.16b, v24.16b\n" |
| 149 | "ldr d8, [x21, x17]\n" |
| 150 | "ldr d27, [x20, x17]\n" |
| 151 | "mov v10.16b, v9.16b\n" |
| 152 | "mov v6.16b, v24.16b\n" |
| 153 | "ldr x20, [x15, #0x20]\n" |
| 154 | "ldr d15, [x20, x17]\n" |
| 155 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 156 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 157 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 158 | "usubl v27.8h, v27.8b, v14.8b\n" |
| 159 | "usubl v15.8h, v15.8b, v14.8b\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 160 | "beq 2f\n" |
| 161 | "1:" // Loop |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 162 | "ldr q3, [x13, #0x0]\n" |
| 163 | "ldr q17, [x12, #0x0]\n" |
| 164 | "smlal v9.4s, v22.4h, v26.4h\n" |
| 165 | "smlal2 v24.4s, v22.8h, v26.8h\n" |
| 166 | "ldr q21, [x13, #0x10]\n" |
| 167 | "ldr q28, [x12, #0x10]\n" |
| 168 | "smlal v9.4s, v4.4h, v23.4h\n" |
| 169 | "smlal v7.4s, v22.4h, v5.4h\n" |
| 170 | "ldr x20, [x15, #0x28]\n" |
| 171 | "ldr d11, [x20, x17]\n" |
| 172 | "smlal v2.4s, v22.4h, v16.4h\n" |
| 173 | "smlal v10.4s, v22.4h, v23.4h\n" |
| 174 | "smlal2 v24.4s, v4.8h, v23.8h\n" |
| 175 | "ldr x20, [x15, #0x38]\n" |
| 176 | "ldr d4, [x20, x17]\n" |
| 177 | "smlal v9.4s, v27.4h, v18.4h\n" |
| 178 | "smlal2 v0.4s, v22.8h, v5.8h\n" |
| 179 | "smlal2 v30.4s, v22.8h, v16.8h\n" |
| 180 | "ldr x20, [x15, #0x30]\n" |
| 181 | "usubl v11.8h, v11.8b, v14.8b\n" |
| 182 | "smlal2 v6.4s, v22.8h, v23.8h\n" |
| 183 | "ldr d22, [x20, x17]\n" |
| 184 | "smlal v7.4s, v8.4h, v1.4h\n" |
| 185 | "ldr x20, [x15, #0x40]\n" |
| 186 | "smlal v2.4s, v27.4h, v1.4h\n" |
| 187 | "smlal v10.4s, v27.4h, v16.4h\n" |
| 188 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 189 | "ldr x27, [x15, #0x48]\n" |
| 190 | "smlal2 v24.4s, v27.8h, v18.8h\n" |
| 191 | "smlal v9.4s, v15.4h, v25.4h\n" |
| 192 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 193 | "ldr x26, [x15, #0x50]\n" |
| 194 | "smlal2 v0.4s, v8.8h, v1.8h\n" |
| 195 | "ldr d8, [x20, x17]\n" |
| 196 | "smlal2 v30.4s, v27.8h, v1.8h\n" |
| 197 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 198 | "smlal2 v6.4s, v27.8h, v16.8h\n" |
| 199 | "smlal v7.4s, v27.4h, v26.4h\n" |
| 200 | "ldr x25, [x15, #0x58]\n" |
| 201 | "ldr x24, [x15, #0x60]\n" |
| 202 | "smlal v2.4s, v11.4h, v31.4h\n" |
| 203 | "smlal v10.4s, v15.4h, v5.4h\n" |
| 204 | "ldr x23, [x15, #0x68]\n" |
| 205 | "ldr x22, [x15, #0x70]\n" |
| 206 | "smlal2 v24.4s, v15.8h, v25.8h\n" |
| 207 | "smlal v9.4s, v4.4h, v16.4h\n" |
| 208 | "ldr x21, [x15, #0x78]\n" |
| 209 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 210 | "smlal2 v0.4s, v27.8h, v26.8h\n" |
| 211 | "ldr d27, [x27, x17]\n" |
| 212 | "smlal2 v30.4s, v11.8h, v31.8h\n" |
| 213 | "ldr d11, [x26, x17]\n" |
| 214 | "smlal2 v6.4s, v15.8h, v5.8h\n" |
| 215 | "smlal v7.4s, v15.4h, v31.4h\n" |
| 216 | "usubl v27.8h, v27.8b, v14.8b\n" |
| 217 | "add x14, x14, #0x48\n" |
| 218 | "smlal v2.4s, v15.4h, v26.4h\n" |
| 219 | "smlal v10.4s, v22.4h, v20.4h\n" |
| 220 | "usubl v11.8h, v11.8b, v14.8b\n" |
| 221 | "subs x8, x8, #0x1\n" |
| 222 | "smlal2 v24.4s, v4.8h, v16.8h\n" |
| 223 | "smlal v9.4s, v8.4h, v1.4h\n" |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 224 | "add x13, x13, #0x20\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 225 | "add x12, x12, #0x20\n" |
| 226 | "smlal2 v0.4s, v15.8h, v31.8h\n" |
| 227 | "smlal2 v30.4s, v15.8h, v26.8h\n" |
| 228 | "ldr d15, [x25, x17]\n" |
| 229 | "usubl v15.8h, v15.8b, v14.8b\n" |
| 230 | "smlal2 v6.4s, v22.8h, v20.8h\n" |
| 231 | "ldr d22, [x24, x17]\n" |
| 232 | "smlal v7.4s, v4.4h, v23.4h\n" |
| 233 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 234 | "smlal v2.4s, v27.4h, v18.4h\n" |
| 235 | "smlal v10.4s, v27.4h, v26.4h\n" |
| 236 | "smlal2 v24.4s, v8.8h, v1.8h\n" |
| 237 | "smlal v9.4s, v27.4h, v20.4h\n" |
| 238 | "smlal2 v0.4s, v4.8h, v23.8h\n" |
| 239 | "ldr d4, [x23, x17]\n" |
| 240 | "smlal2 v30.4s, v27.8h, v18.8h\n" |
| 241 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 242 | "smlal2 v6.4s, v27.8h, v26.8h\n" |
| 243 | "ldr d26, [x22, x17]\n" |
| 244 | "smlal v7.4s, v8.4h, v16.4h\n" |
| 245 | "usubl v26.8h, v26.8b, v14.8b\n" |
| 246 | "smlal v2.4s, v11.4h, v23.4h\n" |
| 247 | "smlal v10.4s, v15.4h, v1.4h\n" |
| 248 | "smlal2 v24.4s, v27.8h, v20.8h\n" |
| 249 | "smlal v9.4s, v11.4h, v5.4h\n" |
| 250 | "smlal2 v0.4s, v8.8h, v16.8h\n" |
| 251 | "ldr d8, [x21, x17]\n" |
| 252 | "smlal2 v30.4s, v11.8h, v23.8h\n" |
| 253 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 254 | "smlal2 v6.4s, v15.8h, v1.8h\n" |
| 255 | "smlal v7.4s, v27.4h, v25.4h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 256 | "add x17, x17, #0x8\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 257 | "smlal v2.4s, v22.4h, v5.4h\n" |
| 258 | "smlal v10.4s, v4.4h, v18.4h\n" |
| 259 | "smlal2 v24.4s, v11.8h, v5.8h\n" |
| 260 | "smlal v9.4s, v22.4h, v31.4h\n" |
| 261 | "sqrdmulh v9.4s, v9.4s, v3.4s\n" |
| 262 | "smlal2 v0.4s, v27.8h, v25.8h\n" |
| 263 | "smlal2 v30.4s, v22.8h, v5.8h\n" |
| 264 | "and v27.16b, v9.16b, v17.16b\n" |
| 265 | "smlal2 v6.4s, v4.8h, v18.8h\n" |
| 266 | "smlal v7.4s, v15.4h, v18.4h\n" |
| 267 | "sshr v27.4s, v27.4s, #0x1f\n" |
| 268 | "smlal v2.4s, v26.4h, v25.4h\n" |
| 269 | "smlal v10.4s, v26.4h, v31.4h\n" |
| 270 | "sqadd v9.4s, v9.4s, v27.4s\n" |
| 271 | "smlal2 v24.4s, v22.8h, v31.8h\n" |
| 272 | "smlal2 v0.4s, v15.8h, v18.8h\n" |
| 273 | "sqrdmulh v24.4s, v24.4s, v21.4s\n" |
| 274 | "smlal2 v30.4s, v26.8h, v25.8h\n" |
| 275 | "smlal2 v6.4s, v26.8h, v31.8h\n" |
| 276 | "and v31.16b, v24.16b, v28.16b\n" |
| 277 | "smlal v7.4s, v4.4h, v20.4h\n" |
| 278 | "smlal v2.4s, v8.4h, v20.4h\n" |
| 279 | "sqrdmulh v7.4s, v7.4s, v3.4s\n" |
| 280 | "smlal v10.4s, v8.4h, v25.4h\n" |
| 281 | "smlal2 v0.4s, v4.8h, v20.8h\n" |
| 282 | "sqrdmulh v2.4s, v2.4s, v3.4s\n" |
| 283 | "smlal2 v30.4s, v8.8h, v20.8h\n" |
| 284 | "smlal2 v6.4s, v8.8h, v25.8h\n" |
| 285 | "sqrdmulh v10.4s, v10.4s, v3.4s\n" |
| 286 | "sshr v31.4s, v31.4s, #0x1f\n" |
| 287 | "and v22.16b, v7.16b, v17.16b\n" |
| 288 | "sqrdmulh v0.4s, v0.4s, v21.4s\n" |
| 289 | "and v3.16b, v2.16b, v17.16b\n" |
| 290 | "sqrdmulh v30.4s, v30.4s, v21.4s\n" |
| 291 | "and v11.16b, v10.16b, v17.16b\n" |
| 292 | "sqrdmulh v6.4s, v6.4s, v21.4s\n" |
| 293 | "sqadd v24.4s, v24.4s, v31.4s\n" |
| 294 | "sshr v22.4s, v22.4s, #0x1f\n" |
| 295 | "and v20.16b, v0.16b, v28.16b\n" |
| 296 | "sshr v3.4s, v3.4s, #0x1f\n" |
| 297 | "and v31.16b, v30.16b, v28.16b\n" |
| 298 | "sshr v11.4s, v11.4s, #0x1f\n" |
| 299 | "and v18.16b, v6.16b, v28.16b\n" |
| 300 | "sqadd v7.4s, v7.4s, v22.4s\n" |
| 301 | "sshr v20.4s, v20.4s, #0x1f\n" |
| 302 | "sqadd v2.4s, v2.4s, v3.4s\n" |
| 303 | "sshr v31.4s, v31.4s, #0x1f\n" |
| 304 | "sqadd v10.4s, v10.4s, v11.4s\n" |
| 305 | "sshr v18.4s, v18.4s, #0x1f\n" |
| 306 | "srshl v9.4s, v9.4s, v17.4s\n" |
| 307 | "srshl v7.4s, v7.4s, v17.4s\n" |
| 308 | "sqadd v0.4s, v0.4s, v20.4s\n" |
| 309 | "srshl v2.4s, v2.4s, v17.4s\n" |
| 310 | "sqadd v30.4s, v30.4s, v31.4s\n" |
| 311 | "srshl v10.4s, v10.4s, v17.4s\n" |
| 312 | "sqadd v6.4s, v6.4s, v18.4s\n" |
| 313 | "srshl v24.4s, v24.4s, v28.4s\n" |
| 314 | "sqxtn v9.4h, v9.4s\n" |
| 315 | "srshl v0.4s, v0.4s, v28.4s\n" |
| 316 | "sqxtn v7.4h, v7.4s\n" |
| 317 | "srshl v30.4s, v30.4s, v28.4s\n" |
| 318 | "sqxtn v2.4h, v2.4s\n" |
| 319 | "srshl v6.4s, v6.4s, v28.4s\n" |
| 320 | "sqxtn v10.4h, v10.4s\n" |
| 321 | "sqxtn2 v9.8h, v24.4s\n" |
| 322 | "sqxtn2 v7.8h, v0.4s\n" |
| 323 | "sqxtn2 v2.8h, v30.4s\n" |
| 324 | "sqxtn2 v10.8h, v6.4s\n" |
| 325 | "sqadd v9.8h, v9.8h, v13.8h\n" |
| 326 | "sqadd v7.8h, v7.8h, v13.8h\n" |
| 327 | "sqadd v2.8h, v2.8h, v13.8h\n" |
| 328 | "sqadd v10.8h, v10.8h, v13.8h\n" |
| 329 | "smax v9.8h, v9.8h, v29.8h\n" |
| 330 | "smax v7.8h, v7.8h, v29.8h\n" |
| 331 | "smax v2.8h, v2.8h, v29.8h\n" |
| 332 | "smax v10.8h, v10.8h, v29.8h\n" |
| 333 | "smin v9.8h, v9.8h, v12.8h\n" |
| 334 | "smin v7.8h, v7.8h, v12.8h\n" |
| 335 | "smin v2.8h, v2.8h, v12.8h\n" |
| 336 | "smin v10.8h, v10.8h, v12.8h\n" |
| 337 | "uzp1 v9.16b, v9.16b, v9.16b\n" |
| 338 | "str d9, [x11, x16]\n" |
| 339 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
| 340 | "uzp1 v2.16b, v2.16b, v2.16b\n" |
| 341 | "str d7, [x10, x16]\n" |
| 342 | "uzp1 v10.16b, v10.16b, v10.16b\n" |
| 343 | "str d2, [x9, x16]\n" |
| 344 | "str d10, [x28, x16]\n" |
| 345 | "ldr q9, [x20, #0x0]\n" |
| 346 | "ldr q24, [x20, #0x10]\n" |
| 347 | "add x20, x20, #0x20\n" |
| 348 | "ldr d23, [x14, #0x0]\n" |
| 349 | "ldr d16, [x14, #0x8]\n" |
| 350 | "add x16, x16, #0x8\n" |
| 351 | "str x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 352 | "ldr d1, [x14, #0x10]\n" |
| 353 | "ldr d5, [x14, #0x18]\n" |
| 354 | "mov v7.16b, v9.16b\n" |
| 355 | "mov v0.16b, v24.16b\n" |
| 356 | "ldr d26, [x14, #0x20]\n" |
| 357 | "ldr d18, [x14, #0x28]\n" |
| 358 | "mov v2.16b, v9.16b\n" |
| 359 | "mov v30.16b, v24.16b\n" |
| 360 | "ldr d31, [x14, #0x30]\n" |
| 361 | "ldr d25, [x14, #0x38]\n" |
| 362 | "mov v10.16b, v9.16b\n" |
| 363 | "mov v6.16b, v24.16b\n" |
| 364 | "ldr d20, [x14, #0x40]\n" |
| 365 | "ldp x23, x22, [x15, #0x0]\n" |
| 366 | "ssubl v23.8h, v23.8b, v19.8b\n" |
| 367 | "ssubl v16.8h, v16.8b, v19.8b\n" |
| 368 | "ldp x21, x20, [x15, #0x10]\n" |
| 369 | "ldr d22, [x23, x17]\n" |
| 370 | "ssubl v1.8h, v1.8b, v19.8b\n" |
| 371 | "ssubl v5.8h, v5.8b, v19.8b\n" |
| 372 | "ldr d4, [x22, x17]\n" |
| 373 | "ldr d8, [x21, x17]\n" |
| 374 | "ssubl v26.8h, v26.8b, v19.8b\n" |
| 375 | "ssubl v18.8h, v18.8b, v19.8b\n" |
| 376 | "ldr d27, [x20, x17]\n" |
| 377 | "ldr x20, [x15, #0x20]\n" |
| 378 | "ssubl v31.8h, v31.8b, v19.8b\n" |
| 379 | "ssubl v25.8h, v25.8b, v19.8b\n" |
| 380 | "ldr d15, [x20, x17]\n" |
| 381 | "ssubl v20.8h, v20.8b, v19.8b\n" |
| 382 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 383 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 384 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 385 | "usubl v27.8h, v27.8b, v14.8b\n" |
| 386 | "usubl v15.8h, v15.8b, v14.8b\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 387 | "bgt 1b\n" |
| 388 | "2:" // Tail |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 389 | "ldr q28, [x13, #0x0]\n" |
| 390 | "ldr q17, [x12, #0x0]\n" |
| 391 | "smlal v9.4s, v22.4h, v26.4h\n" |
| 392 | "smlal2 v24.4s, v22.8h, v26.8h\n" |
| 393 | "ldr q21, [x13, #0x10]\n" |
| 394 | "ldr q3, [x12, #0x10]\n" |
| 395 | "smlal v9.4s, v4.4h, v23.4h\n" |
| 396 | "smlal v7.4s, v22.4h, v5.4h\n" |
| 397 | "ldr x20, [x15, #0x28]\n" |
| 398 | "ldr d11, [x20, x17]\n" |
| 399 | "smlal v2.4s, v22.4h, v16.4h\n" |
| 400 | "smlal v10.4s, v22.4h, v23.4h\n" |
| 401 | "smlal2 v24.4s, v4.8h, v23.8h\n" |
| 402 | "ldr x20, [x15, #0x38]\n" |
| 403 | "ldr d4, [x20, x17]\n" |
| 404 | "smlal v9.4s, v27.4h, v18.4h\n" |
| 405 | "smlal2 v0.4s, v22.8h, v5.8h\n" |
| 406 | "smlal2 v30.4s, v22.8h, v16.8h\n" |
| 407 | "ldr x20, [x15, #0x30]\n" |
| 408 | "usubl v11.8h, v11.8b, v14.8b\n" |
| 409 | "smlal2 v6.4s, v22.8h, v23.8h\n" |
| 410 | "ldr d22, [x20, x17]\n" |
| 411 | "smlal v7.4s, v8.4h, v1.4h\n" |
| 412 | "ldr x20, [x15, #0x40]\n" |
| 413 | "smlal v2.4s, v27.4h, v1.4h\n" |
| 414 | "smlal v10.4s, v27.4h, v16.4h\n" |
| 415 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 416 | "ldr x26, [x15, #0x48]\n" |
| 417 | "smlal2 v24.4s, v27.8h, v18.8h\n" |
| 418 | "smlal v9.4s, v15.4h, v25.4h\n" |
| 419 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 420 | "ldr x25, [x15, #0x50]\n" |
| 421 | "smlal2 v0.4s, v8.8h, v1.8h\n" |
| 422 | "ldr d8, [x20, x17]\n" |
| 423 | "smlal2 v30.4s, v27.8h, v1.8h\n" |
| 424 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 425 | "smlal2 v6.4s, v27.8h, v16.8h\n" |
| 426 | "smlal v7.4s, v27.4h, v26.4h\n" |
| 427 | "ldr x24, [x15, #0x58]\n" |
| 428 | "ldr x23, [x15, #0x60]\n" |
| 429 | "smlal v2.4s, v11.4h, v31.4h\n" |
| 430 | "smlal v10.4s, v15.4h, v5.4h\n" |
| 431 | "ldr x22, [x15, #0x68]\n" |
| 432 | "ldr x21, [x15, #0x70]\n" |
| 433 | "smlal2 v24.4s, v15.8h, v25.8h\n" |
| 434 | "smlal v9.4s, v4.4h, v16.4h\n" |
| 435 | "ldr x20, [x15, #0x78]\n" |
| 436 | "tst x7, #0x7\n" |
| 437 | "smlal2 v0.4s, v27.8h, v26.8h\n" |
| 438 | "ldr d27, [x26, x17]\n" |
| 439 | "smlal2 v30.4s, v11.8h, v31.8h\n" |
| 440 | "ldr d11, [x25, x17]\n" |
| 441 | "smlal2 v6.4s, v15.8h, v5.8h\n" |
| 442 | "smlal v7.4s, v15.4h, v31.4h\n" |
| 443 | "usubl v27.8h, v27.8b, v14.8b\n" |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 444 | "add x13, x13, #0x20\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 445 | "smlal v2.4s, v15.4h, v26.4h\n" |
| 446 | "smlal v10.4s, v22.4h, v20.4h\n" |
| 447 | "usubl v11.8h, v11.8b, v14.8b\n" |
| 448 | "add x12, x12, #0x20\n" |
| 449 | "smlal2 v24.4s, v4.8h, v16.8h\n" |
| 450 | "smlal v9.4s, v8.4h, v1.4h\n" |
| 451 | "smlal2 v0.4s, v15.8h, v31.8h\n" |
| 452 | "smlal2 v30.4s, v15.8h, v26.8h\n" |
| 453 | "ldr d15, [x24, x17]\n" |
| 454 | "usubl v15.8h, v15.8b, v14.8b\n" |
| 455 | "smlal2 v6.4s, v22.8h, v20.8h\n" |
| 456 | "ldr d22, [x23, x17]\n" |
| 457 | "smlal v7.4s, v4.4h, v23.4h\n" |
| 458 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 459 | "smlal v2.4s, v27.4h, v18.4h\n" |
| 460 | "smlal v10.4s, v27.4h, v26.4h\n" |
| 461 | "smlal2 v24.4s, v8.8h, v1.8h\n" |
| 462 | "smlal v9.4s, v27.4h, v20.4h\n" |
| 463 | "smlal2 v0.4s, v4.8h, v23.8h\n" |
| 464 | "ldr d4, [x22, x17]\n" |
| 465 | "smlal2 v30.4s, v27.8h, v18.8h\n" |
| 466 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 467 | "smlal2 v6.4s, v27.8h, v26.8h\n" |
| 468 | "ldr d26, [x21, x17]\n" |
| 469 | "smlal v7.4s, v8.4h, v16.4h\n" |
| 470 | "usubl v26.8h, v26.8b, v14.8b\n" |
| 471 | "smlal v2.4s, v11.4h, v23.4h\n" |
| 472 | "smlal v10.4s, v15.4h, v1.4h\n" |
| 473 | "smlal2 v24.4s, v27.8h, v20.8h\n" |
| 474 | "smlal v9.4s, v11.4h, v5.4h\n" |
| 475 | "smlal2 v0.4s, v8.8h, v16.8h\n" |
| 476 | "ldr d16, [x20, x17]\n" |
| 477 | "smlal2 v30.4s, v11.8h, v23.8h\n" |
| 478 | "usubl v16.8h, v16.8b, v14.8b\n" |
| 479 | "smlal2 v6.4s, v15.8h, v1.8h\n" |
| 480 | "smlal v7.4s, v27.4h, v25.4h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 481 | "add x17, x17, #0x8\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 482 | "smlal v2.4s, v22.4h, v5.4h\n" |
| 483 | "smlal v10.4s, v4.4h, v18.4h\n" |
| 484 | "smlal2 v24.4s, v11.8h, v5.8h\n" |
| 485 | "smlal v9.4s, v22.4h, v31.4h\n" |
| 486 | "sqrdmulh v9.4s, v9.4s, v28.4s\n" |
| 487 | "smlal2 v0.4s, v27.8h, v25.8h\n" |
| 488 | "smlal2 v30.4s, v22.8h, v5.8h\n" |
| 489 | "and v1.16b, v9.16b, v17.16b\n" |
| 490 | "smlal2 v6.4s, v4.8h, v18.8h\n" |
| 491 | "smlal v7.4s, v15.4h, v18.4h\n" |
| 492 | "sshr v1.4s, v1.4s, #0x1f\n" |
| 493 | "smlal v2.4s, v26.4h, v25.4h\n" |
| 494 | "smlal v10.4s, v26.4h, v31.4h\n" |
| 495 | "sqadd v9.4s, v9.4s, v1.4s\n" |
| 496 | "smlal2 v24.4s, v22.8h, v31.8h\n" |
| 497 | "smlal2 v0.4s, v15.8h, v18.8h\n" |
| 498 | "sqrdmulh v24.4s, v24.4s, v21.4s\n" |
| 499 | "smlal2 v30.4s, v26.8h, v25.8h\n" |
| 500 | "smlal2 v6.4s, v26.8h, v31.8h\n" |
| 501 | "and v31.16b, v24.16b, v3.16b\n" |
| 502 | "smlal v7.4s, v4.4h, v20.4h\n" |
| 503 | "smlal v2.4s, v16.4h, v20.4h\n" |
| 504 | "sqrdmulh v7.4s, v7.4s, v28.4s\n" |
| 505 | "smlal v10.4s, v16.4h, v25.4h\n" |
| 506 | "smlal2 v0.4s, v4.8h, v20.8h\n" |
| 507 | "sqrdmulh v2.4s, v2.4s, v28.4s\n" |
| 508 | "smlal2 v30.4s, v16.8h, v20.8h\n" |
| 509 | "smlal2 v6.4s, v16.8h, v25.8h\n" |
| 510 | "sqrdmulh v10.4s, v10.4s, v28.4s\n" |
| 511 | "sshr v31.4s, v31.4s, #0x1f\n" |
| 512 | "and v22.16b, v7.16b, v17.16b\n" |
| 513 | "sqrdmulh v0.4s, v0.4s, v21.4s\n" |
| 514 | "and v15.16b, v2.16b, v17.16b\n" |
| 515 | "sqrdmulh v30.4s, v30.4s, v21.4s\n" |
| 516 | "and v11.16b, v10.16b, v17.16b\n" |
| 517 | "sqrdmulh v6.4s, v6.4s, v21.4s\n" |
| 518 | "sqadd v24.4s, v24.4s, v31.4s\n" |
| 519 | "sshr v22.4s, v22.4s, #0x1f\n" |
| 520 | "and v18.16b, v0.16b, v3.16b\n" |
| 521 | "sshr v15.4s, v15.4s, #0x1f\n" |
| 522 | "and v23.16b, v30.16b, v3.16b\n" |
| 523 | "sshr v11.4s, v11.4s, #0x1f\n" |
| 524 | "and v21.16b, v6.16b, v3.16b\n" |
| 525 | "sqadd v7.4s, v7.4s, v22.4s\n" |
| 526 | "sshr v18.4s, v18.4s, #0x1f\n" |
| 527 | "sqadd v2.4s, v2.4s, v15.4s\n" |
| 528 | "sshr v23.4s, v23.4s, #0x1f\n" |
| 529 | "sqadd v10.4s, v10.4s, v11.4s\n" |
| 530 | "sshr v21.4s, v21.4s, #0x1f\n" |
| 531 | "srshl v9.4s, v9.4s, v17.4s\n" |
| 532 | "srshl v7.4s, v7.4s, v17.4s\n" |
| 533 | "sqadd v0.4s, v0.4s, v18.4s\n" |
| 534 | "srshl v2.4s, v2.4s, v17.4s\n" |
| 535 | "sqadd v30.4s, v30.4s, v23.4s\n" |
| 536 | "srshl v10.4s, v10.4s, v17.4s\n" |
| 537 | "sqadd v6.4s, v6.4s, v21.4s\n" |
| 538 | "srshl v24.4s, v24.4s, v3.4s\n" |
| 539 | "sqxtn v9.4h, v9.4s\n" |
| 540 | "srshl v0.4s, v0.4s, v3.4s\n" |
| 541 | "sqxtn v7.4h, v7.4s\n" |
| 542 | "srshl v30.4s, v30.4s, v3.4s\n" |
| 543 | "sqxtn v2.4h, v2.4s\n" |
| 544 | "srshl v6.4s, v6.4s, v3.4s\n" |
| 545 | "sqxtn v10.4h, v10.4s\n" |
| 546 | "sqxtn2 v9.8h, v24.4s\n" |
| 547 | "sqxtn2 v7.8h, v0.4s\n" |
| 548 | "sqxtn2 v2.8h, v30.4s\n" |
| 549 | "sqxtn2 v10.8h, v6.4s\n" |
| 550 | "sqadd v9.8h, v9.8h, v13.8h\n" |
| 551 | "sqadd v7.8h, v7.8h, v13.8h\n" |
| 552 | "sqadd v2.8h, v2.8h, v13.8h\n" |
| 553 | "sqadd v10.8h, v10.8h, v13.8h\n" |
| 554 | "smax v9.8h, v9.8h, v29.8h\n" |
| 555 | "smax v7.8h, v7.8h, v29.8h\n" |
| 556 | "smax v2.8h, v2.8h, v29.8h\n" |
| 557 | "smax v10.8h, v10.8h, v29.8h\n" |
| 558 | "smin v9.8h, v9.8h, v12.8h\n" |
| 559 | "smin v7.8h, v7.8h, v12.8h\n" |
| 560 | "smin v2.8h, v2.8h, v12.8h\n" |
| 561 | "smin v10.8h, v10.8h, v12.8h\n" |
| 562 | "uzp1 v9.16b, v9.16b, v9.16b\n" |
| 563 | "str d9, [x11, x16]\n" |
| 564 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
| 565 | "uzp1 v2.16b, v2.16b, v2.16b\n" |
| 566 | "str d7, [x10, x16]\n" |
| 567 | "uzp1 v10.16b, v10.16b, v10.16b\n" |
| 568 | "str d2, [x9, x16]\n" |
| 569 | "str d10, [x28, x16]\n" |
| 570 | "add x16, x16, #0x8\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 571 | "beq 64f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 572 | "add x14, x14, #0x48\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 573 | "3:" // Oddments |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 574 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 575 | "tbz x7, #2, 5f\n" |
| 576 | "ld1 { v9.4s }, [x20], #0x10\n" |
| 577 | "tbz x7, #1, 4f\n" |
| 578 | "ld1 { v24.d }[0], [x20], #0x8\n" |
| 579 | "tbz x7, #0, 7f\n" |
| 580 | "ld1 { v24.s }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 581 | "b 7f\n" |
| 582 | "4:" // Oddments: Load bias: Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 583 | "tbz x7, #0, 7f\n" |
| 584 | "ld1 { v24.s }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 585 | "b 7f\n" |
| 586 | "5:" // Oddments: Load bias: Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 587 | "tbz x7, #1, 6f\n" |
| 588 | "ld1 { v9.d }[0], [x20], #0x8\n" |
| 589 | "tbz x7, #0, 7f\n" |
| 590 | "ld1 { v9.s }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 591 | "b 7f\n" |
| 592 | "6:" // Oddments: Load bias: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 593 | "tbz x7, #0, 7f\n" |
| 594 | "ld1 { v9.s }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 595 | "7:" // Oddments: Load bias: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 596 | "ldr d23, [x14, #0x0]\n" |
| 597 | "ldr d16, [x14, #0x8]\n" |
| 598 | "mov v7.16b, v9.16b\n" |
| 599 | "mov v0.16b, v24.16b\n" |
| 600 | "ldr d1, [x14, #0x10]\n" |
| 601 | "ldr d5, [x14, #0x18]\n" |
| 602 | "mov v2.16b, v9.16b\n" |
| 603 | "mov v30.16b, v24.16b\n" |
| 604 | "ldr d26, [x14, #0x20]\n" |
| 605 | "ldr d18, [x14, #0x28]\n" |
| 606 | "mov v10.16b, v9.16b\n" |
| 607 | "mov v6.16b, v24.16b\n" |
| 608 | "ldr d31, [x14, #0x30]\n" |
| 609 | "ldr d25, [x14, #0x38]\n" |
| 610 | "ssubl v23.8h, v23.8b, v19.8b\n" |
| 611 | "ssubl v16.8h, v16.8b, v19.8b\n" |
| 612 | "ldr d20, [x14, #0x40]\n" |
| 613 | "ldp x24, x23, [x15, #0x0]\n" |
| 614 | "ssubl v1.8h, v1.8b, v19.8b\n" |
| 615 | "ssubl v5.8h, v5.8b, v19.8b\n" |
| 616 | "ldp x22, x21, [x15, #0x10]\n" |
| 617 | "ldr x20, [x15, #0x20]\n" |
| 618 | "ssubl v26.8h, v26.8b, v19.8b\n" |
| 619 | "ssubl v18.8h, v18.8b, v19.8b\n" |
| 620 | "ssubl v31.8h, v31.8b, v19.8b\n" |
| 621 | "ssubl v25.8h, v25.8b, v19.8b\n" |
| 622 | "ssubl v20.8h, v20.8b, v19.8b\n" |
| 623 | "add x24, x24, x17\n" |
| 624 | "add x23, x23, x17\n" |
| 625 | "add x22, x22, x17\n" |
| 626 | "add x21, x21, x17\n" |
| 627 | "add x20, x20, x17\n" |
| 628 | "tbz x7, #2, 9f\n" |
| 629 | "ld1 { v22.s }[0], [x24], #0x4\n" |
| 630 | "ld1 { v4.s }[0], [x23], #0x4\n" |
| 631 | "ld1 { v8.s }[0], [x22], #0x4\n" |
| 632 | "ld1 { v27.s }[0], [x21], #0x4\n" |
| 633 | "ld1 { v15.s }[0], [x20], #0x4\n" |
| 634 | "tbz x7, #1, 8f\n" |
| 635 | "ld1 { v22.h }[2], [x24], #0x2\n" |
| 636 | "ld1 { v4.h }[2], [x23], #0x2\n" |
| 637 | "ld1 { v8.h }[2], [x22], #0x2\n" |
| 638 | "ld1 { v27.h }[2], [x21], #0x2\n" |
| 639 | "ld1 { v15.h }[2], [x20], #0x2\n" |
| 640 | "tbz x7, #0, 11f\n" |
| 641 | "ld1 { v22.b }[6], [x24]\n" |
| 642 | "ld1 { v4.b }[6], [x23]\n" |
| 643 | "ld1 { v8.b }[6], [x22]\n" |
| 644 | "ld1 { v27.b }[6], [x21]\n" |
| 645 | "ld1 { v15.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 646 | "b 11f\n" |
| 647 | "8:" // Oddments: Initial loads: Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 648 | "tbz x7, #0, 11f\n" |
| 649 | "ld1 { v22.b }[4], [x24]\n" |
| 650 | "ld1 { v4.b }[4], [x23]\n" |
| 651 | "ld1 { v8.b }[4], [x22]\n" |
| 652 | "ld1 { v27.b }[4], [x21]\n" |
| 653 | "ld1 { v15.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 654 | "b 11f\n" |
| 655 | "9:" // Oddments: Initial loads: Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 656 | "tbz x7, #1, 10f\n" |
| 657 | "ld1 { v22.h }[0], [x24], #0x2\n" |
| 658 | "ld1 { v4.h }[0], [x23], #0x2\n" |
| 659 | "ld1 { v8.h }[0], [x22], #0x2\n" |
| 660 | "ld1 { v27.h }[0], [x21], #0x2\n" |
| 661 | "ld1 { v15.h }[0], [x20], #0x2\n" |
| 662 | "tbz x7, #0, 11f\n" |
| 663 | "ld1 { v22.b }[2], [x24]\n" |
| 664 | "ld1 { v4.b }[2], [x23]\n" |
| 665 | "ld1 { v8.b }[2], [x22]\n" |
| 666 | "ld1 { v27.b }[2], [x21]\n" |
| 667 | "ld1 { v15.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 668 | "b 11f\n" |
| 669 | "10:" // Oddments: Initial loads: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 670 | "tbz x7, #0, 11f\n" |
| 671 | "ld1 { v22.b }[0], [x24]\n" |
| 672 | "ld1 { v4.b }[0], [x23]\n" |
| 673 | "ld1 { v8.b }[0], [x22]\n" |
| 674 | "ld1 { v27.b }[0], [x21]\n" |
| 675 | "ld1 { v15.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 676 | "11:" // Oddments: Initial loads: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 677 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 678 | "smlal v9.4s, v22.4h, v26.4h\n" |
| 679 | "smlal2 v24.4s, v22.8h, v26.8h\n" |
| 680 | "ldr x20, [x15, #0x28]\n" |
| 681 | "smlal v7.4s, v22.4h, v5.4h\n" |
| 682 | "smlal2 v0.4s, v22.8h, v5.8h\n" |
| 683 | "usubl v4.8h, v4.8b, v14.8b\n" |
| 684 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 685 | "smlal v2.4s, v22.4h, v16.4h\n" |
| 686 | "smlal2 v30.4s, v22.8h, v16.8h\n" |
| 687 | "add x20, x20, x17\n" |
| 688 | "smlal v10.4s, v22.4h, v23.4h\n" |
| 689 | "smlal2 v6.4s, v22.8h, v23.8h\n" |
| 690 | "usubl v27.8h, v27.8b, v14.8b\n" |
| 691 | "smlal v9.4s, v4.4h, v23.4h\n" |
| 692 | "smlal2 v24.4s, v4.8h, v23.8h\n" |
| 693 | "usubl v15.8h, v15.8b, v14.8b\n" |
| 694 | "smlal v7.4s, v8.4h, v1.4h\n" |
| 695 | "smlal2 v0.4s, v8.8h, v1.8h\n" |
| 696 | "smlal v9.4s, v27.4h, v18.4h\n" |
| 697 | "smlal2 v24.4s, v27.8h, v18.8h\n" |
| 698 | "smlal v7.4s, v27.4h, v26.4h\n" |
| 699 | "smlal2 v0.4s, v27.8h, v26.8h\n" |
| 700 | "smlal v2.4s, v27.4h, v1.4h\n" |
| 701 | "smlal2 v30.4s, v27.8h, v1.8h\n" |
| 702 | "smlal v10.4s, v27.4h, v16.4h\n" |
| 703 | "smlal2 v6.4s, v27.8h, v16.8h\n" |
| 704 | "tbz x7, #2, 13f\n" |
| 705 | "ld1 { v21.s }[0], [x20], #0x4\n" |
| 706 | "tbz x7, #1, 12f\n" |
| 707 | "ld1 { v21.h }[2], [x20], #0x2\n" |
| 708 | "tbz x7, #0, 15f\n" |
| 709 | "ld1 { v21.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 710 | "b 15f\n" |
| 711 | "12:" // Oddments: Load (3, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 712 | "tbz x7, #0, 15f\n" |
| 713 | "ld1 { v21.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 714 | "b 15f\n" |
| 715 | "13:" // Oddments: Load (3, 0): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 716 | "tbz x7, #1, 14f\n" |
| 717 | "ld1 { v21.h }[0], [x20], #0x2\n" |
| 718 | "tbz x7, #0, 15f\n" |
| 719 | "ld1 { v21.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 720 | "b 15f\n" |
| 721 | "14:" // Oddments: Load (3, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 722 | "tbz x7, #0, 15f\n" |
| 723 | "ld1 { v21.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 724 | "15:" // Oddments: Load (3, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 725 | "usubl v21.8h, v21.8b, v14.8b\n" |
| 726 | "smlal v2.4s, v21.4h, v31.4h\n" |
| 727 | "smlal2 v30.4s, v21.8h, v31.8h\n" |
| 728 | "ldr x20, [x15, #0x30]\n" |
| 729 | "smlal v9.4s, v15.4h, v25.4h\n" |
| 730 | "smlal2 v24.4s, v15.8h, v25.8h\n" |
| 731 | "add x20, x20, x17\n" |
| 732 | "smlal v7.4s, v15.4h, v31.4h\n" |
| 733 | "smlal2 v0.4s, v15.8h, v31.8h\n" |
| 734 | "smlal v2.4s, v15.4h, v26.4h\n" |
| 735 | "smlal2 v30.4s, v15.8h, v26.8h\n" |
| 736 | "smlal v10.4s, v15.4h, v5.4h\n" |
| 737 | "smlal2 v6.4s, v15.8h, v5.8h\n" |
| 738 | "tbz x7, #2, 17f\n" |
| 739 | "ld1 { v28.s }[0], [x20], #0x4\n" |
| 740 | "tbz x7, #1, 16f\n" |
| 741 | "ld1 { v28.h }[2], [x20], #0x2\n" |
| 742 | "tbz x7, #0, 19f\n" |
| 743 | "ld1 { v28.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 744 | "b 19f\n" |
| 745 | "16:" // Oddments: Load (3, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 746 | "tbz x7, #0, 19f\n" |
| 747 | "ld1 { v28.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 748 | "b 19f\n" |
| 749 | "17:" // Oddments: Load (3, 3): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 750 | "tbz x7, #1, 18f\n" |
| 751 | "ld1 { v28.h }[0], [x20], #0x2\n" |
| 752 | "tbz x7, #0, 19f\n" |
| 753 | "ld1 { v28.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 754 | "b 19f\n" |
| 755 | "18:" // Oddments: Load (3, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 756 | "tbz x7, #0, 19f\n" |
| 757 | "ld1 { v28.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 758 | "19:" // Oddments: Load (3, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 759 | "usubl v28.8h, v28.8b, v14.8b\n" |
| 760 | "ldr x20, [x15, #0x38]\n" |
| 761 | "smlal v10.4s, v28.4h, v20.4h\n" |
| 762 | "smlal2 v6.4s, v28.8h, v20.8h\n" |
| 763 | "add x20, x20, x17\n" |
| 764 | "tbz x7, #2, 21f\n" |
| 765 | "ld1 { v22.s }[0], [x20], #0x4\n" |
| 766 | "tbz x7, #1, 20f\n" |
| 767 | "ld1 { v22.h }[2], [x20], #0x2\n" |
| 768 | "tbz x7, #0, 23f\n" |
| 769 | "ld1 { v22.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 770 | "b 23f\n" |
| 771 | "20:" // Oddments: Load (0, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 772 | "tbz x7, #0, 23f\n" |
| 773 | "ld1 { v22.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 774 | "b 23f\n" |
| 775 | "21:" // Oddments: Load (0, 1): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 776 | "tbz x7, #1, 22f\n" |
| 777 | "ld1 { v22.h }[0], [x20], #0x2\n" |
| 778 | "tbz x7, #0, 23f\n" |
| 779 | "ld1 { v22.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 780 | "b 23f\n" |
| 781 | "22:" // Oddments: Load (0, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 782 | "tbz x7, #0, 23f\n" |
| 783 | "ld1 { v22.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 784 | "23:" // Oddments: Load (0, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 785 | "usubl v22.8h, v22.8b, v14.8b\n" |
| 786 | "ldr x20, [x15, #0x40]\n" |
| 787 | "smlal v9.4s, v22.4h, v16.4h\n" |
| 788 | "smlal2 v24.4s, v22.8h, v16.8h\n" |
| 789 | "smlal v7.4s, v22.4h, v23.4h\n" |
| 790 | "smlal2 v0.4s, v22.8h, v23.8h\n" |
| 791 | "add x20, x20, x17\n" |
| 792 | "tbz x7, #2, 25f\n" |
| 793 | "ld1 { v21.s }[0], [x20], #0x4\n" |
| 794 | "tbz x7, #1, 24f\n" |
| 795 | "ld1 { v21.h }[2], [x20], #0x2\n" |
| 796 | "tbz x7, #0, 27f\n" |
| 797 | "ld1 { v21.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 798 | "b 27f\n" |
| 799 | "24:" // Oddments: Load (0, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 800 | "tbz x7, #0, 27f\n" |
| 801 | "ld1 { v21.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 802 | "b 27f\n" |
| 803 | "25:" // Oddments: Load (0, 2): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 804 | "tbz x7, #1, 26f\n" |
| 805 | "ld1 { v21.h }[0], [x20], #0x2\n" |
| 806 | "tbz x7, #0, 27f\n" |
| 807 | "ld1 { v21.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 808 | "b 27f\n" |
| 809 | "26:" // Oddments: Load (0, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 810 | "tbz x7, #0, 27f\n" |
| 811 | "ld1 { v21.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 812 | "27:" // Oddments: Load (0, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 813 | "usubl v21.8h, v21.8b, v14.8b\n" |
| 814 | "ldr x20, [x15, #0x48]\n" |
| 815 | "smlal v9.4s, v21.4h, v1.4h\n" |
| 816 | "smlal2 v24.4s, v21.8h, v1.8h\n" |
| 817 | "smlal v7.4s, v21.4h, v16.4h\n" |
| 818 | "smlal2 v0.4s, v21.8h, v16.8h\n" |
| 819 | "add x20, x20, x17\n" |
| 820 | "tbz x7, #2, 29f\n" |
| 821 | "ld1 { v28.s }[0], [x20], #0x4\n" |
| 822 | "tbz x7, #1, 28f\n" |
| 823 | "ld1 { v28.h }[2], [x20], #0x2\n" |
| 824 | "tbz x7, #0, 31f\n" |
| 825 | "ld1 { v28.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 826 | "b 31f\n" |
| 827 | "28:" // Oddments: Load (2, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 828 | "tbz x7, #0, 31f\n" |
| 829 | "ld1 { v28.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 830 | "b 31f\n" |
| 831 | "29:" // Oddments: Load (2, 2): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 832 | "tbz x7, #1, 30f\n" |
| 833 | "ld1 { v28.h }[0], [x20], #0x2\n" |
| 834 | "tbz x7, #0, 31f\n" |
| 835 | "ld1 { v28.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 836 | "b 31f\n" |
| 837 | "30:" // Oddments: Load (2, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 838 | "tbz x7, #0, 31f\n" |
| 839 | "ld1 { v28.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 840 | "31:" // Oddments: Load (2, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 841 | "usubl v28.8h, v28.8b, v14.8b\n" |
| 842 | "ldr x20, [x15, #0x50]\n" |
| 843 | "smlal v9.4s, v28.4h, v20.4h\n" |
| 844 | "smlal2 v24.4s, v28.8h, v20.8h\n" |
| 845 | "smlal v7.4s, v28.4h, v25.4h\n" |
| 846 | "smlal2 v0.4s, v28.8h, v25.8h\n" |
| 847 | "add x20, x20, x17\n" |
| 848 | "smlal v2.4s, v28.4h, v18.4h\n" |
| 849 | "smlal2 v30.4s, v28.8h, v18.8h\n" |
| 850 | "smlal v10.4s, v28.4h, v26.4h\n" |
| 851 | "smlal2 v6.4s, v28.8h, v26.8h\n" |
| 852 | "tbz x7, #2, 33f\n" |
| 853 | "ld1 { v8.s }[0], [x20], #0x4\n" |
| 854 | "tbz x7, #1, 32f\n" |
| 855 | "ld1 { v8.h }[2], [x20], #0x2\n" |
| 856 | "tbz x7, #0, 35f\n" |
| 857 | "ld1 { v8.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 858 | "b 35f\n" |
| 859 | "32:" // Oddments: Load (1, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 860 | "tbz x7, #0, 35f\n" |
| 861 | "ld1 { v8.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 862 | "b 35f\n" |
| 863 | "33:" // Oddments: Load (1, 0): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 864 | "tbz x7, #1, 34f\n" |
| 865 | "ld1 { v8.h }[0], [x20], #0x2\n" |
| 866 | "tbz x7, #0, 35f\n" |
| 867 | "ld1 { v8.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 868 | "b 35f\n" |
| 869 | "34:" // Oddments: Load (1, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 870 | "tbz x7, #0, 35f\n" |
| 871 | "ld1 { v8.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 872 | "35:" // Oddments: Load (1, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 873 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 874 | "ldr x20, [x15, #0x58]\n" |
| 875 | "smlal v9.4s, v8.4h, v5.4h\n" |
| 876 | "smlal2 v24.4s, v8.8h, v5.8h\n" |
| 877 | "smlal v2.4s, v8.4h, v23.4h\n" |
| 878 | "smlal2 v30.4s, v8.8h, v23.8h\n" |
| 879 | "add x20, x20, x17\n" |
| 880 | "tbz x7, #2, 37f\n" |
| 881 | "ld1 { v8.s }[0], [x20], #0x4\n" |
| 882 | "tbz x7, #1, 36f\n" |
| 883 | "ld1 { v8.h }[2], [x20], #0x2\n" |
| 884 | "tbz x7, #0, 39f\n" |
| 885 | "ld1 { v8.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 886 | "b 39f\n" |
| 887 | "36:" // Oddments: Load (1, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 888 | "tbz x7, #0, 39f\n" |
| 889 | "ld1 { v8.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 890 | "b 39f\n" |
| 891 | "37:" // Oddments: Load (1, 3): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 892 | "tbz x7, #1, 38f\n" |
| 893 | "ld1 { v8.h }[0], [x20], #0x2\n" |
| 894 | "tbz x7, #0, 39f\n" |
| 895 | "ld1 { v8.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 896 | "b 39f\n" |
| 897 | "38:" // Oddments: Load (1, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 898 | "tbz x7, #0, 39f\n" |
| 899 | "ld1 { v8.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 900 | "39:" // Oddments: Load (1, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 901 | "usubl v8.8h, v8.8b, v14.8b\n" |
| 902 | "ldr x20, [x15, #0x60]\n" |
| 903 | "smlal v7.4s, v8.4h, v18.4h\n" |
| 904 | "smlal2 v0.4s, v8.8h, v18.8h\n" |
| 905 | "smlal v10.4s, v8.4h, v1.4h\n" |
| 906 | "smlal2 v6.4s, v8.8h, v1.8h\n" |
| 907 | "add x20, x20, x17\n" |
| 908 | "tbz x7, #2, 41f\n" |
| 909 | "ld1 { v17.s }[0], [x20], #0x4\n" |
| 910 | "tbz x7, #1, 40f\n" |
| 911 | "ld1 { v17.h }[2], [x20], #0x2\n" |
| 912 | "tbz x7, #0, 43f\n" |
| 913 | "ld1 { v17.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 914 | "b 43f\n" |
| 915 | "40:" // Oddments: Load (2, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 916 | "tbz x7, #0, 43f\n" |
| 917 | "ld1 { v17.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 918 | "b 43f\n" |
| 919 | "41:" // Oddments: Load (2, 0): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 920 | "tbz x7, #1, 42f\n" |
| 921 | "ld1 { v17.h }[0], [x20], #0x2\n" |
| 922 | "tbz x7, #0, 43f\n" |
| 923 | "ld1 { v17.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 924 | "b 43f\n" |
| 925 | "42:" // Oddments: Load (2, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 926 | "tbz x7, #0, 43f\n" |
| 927 | "ld1 { v17.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 928 | "43:" // Oddments: Load (2, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 929 | "usubl v17.8h, v17.8b, v14.8b\n" |
| 930 | "ldr x20, [x15, #0x68]\n" |
| 931 | "smlal v9.4s, v17.4h, v31.4h\n" |
| 932 | "smlal2 v24.4s, v17.8h, v31.8h\n" |
| 933 | "smlal v2.4s, v17.4h, v5.4h\n" |
| 934 | "smlal2 v30.4s, v17.8h, v5.8h\n" |
| 935 | "add x20, x20, x17\n" |
| 936 | "tbz x7, #2, 45f\n" |
| 937 | "ld1 { v23.s }[0], [x20], #0x4\n" |
| 938 | "tbz x7, #1, 44f\n" |
| 939 | "ld1 { v23.h }[2], [x20], #0x2\n" |
| 940 | "tbz x7, #0, 47f\n" |
| 941 | "ld1 { v23.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 942 | "b 47f\n" |
| 943 | "44:" // Oddments: Load (2, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 944 | "tbz x7, #0, 47f\n" |
| 945 | "ld1 { v23.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 946 | "b 47f\n" |
| 947 | "45:" // Oddments: Load (2, 3): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 948 | "tbz x7, #1, 46f\n" |
| 949 | "ld1 { v23.h }[0], [x20], #0x2\n" |
| 950 | "tbz x7, #0, 47f\n" |
| 951 | "ld1 { v23.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 952 | "b 47f\n" |
| 953 | "46:" // Oddments: Load (2, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 954 | "tbz x7, #0, 47f\n" |
| 955 | "ld1 { v23.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 956 | "47:" // Oddments: Load (2, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 957 | "usubl v23.8h, v23.8b, v14.8b\n" |
| 958 | "ldr x20, [x15, #0x70]\n" |
| 959 | "smlal v7.4s, v23.4h, v20.4h\n" |
| 960 | "smlal2 v0.4s, v23.8h, v20.8h\n" |
| 961 | "smlal v10.4s, v23.4h, v18.4h\n" |
| 962 | "smlal2 v6.4s, v23.8h, v18.8h\n" |
| 963 | "add x20, x20, x17\n" |
| 964 | "tbz x7, #2, 49f\n" |
| 965 | "ld1 { v5.s }[0], [x20], #0x4\n" |
| 966 | "tbz x7, #1, 48f\n" |
| 967 | "ld1 { v5.h }[2], [x20], #0x2\n" |
| 968 | "tbz x7, #0, 51f\n" |
| 969 | "ld1 { v5.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 970 | "b 51f\n" |
| 971 | "48:" // Oddments: Load (3, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 972 | "tbz x7, #0, 51f\n" |
| 973 | "ld1 { v5.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 974 | "b 51f\n" |
| 975 | "49:" // Oddments: Load (3, 1): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 976 | "tbz x7, #1, 50f\n" |
| 977 | "ld1 { v5.h }[0], [x20], #0x2\n" |
| 978 | "tbz x7, #0, 51f\n" |
| 979 | "ld1 { v5.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 980 | "b 51f\n" |
| 981 | "50:" // Oddments: Load (3, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 982 | "tbz x7, #0, 51f\n" |
| 983 | "ld1 { v5.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 984 | "51:" // Oddments: Load (3, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 985 | "usubl v5.8h, v5.8b, v14.8b\n" |
| 986 | "ldr x20, [x15, #0x78]\n" |
| 987 | "smlal v2.4s, v5.4h, v25.4h\n" |
| 988 | "smlal2 v30.4s, v5.8h, v25.8h\n" |
| 989 | "smlal v10.4s, v5.4h, v31.4h\n" |
| 990 | "smlal2 v6.4s, v5.8h, v31.8h\n" |
| 991 | "add x20, x20, x17\n" |
| 992 | "tbz x7, #2, 53f\n" |
| 993 | "ld1 { v23.s }[0], [x20], #0x4\n" |
| 994 | "tbz x7, #1, 52f\n" |
| 995 | "ld1 { v23.h }[2], [x20], #0x2\n" |
| 996 | "tbz x7, #0, 55f\n" |
| 997 | "ld1 { v23.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 998 | "b 55f\n" |
| 999 | "52:" // Oddments: Load (3, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1000 | "tbz x7, #0, 55f\n" |
| 1001 | "ld1 { v23.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1002 | "b 55f\n" |
| 1003 | "53:" // Oddments: Load (3, 2): Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1004 | "tbz x7, #1, 54f\n" |
| 1005 | "ld1 { v23.h }[0], [x20], #0x2\n" |
| 1006 | "tbz x7, #0, 55f\n" |
| 1007 | "ld1 { v23.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1008 | "b 55f\n" |
| 1009 | "54:" // Oddments: Load (3, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1010 | "tbz x7, #0, 55f\n" |
| 1011 | "ld1 { v23.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1012 | "55:" // Oddments: Load (3, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1013 | "usubl v23.8h, v23.8b, v14.8b\n" |
| 1014 | "smlal v2.4s, v23.4h, v20.4h\n" |
| 1015 | "smlal2 v30.4s, v23.8h, v20.8h\n" |
| 1016 | "smlal v10.4s, v23.4h, v25.4h\n" |
| 1017 | "smlal2 v6.4s, v23.8h, v25.8h\n" |
| 1018 | "tbz x7, #2, 57f\n" |
| 1019 | "ld1 { v15.4s }, [x13], #0x10\n" |
| 1020 | "ld1 { v19.4s }, [x12], #0x10\n" |
| 1021 | "tbz x7, #1, 56f\n" |
| 1022 | "ld1 { v18.d }[0], [x13], #0x8\n" |
| 1023 | "ld1 { v22.d }[0], [x12], #0x8\n" |
| 1024 | "tbz x7, #0, 59f\n" |
| 1025 | "ld1 { v18.s }[2], [x13]\n" |
| 1026 | "ld1 { v22.s }[2], [x12]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1027 | "b 59f\n" |
| 1028 | "56:" // Oddments: Load requant params: Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1029 | "tbz x7, #0, 59f\n" |
| 1030 | "ld1 { v18.s }[0], [x13]\n" |
| 1031 | "ld1 { v22.s }[0], [x12]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1032 | "b 59f\n" |
| 1033 | "57:" // Oddments: Load requant params: Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1034 | "tbz x7, #1, 58f\n" |
| 1035 | "ld1 { v15.d }[0], [x13], #0x8\n" |
| 1036 | "ld1 { v19.d }[0], [x12], #0x8\n" |
| 1037 | "tbz x7, #0, 59f\n" |
| 1038 | "ld1 { v15.s }[2], [x13]\n" |
| 1039 | "ld1 { v19.s }[2], [x12]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1040 | "b 59f\n" |
| 1041 | "58:" // Oddments: Load requant params: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1042 | "tbz x7, #0, 59f\n" |
| 1043 | "ld1 { v15.s }[0], [x13]\n" |
| 1044 | "ld1 { v19.s }[0], [x12]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1045 | "59:" // Oddments: Load requant params: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1046 | "sqrdmulh v9.4s, v9.4s, v15.4s\n" |
| 1047 | "and v17.16b, v9.16b, v19.16b\n" |
| 1048 | "add x11, x11, x16\n" |
| 1049 | "add x10, x10, x16\n" |
| 1050 | "sqrdmulh v24.4s, v24.4s, v18.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1051 | "sshr v17.4s, v17.4s, #0x1f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1052 | "add x9, x9, x16\n" |
| 1053 | "add x28, x28, x16\n" |
| 1054 | "and v20.16b, v24.16b, v22.16b\n" |
| 1055 | "sqrdmulh v7.4s, v7.4s, v15.4s\n" |
| 1056 | "sqrdmulh v2.4s, v2.4s, v15.4s\n" |
| 1057 | "sqrdmulh v10.4s, v10.4s, v15.4s\n" |
| 1058 | "sqadd v9.4s, v9.4s, v17.4s\n" |
| 1059 | "sshr v20.4s, v20.4s, #0x1f\n" |
| 1060 | "and v21.16b, v7.16b, v19.16b\n" |
| 1061 | "sqrdmulh v0.4s, v0.4s, v18.4s\n" |
| 1062 | "and v15.16b, v2.16b, v19.16b\n" |
| 1063 | "sqrdmulh v30.4s, v30.4s, v18.4s\n" |
| 1064 | "and v23.16b, v10.16b, v19.16b\n" |
| 1065 | "sqrdmulh v6.4s, v6.4s, v18.4s\n" |
| 1066 | "sqadd v24.4s, v24.4s, v20.4s\n" |
| 1067 | "sshr v21.4s, v21.4s, #0x1f\n" |
| 1068 | "and v18.16b, v0.16b, v22.16b\n" |
| 1069 | "sshr v15.4s, v15.4s, #0x1f\n" |
| 1070 | "and v17.16b, v30.16b, v22.16b\n" |
| 1071 | "sshr v23.4s, v23.4s, #0x1f\n" |
| 1072 | "and v28.16b, v6.16b, v22.16b\n" |
| 1073 | "sqadd v7.4s, v7.4s, v21.4s\n" |
| 1074 | "sshr v18.4s, v18.4s, #0x1f\n" |
| 1075 | "sqadd v2.4s, v2.4s, v15.4s\n" |
| 1076 | "sshr v17.4s, v17.4s, #0x1f\n" |
| 1077 | "sqadd v10.4s, v10.4s, v23.4s\n" |
| 1078 | "sshr v28.4s, v28.4s, #0x1f\n" |
| 1079 | "srshl v9.4s, v9.4s, v19.4s\n" |
| 1080 | "srshl v7.4s, v7.4s, v19.4s\n" |
| 1081 | "sqadd v0.4s, v0.4s, v18.4s\n" |
| 1082 | "srshl v2.4s, v2.4s, v19.4s\n" |
| 1083 | "sqadd v30.4s, v30.4s, v17.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1084 | "srshl v10.4s, v10.4s, v19.4s\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1085 | "sqadd v6.4s, v6.4s, v28.4s\n" |
| 1086 | "srshl v24.4s, v24.4s, v22.4s\n" |
| 1087 | "sqxtn v9.4h, v9.4s\n" |
| 1088 | "srshl v0.4s, v0.4s, v22.4s\n" |
| 1089 | "sqxtn v7.4h, v7.4s\n" |
| 1090 | "srshl v30.4s, v30.4s, v22.4s\n" |
| 1091 | "sqxtn v2.4h, v2.4s\n" |
| 1092 | "srshl v6.4s, v6.4s, v22.4s\n" |
| 1093 | "sqxtn v10.4h, v10.4s\n" |
| 1094 | "sqxtn2 v9.8h, v24.4s\n" |
| 1095 | "sqxtn2 v7.8h, v0.4s\n" |
| 1096 | "sqxtn2 v2.8h, v30.4s\n" |
| 1097 | "sqxtn2 v10.8h, v6.4s\n" |
| 1098 | "sqadd v9.8h, v9.8h, v13.8h\n" |
| 1099 | "sqadd v7.8h, v7.8h, v13.8h\n" |
| 1100 | "sqadd v2.8h, v2.8h, v13.8h\n" |
| 1101 | "sqadd v10.8h, v10.8h, v13.8h\n" |
| 1102 | "smax v9.8h, v9.8h, v29.8h\n" |
| 1103 | "smax v7.8h, v7.8h, v29.8h\n" |
| 1104 | "smax v2.8h, v2.8h, v29.8h\n" |
| 1105 | "smax v10.8h, v10.8h, v29.8h\n" |
| 1106 | "smin v9.8h, v9.8h, v12.8h\n" |
| 1107 | "smin v7.8h, v7.8h, v12.8h\n" |
| 1108 | "smin v2.8h, v2.8h, v12.8h\n" |
| 1109 | "smin v10.8h, v10.8h, v12.8h\n" |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 1110 | "uzp1 v9.16b, v9.16b, v9.16b\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1111 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
| 1112 | "uzp1 v2.16b, v2.16b, v2.16b\n" |
| 1113 | "uzp1 v10.16b, v10.16b, v10.16b\n" |
| 1114 | "tbz x7, #2, 61f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1115 | "st1 { v9.s }[0], [x11], #0x4\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1116 | "st1 { v7.s }[0], [x10], #0x4\n" |
| 1117 | "st1 { v2.s }[0], [x9], #0x4\n" |
| 1118 | "st1 { v10.s }[0], [x28], #0x4\n" |
| 1119 | "tbz x7, #1, 60f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1120 | "st1 { v9.h }[2], [x11], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1121 | "st1 { v7.h }[2], [x10], #0x2\n" |
| 1122 | "st1 { v2.h }[2], [x9], #0x2\n" |
| 1123 | "st1 { v10.h }[2], [x28], #0x2\n" |
| 1124 | "tbz x7, #0, 63f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1125 | "st1 { v9.b }[6], [x11], #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1126 | "st1 { v7.b }[6], [x10], #0x1\n" |
| 1127 | "st1 { v2.b }[6], [x9], #0x1\n" |
| 1128 | "st1 { v10.b }[6], [x28], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1129 | "b 63f\n" |
| 1130 | "60:" // Oddments: Bit 2: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1131 | "tbz x7, #0, 63f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1132 | "st1 { v9.b }[4], [x11], #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1133 | "st1 { v7.b }[4], [x10], #0x1\n" |
| 1134 | "st1 { v2.b }[4], [x9], #0x1\n" |
| 1135 | "st1 { v10.b }[4], [x28], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1136 | "b 63f\n" |
| 1137 | "61:" // Oddments: Bit 2: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1138 | "tbz x7, #1, 62f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1139 | "st1 { v9.h }[0], [x11], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1140 | "st1 { v7.h }[0], [x10], #0x2\n" |
| 1141 | "st1 { v2.h }[0], [x9], #0x2\n" |
| 1142 | "st1 { v10.h }[0], [x28], #0x2\n" |
| 1143 | "tbz x7, #0, 63f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1144 | "st1 { v9.b }[2], [x11], #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1145 | "st1 { v7.b }[2], [x10], #0x1\n" |
| 1146 | "st1 { v2.b }[2], [x9], #0x1\n" |
| 1147 | "st1 { v10.b }[2], [x28], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1148 | "b 63f\n" |
| 1149 | "62:" // Oddments: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1150 | "tbz x7, #0, 63f\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1151 | "st1 { v9.b }[0], [x11], #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1152 | "st1 { v7.b }[0], [x10], #0x1\n" |
| 1153 | "st1 { v2.b }[0], [x9], #0x1\n" |
| 1154 | "st1 { v10.b }[0], [x28], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1155 | "63:" // Oddments: Bit 2: End |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1156 | "64:" // End |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1157 | : |
| 1158 | : [offsetof_Params_bias] "I" (offsetof(Params, bias)), [offsetof_Params_inptrs] "I" (offsetof(Params, inptrs)), [offsetof_Params_n_channels] "I" (offsetof(Params, n_channels)), [offsetof_Params_outptrs] "I" (offsetof(Params, outptrs)), [offsetof_Params_requant] "I" (offsetof(Params, requant)), [offsetof_Params_requant_muls] "I" (offsetof(Params, requant_muls)), [offsetof_Params_requant_shifts] "I" (offsetof(Params, requant_shifts)), [offsetof_Params_weights] "I" (offsetof(Params, weights)), [offsetof_Requantize32_a_offset] "I" (offsetof(arm_gemm::Requantize32, a_offset)), [offsetof_Requantize32_b_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [offsetof_Requantize32_c_offset] "I" (offsetof(arm_gemm::Requantize32, c_offset)), [offsetof_Requantize32_maxval] "I" (offsetof(arm_gemm::Requantize32, maxval)), [offsetof_Requantize32_minval] "I" (offsetof(arm_gemm::Requantize32, minval)), [params] "r" (¶ms) |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1159 | : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1160 | ); |
| 1161 | } |
| 1162 | |
| 1163 | } // namespace depthwise |
| 1164 | } // namespace arm_conv |
| 1165 | |
| 1166 | #endif // defined(__aarch64__) |