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Michalis Spyrou60c3b0e2021-04-08 12:02:58 +01001/*
Pablo Marquez Tello732c1b22023-03-29 11:42:30 +01002 * Copyright (c) 2019-2023 Arm Limited.
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
Georgios Pinitas2eb5d162021-07-02 09:01:49 +010024#ifndef ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_NATIVE_KERNEL_H
25#define ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_NATIVE_KERNEL_H
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010026
27#include "arm_compute/core/utils/misc/Traits.h"
SiCong Li91295492023-07-21 18:16:13 +010028#include "arm_compute/function_info/ConvolutionInfo.h"
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010029#include "src/core/common/Macros.h"
Georgios Pinitas7891a732021-08-20 21:39:25 +010030#include "src/cpu/ICpuKernel.h"
Pablo Marquez Tello732c1b22023-03-29 11:42:30 +010031#include "support/AclRequires.h"
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010032
33#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
34#include <arm_neon.h>
35#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
36
37namespace arm_compute
38{
39namespace cpu
40{
41namespace kernels
42{
43/** Interface for the kernel to run a depthwise convolution native on a tensor. */
Yair Schwarzbaum46d44d22022-01-12 16:38:58 +020044class CpuDepthwiseConv2dNativeKernel : public ICpuKernel<CpuDepthwiseConv2dNativeKernel>
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010045{
Dana Zlotnikebbae942022-02-03 12:52:15 +020046private:
47 using DepthwiseConv2dNativeKernelPtr =
48 std::add_pointer<void(const ITensor *, const ITensor *, const ITensor *, ITensor *, const Window &, bool, const ConvolutionInfo &)>::type;
49
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010050public:
Georgios Pinitas2eb5d162021-07-02 09:01:49 +010051 CpuDepthwiseConv2dNativeKernel() = default;
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010052 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDepthwiseConv2dNativeKernel);
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010053
54 /** Initialize the function's source, destination and parameters.
55 *
56 * @note Supported data layouts: NHWC
57 *
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010058 * @param[in] src Source tensor. DataType supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010059 * @param[in] weights Weights tensor. This is a 3D tensor with dimensions [IFM, W, H].
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010060 * Data type supported: Same as @p src or QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL when @p src is QASYMM8/QASYMM8_SIGNED.
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010061 * @param[in] biases Biases tensor. A 1D tensor with dimensions [IFM]. Must be nullptr if not needed.
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010062 * Data type supported: Same as @p src, S32 when src is QASYMM8/QASYMM8_SIGNED.
63 * @param[out] dst Destination tensor. Data type supported: Same as @p src.
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010064 * @param[in] info Depthwise convolution meta-data.
65 *
66 */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010067 void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const ConvolutionInfo &info);
68 /** Static function to check if given info will lead to a valid configuration
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010069 *
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010070 * Similar to CpuDepthwiseConv2dNativeKernel::configure()
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010071 *
72 * @return a status
73 */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010074 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const ConvolutionInfo &info);
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010075
76 // Inherited methods overridden:
77 void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override;
Georgios Pinitas2eb5d162021-07-02 09:01:49 +010078 const char *name() const override;
Dana Zlotnikebbae942022-02-03 12:52:15 +020079 struct DepthwiseConv2dNativeKernel
80 {
81 const char *name;
82 const DepthwiseConv2dNativeDataTypeISASelectorPtr is_selected;
83 DepthwiseConv2dNativeKernelPtr ukernel;
84 };
85 static const std::vector<DepthwiseConv2dNativeKernel> &get_available_kernels();
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010086
87private:
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010088 /** Common signature for all the specialised depthwise convolution native functions
89 *
90 * @param[in] window Region on which to execute the kernel.
91 */
Dana Zlotnikebbae942022-02-03 12:52:15 +020092 DepthwiseConv2dNativeKernelPtr _func{ nullptr };
93 ConvolutionInfo _conv_info{};
94 bool _has_biases{ false };
Michalis Spyrou60c3b0e2021-04-08 12:02:58 +010095};
96} // namespace kernels
97} // namespace cpu
98} // namespace arm_compute
Georgios Pinitas2eb5d162021-07-02 09:01:49 +010099#endif /* ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_NATIVE_KERNEL_H */