Michele Di Giorgio | 93b75e0 | 2021-06-21 12:00:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016-2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_GEMM_INTERLEAVE4x4_KERNEL_H |
| 25 | #define ARM_COMPUTE_CPU_GEMM_INTERLEAVE4x4_KERNEL_H |
| 26 | |
| 27 | #include "src/core/common/Macros.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 28 | #include "src/cpu/ICpuKernel.h" |
Michele Di Giorgio | 93b75e0 | 2021-06-21 12:00:43 +0100 | [diff] [blame] | 29 | |
| 30 | namespace arm_compute |
| 31 | { |
| 32 | namespace cpu |
| 33 | { |
| 34 | namespace kernels |
| 35 | { |
| 36 | /** Kernel to interleave the elements of a matrix |
| 37 | * |
| 38 | * This function puts the values in a 4x4 block of Matrix A on the same row (Interleaved values) |
| 39 | * |
| 40 | * @f[ |
| 41 | * \left( \begin{array}{cccc} |
| 42 | * a00 & a01 & a02 & a03 \\ |
| 43 | * a10 & a11 & a12 & a13 \\ |
| 44 | * a20 & a21 & a22 & a23 \\ |
| 45 | * a30 & a31 & a32 & a33 \\ |
| 46 | * \end{array} \right) |
| 47 | * \rightarrow |
| 48 | * \left( \begin{array}{ccccccccccccccccc} |
| 49 | * a00 & a10 & a20 & a30 & a01 & a11 & a21 & a31 & a02 & a12 & a22 & a32 & a03 & a13 & a23 & a33 \\ |
| 50 | * \end{array} \right) |
| 51 | * @f] |
| 52 | * |
| 53 | * After this operation, the dst matrix will have the following shape: [ height * 4, ceil(width / 4.0f) ] |
| 54 | */ |
| 55 | class CpuGemmInterleave4x4Kernel : public ICpuKernel |
| 56 | { |
| 57 | public: |
Michele Di Giorgio | 93b75e0 | 2021-06-21 12:00:43 +0100 | [diff] [blame] | 58 | CpuGemmInterleave4x4Kernel() = default; |
Michele Di Giorgio | 93b75e0 | 2021-06-21 12:00:43 +0100 | [diff] [blame] | 59 | /** Initialise the kernel's src and dst. |
| 60 | * |
| 61 | * @param[in] src Input tensor info. Data types supported: All |
| 62 | * @param[out] dst Output tensor info which stores the interleaved matrix. Data type supported: same as @p src. |
| 63 | */ |
| 64 | void configure(const ITensorInfo *src, ITensorInfo *dst); |
| 65 | /** Static function to check if given info will lead to a valid configuration of @ref CpuGemmInterleave4x4Kernel |
| 66 | * |
| 67 | * Similar to @ref CpuGemmInterleave4x4Kernel::configure() |
| 68 | * |
| 69 | * @return a status |
| 70 | */ |
| 71 | static Status validate(const ITensorInfo *src, const ITensorInfo *dst); |
| 72 | |
| 73 | // Inherited methods overridden: |
| 74 | void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; |
| 75 | const char *name() const override; |
Michele Di Giorgio | 93b75e0 | 2021-06-21 12:00:43 +0100 | [diff] [blame] | 76 | }; |
| 77 | } // namespace kernels |
| 78 | } // namespace cpu |
| 79 | } // namespace arm_compute |
Georgios Pinitas | 2eb5d16 | 2021-07-02 09:01:49 +0100 | [diff] [blame] | 80 | #endif /* ARM_COMPUTE_CPU_GEMM_INTERLEAVE4x4_KERNEL_H */ |