Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 24 | #include "src/cpu/operators/CpuGemmDirectConv2d.h" |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 25 | |
| 26 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
| 27 | #include "arm_compute/core/utils/quantization/AsymmHelpers.h" |
| 28 | #include "arm_compute/runtime/FunctionDescriptors.h" |
ramelg01 | 3ae3d88 | 2021-09-12 23:07:47 +0100 | [diff] [blame] | 29 | #include "src/common/utils/Log.h" |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 30 | #include "src/core/helpers/MemoryHelpers.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 31 | #include "src/cpu/utils/CpuAuxTensorHandler.h" |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 32 | |
| 33 | #include "support/Cast.h" |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 34 | |
| 35 | #include <set> |
| 36 | |
| 37 | namespace arm_compute |
| 38 | { |
| 39 | namespace cpu |
| 40 | { |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 41 | using namespace arm_compute::experimental; |
| 42 | using namespace arm_compute::utils::cast; |
| 43 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 44 | namespace |
| 45 | { |
| 46 | GEMMLowpOutputStageInfo calculate_output_stage_metadata(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *dst, const ActivationLayerInfo &act) |
| 47 | { |
| 48 | // Since we need negative offsets for computing convolution, we need to change QuantizationInfo() |
| 49 | // Extract and negate input and weights offset |
| 50 | const QuantizationInfo iqinfo = src->quantization_info(); |
| 51 | const QuantizationInfo wqinfo = weights->quantization_info(); |
| 52 | const QuantizationInfo oqinfo = (dst->total_size() == 0) ? iqinfo : dst->quantization_info(); |
| 53 | const UniformQuantizationInfo uoqinfo = oqinfo.uniform(); |
| 54 | const DataType data_type = src->data_type(); |
| 55 | // Merge activation with output stage |
| 56 | const std::set<ActivationLayerInfo::ActivationFunction> supported_acts = { ActivationLayerInfo::ActivationFunction::RELU, |
| 57 | ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, |
| 58 | ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU |
| 59 | }; |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 60 | PixelValue type_min{}; |
| 61 | PixelValue type_max{}; |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 62 | std::tie(type_min, type_max) = get_min_max(data_type); |
Michele Di Giorgio | 8ae3cda | 2021-06-07 15:30:26 +0100 | [diff] [blame] | 63 | int32_t min_activation = type_min.get<int32_t>(); |
| 64 | int32_t max_activation = type_max.get<int32_t>(); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 65 | if(supported_acts.count(act.activation()) != 0) |
| 66 | { |
| 67 | std::tie(min_activation, max_activation) = get_quantized_activation_min_max(act, data_type, uoqinfo); |
| 68 | } |
| 69 | GEMMLowpOutputStageInfo os_info; |
| 70 | os_info.type = GEMMLowpOutputStageType::QUANTIZE_DOWN_FIXEDPOINT; |
| 71 | os_info.gemmlowp_offset = uoqinfo.offset; |
| 72 | os_info.gemmlowp_min_bound = min_activation; |
| 73 | os_info.gemmlowp_max_bound = max_activation; |
| 74 | os_info.is_quantized_per_channel = (weights->data_type() == DataType::QSYMM8_PER_CHANNEL); |
| 75 | quantization::calculate_quantized_multipliers(iqinfo, wqinfo, oqinfo, os_info); |
| 76 | return os_info; |
| 77 | } |
| 78 | cpu::AsmGemmInfo init_assembly_metadata(const Conv2dInfo &info, bool is_indirect) |
| 79 | { |
| 80 | cpu::AsmGemmInfo asm_info; |
| 81 | asm_info.method = is_indirect ? cpu::AsmConvMethod::Indirect : cpu::AsmConvMethod::Conv; |
| 82 | asm_info.ps_info = info.conv_info; |
| 83 | asm_info.activation_info = info.act_info; |
| 84 | asm_info.depth_output_gemm3d = true; |
| 85 | asm_info.reinterpret_input_as_3d = true; |
| 86 | asm_info.padding_top = info.conv_info.pad_top(); |
| 87 | asm_info.padding_left = info.conv_info.pad_left(); |
| 88 | asm_info.padding_value = 0.f; |
| 89 | asm_info.negated_offsets = false; |
Georgios Pinitas | 4ee8b15 | 2021-07-16 16:16:43 +0100 | [diff] [blame] | 90 | asm_info.fast_mode = info.enable_fast_math; |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 91 | return asm_info; |
| 92 | } |
| 93 | } // namespace |
| 94 | |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 95 | CpuGemmDirectConv2d::CpuGemmDirectConv2d() |
| 96 | : _gemm_asm_func(std::make_unique<CpuGemmAssemblyDispatch>()), |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 97 | _activation_func(std::make_unique<CpuActivation>()), |
| 98 | _weights_permute_func(std::make_unique<CpuPermute>()), |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 99 | _aux_mem(AuxTensorIdx::Count), |
| 100 | _perm_weights(), |
| 101 | _run_activation(false), |
| 102 | _is_prepared(false) |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 103 | { |
| 104 | } |
| 105 | |
| 106 | CpuGemmDirectConv2d::~CpuGemmDirectConv2d() = default; |
| 107 | |
| 108 | void CpuGemmDirectConv2d::configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const Conv2dInfo &info) |
| 109 | { |
| 110 | ARM_COMPUTE_ERROR_ON_NULLPTR(src, weights, dst); |
| 111 | ARM_COMPUTE_ERROR_THROW_ON(CpuGemmDirectConv2d::validate(src, |
| 112 | weights, |
| 113 | biases != nullptr ? biases : nullptr, |
| 114 | dst, |
| 115 | info)); |
ramelg01 | 3ae3d88 | 2021-09-12 23:07:47 +0100 | [diff] [blame] | 116 | ARM_COMPUTE_LOG_PARAMS(src, weights, biases, dst, info); |
| 117 | |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 118 | _run_activation = info.act_info.enabled() && !_gemm_asm_func->is_activation_supported(info.act_info); |
| 119 | _is_prepared = false; |
| 120 | |
| 121 | _weights_permute_func->configure(weights, &_perm_weights, PermutationVector{ 3, 0, 1, 2 }); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 122 | |
| 123 | // Configure assembly dispatch |
| 124 | cpu::AsmGemmInfo asm_info = init_assembly_metadata(info, false); |
| 125 | if(is_data_type_quantized(src->data_type())) |
| 126 | { |
| 127 | asm_info.output_stage = calculate_output_stage_metadata(src, weights, dst, info.act_info); |
| 128 | } |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 129 | _gemm_asm_func->configure(src, &_perm_weights, biases, dst, asm_info); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 130 | |
| 131 | // Configure activation |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 132 | if(_run_activation) |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 133 | { |
| 134 | _activation_func->configure(dst, nullptr, info.act_info); |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | // Add auxiliary memory requirements of the assembly dispatch |
| 138 | auto asm_mem_req = _gemm_asm_func->workspace(); |
| 139 | _aux_mem[AsmGemmWorkspace] = asm_mem_req[AsmGemmWorkspace]; |
| 140 | _aux_mem[Pretranspose] = asm_mem_req[Pretranspose]; |
| 141 | |
| 142 | if(_aux_mem[Pretranspose].size > 0) |
| 143 | { |
| 144 | // Release permuted weights at the of prepare as they are further transposed by the assembly dispatch |
| 145 | _aux_mem[PermutedWeights] = MemoryInfo(offset_int_vec(PermutedWeights), MemoryLifetime::Prepare, weights->total_size()); |
| 146 | } |
| 147 | else |
| 148 | { |
| 149 | _aux_mem[PermutedWeights] = MemoryInfo(offset_int_vec(PermutedWeights), MemoryLifetime::Persistent, weights->total_size()); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 150 | } |
| 151 | } |
| 152 | Status CpuGemmDirectConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const Conv2dInfo &info) |
| 153 | { |
| 154 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, weights, dst); |
| 155 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::BFLOAT16, DataType::F16, DataType::F32); |
| 156 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(weights, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM8_PER_CHANNEL, DataType::BFLOAT16, DataType::F16, DataType::F32); |
| 157 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, weights); |
| 158 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.num_groups > 1, "Grouping (num_groups != 1) is not supported on Neon"); |
| 159 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src->data_layout() != DataLayout::NHWC, "Data layout supported is NHWC"); |
| 160 | const DataType data_type = src->data_type(); |
| 161 | const TensorShape i_shape = src->tensor_shape(); |
| 162 | const TensorShape w_shape = weights->tensor_shape(); |
| 163 | ARM_COMPUTE_RETURN_ERROR_ON(w_shape[0] != i_shape[0]); |
| 164 | ARM_COMPUTE_RETURN_ERROR_ON(info.dilation != Size2D(1U, 1U)); |
| 165 | ARM_COMPUTE_RETURN_ERROR_ON(weights->num_dimensions() > 4); |
| 166 | // Validate biases |
| 167 | if(biases != nullptr) |
| 168 | { |
| 169 | if(is_data_type_quantized_asymmetric(data_type)) |
| 170 | { |
| 171 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(biases, 1, DataType::S32); |
| 172 | } |
| 173 | else if(data_type == DataType::BFLOAT16) |
| 174 | { |
| 175 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(biases, 1, DataType::F32); |
| 176 | } |
| 177 | else |
| 178 | { |
| 179 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, biases); |
| 180 | } |
| 181 | ARM_COMPUTE_RETURN_ERROR_ON(biases->dimension(0) != weights->dimension(3)); |
| 182 | ARM_COMPUTE_RETURN_ERROR_ON(biases->num_dimensions() > 1); |
| 183 | } |
| 184 | |
| 185 | cpu::AsmGemmInfo asm_info = init_assembly_metadata(info, false); |
| 186 | ARM_COMPUTE_RETURN_ON_ERROR(cpu::CpuGemmAssemblyDispatch::validate(src, weights, biases, dst, asm_info)); |
| 187 | return Status{}; |
| 188 | } |
| 189 | void CpuGemmDirectConv2d::run(ITensorPack &tensors) |
| 190 | { |
| 191 | prepare(tensors); |
| 192 | |
| 193 | _gemm_asm_func->run(tensors); |
| 194 | if(_run_activation) |
| 195 | { |
| 196 | _activation_func->run(tensors); |
| 197 | } |
Michele Di Giorgio | 8ae3cda | 2021-06-07 15:30:26 +0100 | [diff] [blame] | 198 | } |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 199 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 200 | void CpuGemmDirectConv2d::prepare(ITensorPack &tensors) |
| 201 | { |
| 202 | if(!_is_prepared) |
| 203 | { |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 204 | const ITensor *weights = tensors.get_const_tensor(ACL_SRC_1); |
| 205 | ITensor *weights_aux = utils::cast::polymorphic_cast<ITensor *>(tensors.get_tensor(offset_int_vec(PermutedWeights))); |
| 206 | ARM_COMPUTE_ERROR_ON_NULLPTR(weights, weights_aux); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 207 | |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 208 | CpuAuxTensorHandler permuted_weights(_perm_weights, *weights_aux); |
| 209 | ITensorPack permute_tensors{ { ACL_SRC, weights }, { ACL_DST, permuted_weights.get() } }; |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 210 | _weights_permute_func->run(permute_tensors); |
| 211 | |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 212 | tensors.add_const_tensor(ACL_SRC_1, permuted_weights.get()); |
| 213 | // Call prepare of assembly dispatch |
| 214 | _gemm_asm_func->prepare(tensors); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 215 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 216 | _is_prepared = true; |
| 217 | } |
| 218 | } |
| 219 | |
Michele Di Giorgio | d7316eb | 2021-06-16 11:14:41 +0100 | [diff] [blame] | 220 | experimental::MemoryRequirements CpuGemmDirectConv2d::workspace() const |
| 221 | { |
| 222 | return _aux_mem; |
| 223 | } |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 224 | } // namespace cpu |
| 225 | } // namespace arm_compute |