Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 1 | /* |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 2 | * Copyright (c) 2021-2022 Arm Limited. |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_WINOGRAD_CONV2D_KERNEL_H |
| 25 | #define ARM_COMPUTE_CPU_WINOGRAD_CONV2D_KERNEL_H |
| 26 | |
| 27 | #include "arm_compute/core/TensorInfo.h" |
| 28 | #include "arm_compute/runtime/FunctionDescriptors.h" |
| 29 | #include "src/core/common/Macros.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 30 | #include "src/cpu/ICpuOperator.h" |
| 31 | #include "src/cpu/kernels/CpuWinogradConv2dKernel.h" |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 32 | #include "src/cpu/kernels/assembly/gemm_common.hpp" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 33 | #include "src/cpu/operators/CpuActivation.h" |
| 34 | #include "src/cpu/operators/CpuGemm.h" |
| 35 | #include "src/cpu/operators/CpuPermute.h" |
| 36 | #include "src/cpu/operators/internal/CpuGemmAssemblyDispatch.h" |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 37 | |
| 38 | namespace arm_compute |
| 39 | { |
| 40 | namespace cpu |
| 41 | { |
| 42 | class CpuWinogradConv2d : public ICpuOperator |
| 43 | { |
| 44 | public: |
| 45 | /** Constructor */ |
| 46 | CpuWinogradConv2d(); |
| 47 | ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuWinogradConv2d); |
| 48 | /** Destructor */ |
| 49 | ~CpuWinogradConv2d(); |
| 50 | |
| 51 | /** Set the input and output tensors. |
| 52 | * |
| 53 | * Valid data layouts: |
| 54 | * - NHWC |
| 55 | * - NCHW |
| 56 | * |
| 57 | * Valid data type configurations: |
| 58 | * |src0 |src1 |src2 |dst | |
| 59 | * |:--------------|:--------------|:------|:--------------| |
| 60 | * |F16 |F16 |F16 |F16 | |
| 61 | * |F32 |F32 |F32 |F32 | |
| 62 | * |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 63 | * @param[in] src Source tensor Info. 3 lower dimensions represent a single input [width, height, IFM], |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 64 | * while every optional dimension from 4 and above represent a batch of inputs. |
| 65 | * Data types supported: F16/F32. |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 66 | * @param[in] weights Weights tensor Info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. Data type supported: Same as @p input. |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 67 | * Currently only 3x3 and 5x5 kernels are supported. |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 68 | * @param[in] biases Biases tensor Info. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. Data type supported: Same as @p weights. |
| 69 | * @param[out] dst Destination tensor Info. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs. |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 70 | * Data types supported: Same as @p input. |
| 71 | * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo. Currently only unit strides are supported. |
| 72 | * @param[in] act_info (Optional) Activation layer information in case of a fused activation. |
| 73 | * @param[in] enable_fast_math (Optional) Enable fast math computation. In case this flag were set, the function could dispatch the fastest implementation |
| 74 | * available which may introduce a drop of accuracy as well. Default is false |
| 75 | */ |
| 76 | void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const PadStrideInfo &conv_info, |
| 77 | const ActivationLayerInfo &act_info = ActivationLayerInfo(), |
| 78 | bool enable_fast_math = false); |
| 79 | /** Static function to check if given info will lead to a valid configuration of @ref CpuWinogradConv2d |
| 80 | * |
| 81 | * Similar to CpuWinogradConv2d::configure() |
| 82 | * |
| 83 | * @return a status |
| 84 | */ |
Michele Di Giorgio | d9cdf14 | 2021-07-02 15:17:08 +0100 | [diff] [blame] | 85 | static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const PadStrideInfo &conv_info, |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 86 | const ActivationLayerInfo &act_info = ActivationLayerInfo(), |
| 87 | bool enable_fast_math = false); |
| 88 | |
| 89 | // Inherited methods overridden: |
| 90 | void run(ITensorPack &tensors) override; |
| 91 | void prepare(ITensorPack &constants) override; |
| 92 | experimental::MemoryRequirements workspace() const override; |
| 93 | |
| 94 | private: |
| 95 | enum AuxTensorIdx |
| 96 | { |
Georgios Pinitas | 87a74ef | 2021-08-20 17:26:45 +0100 | [diff] [blame] | 97 | GemmWorkspace = 0, |
| 98 | Pretranspose = 1, |
| 99 | InterleavedLHS = 2, |
| 100 | TransposedRHS = 3, |
| 101 | TempResult = 4, |
| 102 | TransformedInput = 5, |
| 103 | TransformedOutput = 6, |
| 104 | WorkspaceIO = 7, |
| 105 | TransformedWeights = 8, |
| 106 | PermutedWeights = 9, |
| 107 | PermutedInput = TransformedOutput, |
| 108 | PermutedOutput = TransformedInput, |
| 109 | Count = 10 |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 110 | }; |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 111 | std::unique_ptr<CpuGemm> _gemm_function; |
| 112 | std::unique_ptr<CpuActivation> _activation_func; |
| 113 | std::unique_ptr<ICPPKernel> _transform_input_kernel; |
| 114 | std::unique_ptr<ICPPKernel> _transform_output_kernel; |
| 115 | std::unique_ptr<CpuPermute> _permute_input; |
| 116 | std::unique_ptr<CpuPermute> _permute_output; |
| 117 | std::unique_ptr<CpuPermute> _permute_weights; |
| 118 | experimental::MemoryRequirements _aux_mem{ Count }; |
| 119 | std::unique_ptr<arm_conv::ConvolutionArgs> _conv_args; // Make it unique ptr because this type does not have a default constructor |
| 120 | arm_conv::winograd::WinogradImpl _winograd_impl; |
| 121 | DataLayout _data_layout; |
| 122 | TensorInfo _winograd_transformed_input; |
| 123 | TensorInfo _winograd_transformed_output; |
| 124 | TensorInfo _winograd_transformed_weights; |
| 125 | TensorInfo _input_workspace; |
| 126 | TensorInfo _output_workspace; |
| 127 | TensorInfo _weights_hwio; |
| 128 | TensorInfo _input_nhwc; |
| 129 | TensorInfo _output_nhwc; |
| 130 | bool _is_prepared; |
| 131 | bool _run_activation; |
Michalis Spyrou | 96f977e | 2021-07-01 12:20:56 +0100 | [diff] [blame] | 132 | }; |
| 133 | } // namespace cpu |
| 134 | } // namespace arm_compute |
| 135 | |
| 136 | #endif /* ARM_COMPUTE_CPU_WINOGRAD_CONV2D_KERNEL_H */ |