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Michele Di Giorgio19289042021-02-03 16:05:00 +00001/*
2 * Copyright (c) 2021 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010024#ifndef ARM_COMPUTE_CPU_POOL2D_H
25#define ARM_COMPUTE_CPU_POOL2D_H
Michele Di Giorgio19289042021-02-03 16:05:00 +000026
Michele Di Giorgio0c19cbd2021-05-11 17:41:32 +010027#include "arm_compute/core/experimental/Types.h"
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010028#include "src/core/common/Macros.h"
29#include "src/runtime/cpu/ICpuOperator.h"
Michele Di Giorgio19289042021-02-03 16:05:00 +000030
31#include <memory>
32
33namespace arm_compute
34{
35// Forward Declarations
36struct PoolingLayerInfo;
37
38namespace cpu
39{
Michele Di Giorgio33f41fa2021-03-09 14:09:08 +000040/** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following kernels:
Michele Di Giorgio19289042021-02-03 16:05:00 +000041 *
42 * -# @ref NEFillBorderKernel (executed if padding size is different from zero)
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010043 * -# @ref kernels::CpuPool2dKernel
44 * -# @ref kernels::CpuPool2dAssemblyWrapperKernel
Michele Di Giorgio19289042021-02-03 16:05:00 +000045 */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010046class CpuPool2d : public ICpuOperator
Michele Di Giorgio19289042021-02-03 16:05:00 +000047{
48public:
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010049 CpuPool2d();
50 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuPool2d);
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010051 ~CpuPool2d();
Michele Di Giorgio19289042021-02-03 16:05:00 +000052 /** Set the src and dst tensors.
53 *
54 * @note F16 is supported for pool sizes 2 and 3 only
55 *
56 * @param[in, out] src Source tensor info. (Written to only when padding != 0) Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
57 * @param[out] dst Destination tensor info. Data types supported: same as @p src.
58 * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo.
59 * @param[out] indices (optional) The indices of the maximal values. Data type supported: U32.
60 */
61 void configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &pool_info, ITensorInfo *indices = nullptr);
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010062 /** Static function to check if given info will lead to a valid configuration
Michele Di Giorgio19289042021-02-03 16:05:00 +000063 *
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010064 * Similar to CpuPool2d::configure()
Michele Di Giorgio19289042021-02-03 16:05:00 +000065 *
66 * @return a status
67 */
68 static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const PoolingLayerInfo &pool_info, const ITensorInfo *indices = nullptr);
69
70 // Inherited methods overridden:
71 void run(ITensorPack &tensors) override;
Michele Di Giorgio0c19cbd2021-05-11 17:41:32 +010072 experimental::MemoryRequirements workspace() const override;
Michele Di Giorgio19289042021-02-03 16:05:00 +000073
74private:
Michele Di Giorgio0c19cbd2021-05-11 17:41:32 +010075 std::unique_ptr<INEKernel> _pooling_layer_kernel;
76 std::unique_ptr<INEKernel> _border_handler;
77 std::unique_ptr<INEKernel> _asm_glue;
Michele Di Giorgio19289042021-02-03 16:05:00 +000078
Michele Di Giorgio0c19cbd2021-05-11 17:41:32 +010079 bool _is_global_pooling_layer;
80 DataLayout _data_layout;
Manuel Bottini94f799e2021-06-09 16:37:32 +010081 experimental::MemoryRequirements _aux_mem{};
Michele Di Giorgio19289042021-02-03 16:05:00 +000082};
83} // namespace cpu
84} // namespace arm_compute
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010085#endif /* ARM_COMPUTE_CPU_POOL2D_H */