blob: b64f769459d4620b82fa3f9d0e4ca0d56306c6d1 [file] [log] [blame]
Anthony Barbier6ff3b192017-09-04 18:44:23 +01001/*
2 * Copyright (c) 2017 ARM Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24#include "arm_compute/runtime/NEON/functions/NEGEMMLowp.h"
25
26#include "arm_compute/core/Error.h"
27#include "arm_compute/core/Helpers.h"
28#include "arm_compute/core/ITensor.h"
29#include "arm_compute/core/TensorInfo.h"
30#include "arm_compute/core/Types.h"
31#include "arm_compute/core/Validate.h"
32#include "arm_compute/runtime/NEON/NEScheduler.h"
33#include "arm_compute/runtime/TensorAllocator.h"
34
35using namespace arm_compute;
36
37NEGEMMLowp::NEGEMMLowp()
38 : _interleave_kernel(), _transpose_kernel(), _mm_kernel(), _tmp_a(), _tmp_b()
39{
40}
41
42void NEGEMMLowp::configure(const ITensor *a, const ITensor *b, ITensor *output, int32_t a_offset, int32_t b_offset, int32_t output_offset, int32_t output_mult_int, int32_t shift)
43{
44 ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(a, 1, DataType::U8);
45 ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(b, 1, DataType::U8);
46 ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(output, 1, DataType::U8);
47 ARM_COMPUTE_ERROR_ON_MISMATCHING_DATA_TYPES(a, b, output);
48 ARM_COMPUTE_ERROR_ON_MSG(a->info()->dimension(0) != b->info()->dimension(1), "The product AB is defined only if the number of columns in A is equal to the number of rows in B");
49 ARM_COMPUTE_ERROR_ON_MSG(a->info()->dimension(1) != output->info()->dimension(1), "The C matrix must have the same number of rows as the matrix A");
50 ARM_COMPUTE_ERROR_ON_MSG(b->info()->dimension(0) != output->info()->dimension(0), "The C matrix must have the same number of columns as the matrix C");
51
52 /* The interleaved output matrix will have the following shape: [ a_height * 4, ceil(a_width / 4.0f) ] */
53 TensorShape shape_tmp_a = a->info()->tensor_shape();
54 shape_tmp_a.set(0, a->info()->dimension(0) * 4);
55 shape_tmp_a.set(1, std::ceil(a->info()->dimension(1) / 4.f));
56
57 TensorShape shape_tmp_b = b->info()->tensor_shape();
58 shape_tmp_b.set(0, b->info()->dimension(1) * 16);
59 shape_tmp_b.set(1, std::ceil(b->info()->dimension(0) / 16.f));
60
61 TensorInfo info_a(shape_tmp_a, 1, a->info()->data_type());
62 TensorInfo info_b(shape_tmp_b, 1, b->info()->data_type());
63 _tmp_a.allocator()->init(info_a);
64 _tmp_b.allocator()->init(info_b);
65
66 _interleave_kernel.configure(a, &_tmp_a);
67 _transpose_kernel.configure(b, &_tmp_b);
68 _mm_kernel.configure(&_tmp_a, &_tmp_b, output, a_offset, b_offset, output_offset, output_mult_int, shift);
69
70 _tmp_a.allocator()->allocate();
71 _tmp_b.allocator()->allocate();
72}
73
74void NEGEMMLowp::run()
75{
76 /* Run interleave kernel */
77 NEScheduler::get().schedule(&_interleave_kernel, Window::DimY);
78
79 /* Run transpose kernel */
80 NEScheduler::get().schedule(&_transpose_kernel, Window::DimY);
81
82 /* Run matrix multiply kernel */
83 NEScheduler::get().schedule(&_mm_kernel, Window::DimY);
84}