Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 1 | /* |
Michele Di Giorgio | 1e0208a | 2021-01-22 15:42:59 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2021 Arm Limited. |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "arm_compute/runtime/CL/functions/CLLogicalAnd.h" |
| 25 | #include "arm_compute/core/CL/ICLTensor.h" |
Michele Di Giorgio | 1e0208a | 2021-01-22 15:42:59 +0000 | [diff] [blame] | 26 | #include "src/core/gpu/cl/kernels/ClElementwiseKernel.h" |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 27 | |
| 28 | #include <utility> |
| 29 | |
| 30 | namespace arm_compute |
| 31 | { |
| 32 | namespace experimental |
| 33 | { |
| 34 | void CLLogicalAnd::configure(const CLCompileContext &compile_context, ITensorInfo *input1, ITensorInfo *input2, ITensorInfo *output) |
| 35 | { |
Michele Di Giorgio | 1e0208a | 2021-01-22 15:42:59 +0000 | [diff] [blame] | 36 | auto k = std::make_unique<arm_compute::opencl::kernels::ClLogicalBinaryKernel>(); |
| 37 | k->configure(compile_context, LogicalOperation::And, input1, input2, output); |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 38 | _kernel = std::move(k); |
| 39 | } |
| 40 | |
| 41 | Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) |
| 42 | { |
Michele Di Giorgio | 1e0208a | 2021-01-22 15:42:59 +0000 | [diff] [blame] | 43 | return arm_compute::opencl::kernels::ClLogicalBinaryKernel::validate(LogicalOperation::And, input1, input2, output); |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | void CLLogicalAnd::run(ITensorPack &tensors) |
| 47 | { |
| 48 | ICLOperator::run(tensors); |
| 49 | } |
| 50 | } // namespace experimental |
| 51 | |
| 52 | struct CLLogicalAnd::Impl |
| 53 | { |
| 54 | const ICLTensor *src0{ nullptr }; |
| 55 | const ICLTensor *src1{ nullptr }; |
| 56 | ICLTensor *dst{ nullptr }; |
| 57 | std::unique_ptr<experimental::CLLogicalAnd> op{ nullptr }; |
| 58 | }; |
| 59 | |
| 60 | CLLogicalAnd::CLLogicalAnd() |
Georgios Pinitas | 40f51a6 | 2020-11-21 03:04:18 +0000 | [diff] [blame] | 61 | : _impl(std::make_unique<Impl>()) |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 62 | { |
| 63 | } |
| 64 | CLLogicalAnd::CLLogicalAnd(CLLogicalAnd &&) = default; |
| 65 | CLLogicalAnd &CLLogicalAnd::operator=(CLLogicalAnd &&) = default; |
| 66 | CLLogicalAnd::~CLLogicalAnd() = default; |
| 67 | |
| 68 | void CLLogicalAnd::configure(ICLTensor *input1, ICLTensor *input2, ICLTensor *output) |
| 69 | { |
| 70 | configure(CLKernelLibrary::get().get_compile_context(), input1, input2, output); |
| 71 | } |
| 72 | |
| 73 | void CLLogicalAnd::configure(const CLCompileContext &compile_context, ICLTensor *input1, ICLTensor *input2, ICLTensor *output) |
| 74 | { |
| 75 | _impl->src0 = input1; |
| 76 | _impl->src1 = input2; |
| 77 | _impl->dst = output; |
Georgios Pinitas | 40f51a6 | 2020-11-21 03:04:18 +0000 | [diff] [blame] | 78 | _impl->op = std::make_unique<experimental::CLLogicalAnd>(); |
Sang-Hoon Park | 75eea33 | 2020-11-13 13:44:13 +0000 | [diff] [blame] | 79 | _impl->op->configure(compile_context, input1->info(), input2->info(), output->info()); |
| 80 | } |
| 81 | |
| 82 | Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) |
| 83 | { |
| 84 | return experimental::CLLogicalAnd::validate(input1, input2, output); |
| 85 | } |
| 86 | |
| 87 | void CLLogicalAnd::run() |
| 88 | { |
| 89 | ITensorPack pack; |
| 90 | pack.add_tensor(TensorType::ACL_SRC_0, _impl->src0); |
| 91 | pack.add_tensor(TensorType::ACL_SRC_1, _impl->src1); |
| 92 | pack.add_tensor(TensorType::ACL_DST, _impl->dst); |
| 93 | |
| 94 | _impl->op->run(pack); |
| 95 | } |
| 96 | } // namespace arm_compute |