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review.mlplatform.org / ml / ComputeLibrary / 6e4334962913a4b4d88d3d2b9d76ef2b7850a56c / . / tests / framework / instruments / hwc_names.hpp
blob: 181af7fe59791f38512248fb01b38f280e43c493 [file] [log] [blame]
Moritz Pflanzer45634b42017-08-30 12:48:18 +0100[diff] [blame]1/*
2 * Copyright (c) 2017 ARM Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24#ifndef ARM_COMPUTE_TEST_HWC_NAMES
25#define ARM_COMPUTE_TEST_HWC_NAMES
26
27namespace mali_userspace
28{
29 enum MaliCounterBlockName {
30 MALI_NAME_BLOCK_JM = 0,
31 MALI_NAME_BLOCK_TILER = 1,
32 MALI_NAME_BLOCK_SHADER = 2,
33 MALI_NAME_BLOCK_MMU = 3
34 };
35
36 enum { MALI_NAME_BLOCK_SIZE = 64 };
37
38 /*
39 * "Short names" for hardware counters used by Streamline. Counters names are
40 * stored in accordance with their memory layout in the binary counter block
41 * emitted by the Mali GPU. Each "master" in the GPU emits a fixed-size block
42 * of 64 counters, and each GPU implements the same set of "masters" although
43 * the counters each master exposes within its block of 64 may vary.
44 *
45 * Counters which are an empty string are simply "holes" in the counter memory
46 * where no counter exists.
47 */
48
49 static const char * const hardware_counters_mali_t60x[] = {
50 /* Job Manager */
51 "",
52 "",
53 "",
54 "",
55 "T60x_MESSAGES_SENT",
56 "T60x_MESSAGES_RECEIVED",
57 "T60x_GPU_ACTIVE",
58 "T60x_IRQ_ACTIVE",
59 "T60x_JS0_JOBS",
60 "T60x_JS0_TASKS",
61 "T60x_JS0_ACTIVE",
62 "",
63 "T60x_JS0_WAIT_READ",
64 "T60x_JS0_WAIT_ISSUE",
65 "T60x_JS0_WAIT_DEPEND",
66 "T60x_JS0_WAIT_FINISH",
67 "T60x_JS1_JOBS",
68 "T60x_JS1_TASKS",
69 "T60x_JS1_ACTIVE",
70 "",
71 "T60x_JS1_WAIT_READ",
72 "T60x_JS1_WAIT_ISSUE",
73 "T60x_JS1_WAIT_DEPEND",
74 "T60x_JS1_WAIT_FINISH",
75 "T60x_JS2_JOBS",
76 "T60x_JS2_TASKS",
77 "T60x_JS2_ACTIVE",
78 "",
79 "T60x_JS2_WAIT_READ",
80 "T60x_JS2_WAIT_ISSUE",
81 "T60x_JS2_WAIT_DEPEND",
82 "T60x_JS2_WAIT_FINISH",
83 "",
84 "",
85 "",
86 "",
87 "",
88 "",
89 "",
90 "",
91 "",
92 "",
93 "",
94 "",
95 "",
96 "",
97 "",
98 "",
99 "",
100 "",
101 "",
102 "",
103 "",
104 "",
105 "",
106 "",
107 "",
108 "",
109 "",
110 "",
111 "",
112 "",
113 "",
114 "",
115
116 /*Tiler */
117 "",
118 "",
119 "",
120 "T60x_TI_JOBS_PROCESSED",
121 "T60x_TI_TRIANGLES",
122 "T60x_TI_QUADS",
123 "T60x_TI_POLYGONS",
124 "T60x_TI_POINTS",
125 "T60x_TI_LINES",
126 "T60x_TI_VCACHE_HIT",
127 "T60x_TI_VCACHE_MISS",
128 "T60x_TI_FRONT_FACING",
129 "T60x_TI_BACK_FACING",
130 "T60x_TI_PRIM_VISIBLE",
131 "T60x_TI_PRIM_CULLED",
132 "T60x_TI_PRIM_CLIPPED",
133 "T60x_TI_LEVEL0",
134 "T60x_TI_LEVEL1",
135 "T60x_TI_LEVEL2",
136 "T60x_TI_LEVEL3",
137 "T60x_TI_LEVEL4",
138 "T60x_TI_LEVEL5",
139 "T60x_TI_LEVEL6",
140 "T60x_TI_LEVEL7",
141 "T60x_TI_COMMAND_1",
142 "T60x_TI_COMMAND_2",
143 "T60x_TI_COMMAND_3",
144 "T60x_TI_COMMAND_4",
145 "T60x_TI_COMMAND_4_7",
146 "T60x_TI_COMMAND_8_15",
147 "T60x_TI_COMMAND_16_63",
148 "T60x_TI_COMMAND_64",
149 "T60x_TI_COMPRESS_IN",
150 "T60x_TI_COMPRESS_OUT",
151 "T60x_TI_COMPRESS_FLUSH",
152 "T60x_TI_TIMESTAMPS",
153 "T60x_TI_PCACHE_HIT",
154 "T60x_TI_PCACHE_MISS",
155 "T60x_TI_PCACHE_LINE",
156 "T60x_TI_PCACHE_STALL",
157 "T60x_TI_WRBUF_HIT",
158 "T60x_TI_WRBUF_MISS",
159 "T60x_TI_WRBUF_LINE",
160 "T60x_TI_WRBUF_PARTIAL",
161 "T60x_TI_WRBUF_STALL",
162 "T60x_TI_ACTIVE",
163 "T60x_TI_LOADING_DESC",
164 "T60x_TI_INDEX_WAIT",
165 "T60x_TI_INDEX_RANGE_WAIT",
166 "T60x_TI_VERTEX_WAIT",
167 "T60x_TI_PCACHE_WAIT",
168 "T60x_TI_WRBUF_WAIT",
169 "T60x_TI_BUS_READ",
170 "T60x_TI_BUS_WRITE",
171 "",
172 "",
173 "",
174 "",
175 "",
176 "T60x_TI_UTLB_STALL",
177 "T60x_TI_UTLB_REPLAY_MISS",
178 "T60x_TI_UTLB_REPLAY_FULL",
179 "T60x_TI_UTLB_NEW_MISS",
180 "T60x_TI_UTLB_HIT",
181
182 /* Shader Core */
183 "",
184 "",
185 "",
186 "",
187 "T60x_FRAG_ACTIVE",
188 "T60x_FRAG_PRIMITIVES",
189 "T60x_FRAG_PRIMITIVES_DROPPED",
190 "T60x_FRAG_CYCLES_DESC",
191 "T60x_FRAG_CYCLES_PLR",
192 "T60x_FRAG_CYCLES_VERT",
193 "T60x_FRAG_CYCLES_TRISETUP",
194 "T60x_FRAG_CYCLES_RAST",
195 "T60x_FRAG_THREADS",
196 "T60x_FRAG_DUMMY_THREADS",
197 "T60x_FRAG_QUADS_RAST",
198 "T60x_FRAG_QUADS_EZS_TEST",
199 "T60x_FRAG_QUADS_EZS_KILLED",
200 "T60x_FRAG_THREADS_LZS_TEST",
201 "T60x_FRAG_THREADS_LZS_KILLED",
202 "T60x_FRAG_CYCLES_NO_TILE",
203 "T60x_FRAG_NUM_TILES",
204 "T60x_FRAG_TRANS_ELIM",
205 "T60x_COMPUTE_ACTIVE",
206 "T60x_COMPUTE_TASKS",
207 "T60x_COMPUTE_THREADS",
208 "T60x_COMPUTE_CYCLES_DESC",
209 "T60x_TRIPIPE_ACTIVE",
210 "T60x_ARITH_WORDS",
211 "T60x_ARITH_CYCLES_REG",
212 "T60x_ARITH_CYCLES_L0",
213 "T60x_ARITH_FRAG_DEPEND",
214 "T60x_LS_WORDS",
215 "T60x_LS_ISSUES",
216 "T60x_LS_RESTARTS",
217 "T60x_LS_REISSUES_MISS",
218 "T60x_LS_REISSUES_VD",
219 "T60x_LS_REISSUE_ATTRIB_MISS",
220 "T60x_LS_NO_WB",
221 "T60x_TEX_WORDS",
222 "T60x_TEX_BUBBLES",
223 "T60x_TEX_WORDS_L0",
224 "T60x_TEX_WORDS_DESC",
225 "T60x_TEX_ISSUES",
226 "T60x_TEX_RECIRC_FMISS",
227 "T60x_TEX_RECIRC_DESC",
228 "T60x_TEX_RECIRC_MULTI",
229 "T60x_TEX_RECIRC_PMISS",
230 "T60x_TEX_RECIRC_CONF",
231 "T60x_LSC_READ_HITS",
232 "T60x_LSC_READ_MISSES",
233 "T60x_LSC_WRITE_HITS",
234 "T60x_LSC_WRITE_MISSES",
235 "T60x_LSC_ATOMIC_HITS",
236 "T60x_LSC_ATOMIC_MISSES",
237 "T60x_LSC_LINE_FETCHES",
238 "T60x_LSC_DIRTY_LINE",
239 "T60x_LSC_SNOOPS",
240 "T60x_AXI_TLB_STALL",
241 "T60x_AXI_TLB_MISS",
242 "T60x_AXI_TLB_TRANSACTION",
243 "T60x_LS_TLB_MISS",
244 "T60x_LS_TLB_HIT",
245 "T60x_AXI_BEATS_READ",
246 "T60x_AXI_BEATS_WRITTEN",
247
248 /*L2 and MMU */
249 "",
250 "",
251 "",
252 "",
253 "T60x_MMU_HIT",
254 "T60x_MMU_NEW_MISS",
255 "T60x_MMU_REPLAY_FULL",
256 "T60x_MMU_REPLAY_MISS",
257 "T60x_MMU_TABLE_WALK",
258 "",
259 "",
260 "",
261 "",
262 "",
263 "",
264 "",
265 "T60x_UTLB_HIT",
266 "T60x_UTLB_NEW_MISS",
267 "T60x_UTLB_REPLAY_FULL",
268 "T60x_UTLB_REPLAY_MISS",
269 "T60x_UTLB_STALL",
270 "",
271 "",
272 "",
273 "",
274 "",
275 "",
276 "",
277 "",
278 "",
279 "T60x_L2_EXT_WRITE_BEATS",
280 "T60x_L2_EXT_READ_BEATS",
281 "T60x_L2_ANY_LOOKUP",
282 "T60x_L2_READ_LOOKUP",
283 "T60x_L2_SREAD_LOOKUP",
284 "T60x_L2_READ_REPLAY",
285 "T60x_L2_READ_SNOOP",
286 "T60x_L2_READ_HIT",
287 "T60x_L2_CLEAN_MISS",
288 "T60x_L2_WRITE_LOOKUP",
289 "T60x_L2_SWRITE_LOOKUP",
290 "T60x_L2_WRITE_REPLAY",
291 "T60x_L2_WRITE_SNOOP",
292 "T60x_L2_WRITE_HIT",
293 "T60x_L2_EXT_READ_FULL",
294 "T60x_L2_EXT_READ_HALF",
295 "T60x_L2_EXT_WRITE_FULL",
296 "T60x_L2_EXT_WRITE_HALF",
297 "T60x_L2_EXT_READ",
298 "T60x_L2_EXT_READ_LINE",
299 "T60x_L2_EXT_WRITE",
300 "T60x_L2_EXT_WRITE_LINE",
301 "T60x_L2_EXT_WRITE_SMALL",
302 "T60x_L2_EXT_BARRIER",
303 "T60x_L2_EXT_AR_STALL",
304 "T60x_L2_EXT_R_BUF_FULL",
305 "T60x_L2_EXT_RD_BUF_FULL",
306 "T60x_L2_EXT_R_RAW",
307 "T60x_L2_EXT_W_STALL",
308 "T60x_L2_EXT_W_BUF_FULL",
309 "T60x_L2_EXT_R_W_HAZARD",
310 "T60x_L2_TAG_HAZARD",
311 "T60x_L2_SNOOP_FULL",
312 "T60x_L2_REPLAY_FULL"
313 };
314 static const char * const hardware_counters_mali_t62x[] = {
315 /* Job Manager */
316 "",
317 "",
318 "",
319 "",
320 "T62x_MESSAGES_SENT",
321 "T62x_MESSAGES_RECEIVED",
322 "T62x_GPU_ACTIVE",
323 "T62x_IRQ_ACTIVE",
324 "T62x_JS0_JOBS",
325 "T62x_JS0_TASKS",
326 "T62x_JS0_ACTIVE",
327 "",
328 "T62x_JS0_WAIT_READ",
329 "T62x_JS0_WAIT_ISSUE",
330 "T62x_JS0_WAIT_DEPEND",
331 "T62x_JS0_WAIT_FINISH",
332 "T62x_JS1_JOBS",
333 "T62x_JS1_TASKS",
334 "T62x_JS1_ACTIVE",
335 "",
336 "T62x_JS1_WAIT_READ",
337 "T62x_JS1_WAIT_ISSUE",
338 "T62x_JS1_WAIT_DEPEND",
339 "T62x_JS1_WAIT_FINISH",
340 "T62x_JS2_JOBS",
341 "T62x_JS2_TASKS",
342 "T62x_JS2_ACTIVE",
343 "",
344 "T62x_JS2_WAIT_READ",
345 "T62x_JS2_WAIT_ISSUE",
346 "T62x_JS2_WAIT_DEPEND",
347 "T62x_JS2_WAIT_FINISH",
348 "",
349 "",
350 "",
351 "",
352 "",
353 "",
354 "",
355 "",
356 "",
357 "",
358 "",
359 "",
360 "",
361 "",
362 "",
363 "",
364 "",
365 "",
366 "",
367 "",
368 "",
369 "",
370 "",
371 "",
372 "",
373 "",
374 "",
375 "",
376 "",
377 "",
378 "",
379 "",
380
381 /*Tiler */
382 "",
383 "",
384 "",
385 "T62x_TI_JOBS_PROCESSED",
386 "T62x_TI_TRIANGLES",
387 "T62x_TI_QUADS",
388 "T62x_TI_POLYGONS",
389 "T62x_TI_POINTS",
390 "T62x_TI_LINES",
391 "T62x_TI_VCACHE_HIT",
392 "T62x_TI_VCACHE_MISS",
393 "T62x_TI_FRONT_FACING",
394 "T62x_TI_BACK_FACING",
395 "T62x_TI_PRIM_VISIBLE",
396 "T62x_TI_PRIM_CULLED",
397 "T62x_TI_PRIM_CLIPPED",
398 "T62x_TI_LEVEL0",
399 "T62x_TI_LEVEL1",
400 "T62x_TI_LEVEL2",
401 "T62x_TI_LEVEL3",
402 "T62x_TI_LEVEL4",
403 "T62x_TI_LEVEL5",
404 "T62x_TI_LEVEL6",
405 "T62x_TI_LEVEL7",
406 "T62x_TI_COMMAND_1",
407 "T62x_TI_COMMAND_2",
408 "T62x_TI_COMMAND_3",
409 "T62x_TI_COMMAND_4",
410 "T62x_TI_COMMAND_5_7",
411 "T62x_TI_COMMAND_8_15",
412 "T62x_TI_COMMAND_16_63",
413 "T62x_TI_COMMAND_64",
414 "T62x_TI_COMPRESS_IN",
415 "T62x_TI_COMPRESS_OUT",
416 "T62x_TI_COMPRESS_FLUSH",
417 "T62x_TI_TIMESTAMPS",
418 "T62x_TI_PCACHE_HIT",
419 "T62x_TI_PCACHE_MISS",
420 "T62x_TI_PCACHE_LINE",
421 "T62x_TI_PCACHE_STALL",
422 "T62x_TI_WRBUF_HIT",
423 "T62x_TI_WRBUF_MISS",
424 "T62x_TI_WRBUF_LINE",
425 "T62x_TI_WRBUF_PARTIAL",
426 "T62x_TI_WRBUF_STALL",
427 "T62x_TI_ACTIVE",
428 "T62x_TI_LOADING_DESC",
429 "T62x_TI_INDEX_WAIT",
430 "T62x_TI_INDEX_RANGE_WAIT",
431 "T62x_TI_VERTEX_WAIT",
432 "T62x_TI_PCACHE_WAIT",
433 "T62x_TI_WRBUF_WAIT",
434 "T62x_TI_BUS_READ",
435 "T62x_TI_BUS_WRITE",
436 "",
437 "",
438 "",
439 "",
440 "",
441 "T62x_TI_UTLB_STALL",
442 "T62x_TI_UTLB_REPLAY_MISS",
443 "T62x_TI_UTLB_REPLAY_FULL",
444 "T62x_TI_UTLB_NEW_MISS",
445 "T62x_TI_UTLB_HIT",
446
447 /* Shader Core */
448 "",
449 "",
450 "",
451 "T62x_SHADER_CORE_ACTIVE",
452 "T62x_FRAG_ACTIVE",
453 "T62x_FRAG_PRIMITIVES",
454 "T62x_FRAG_PRIMITIVES_DROPPED",
455 "T62x_FRAG_CYCLES_DESC",
456 "T62x_FRAG_CYCLES_FPKQ_ACTIVE",
457 "T62x_FRAG_CYCLES_VERT",
458 "T62x_FRAG_CYCLES_TRISETUP",
459 "T62x_FRAG_CYCLES_EZS_ACTIVE",
460 "T62x_FRAG_THREADS",
461 "T62x_FRAG_DUMMY_THREADS",
462 "T62x_FRAG_QUADS_RAST",
463 "T62x_FRAG_QUADS_EZS_TEST",
464 "T62x_FRAG_QUADS_EZS_KILLED",
465 "T62x_FRAG_THREADS_LZS_TEST",
466 "T62x_FRAG_THREADS_LZS_KILLED",
467 "T62x_FRAG_CYCLES_NO_TILE",
468 "T62x_FRAG_NUM_TILES",
469 "T62x_FRAG_TRANS_ELIM",
470 "T62x_COMPUTE_ACTIVE",
471 "T62x_COMPUTE_TASKS",
472 "T62x_COMPUTE_THREADS",
473 "T62x_COMPUTE_CYCLES_DESC",
474 "T62x_TRIPIPE_ACTIVE",
475 "T62x_ARITH_WORDS",
476 "T62x_ARITH_CYCLES_REG",
477 "T62x_ARITH_CYCLES_L0",
478 "T62x_ARITH_FRAG_DEPEND",
479 "T62x_LS_WORDS",
480 "T62x_LS_ISSUES",
481 "T62x_LS_RESTARTS",
482 "T62x_LS_REISSUES_MISS",
483 "T62x_LS_REISSUES_VD",
484 "T62x_LS_REISSUE_ATTRIB_MISS",
485 "T62x_LS_NO_WB",
486 "T62x_TEX_WORDS",
487 "T62x_TEX_BUBBLES",
488 "T62x_TEX_WORDS_L0",
489 "T62x_TEX_WORDS_DESC",
490 "T62x_TEX_ISSUES",
491 "T62x_TEX_RECIRC_FMISS",
492 "T62x_TEX_RECIRC_DESC",
493 "T62x_TEX_RECIRC_MULTI",
494 "T62x_TEX_RECIRC_PMISS",
495 "T62x_TEX_RECIRC_CONF",
496 "T62x_LSC_READ_HITS",
497 "T62x_LSC_READ_MISSES",
498 "T62x_LSC_WRITE_HITS",
499 "T62x_LSC_WRITE_MISSES",
500 "T62x_LSC_ATOMIC_HITS",
501 "T62x_LSC_ATOMIC_MISSES",
502 "T62x_LSC_LINE_FETCHES",
503 "T62x_LSC_DIRTY_LINE",
504 "T62x_LSC_SNOOPS",
505 "T62x_AXI_TLB_STALL",
506 "T62x_AXI_TLB_MISS",
507 "T62x_AXI_TLB_TRANSACTION",
508 "T62x_LS_TLB_MISS",
509 "T62x_LS_TLB_HIT",
510 "T62x_AXI_BEATS_READ",
511 "T62x_AXI_BEATS_WRITTEN",
512
513 /*L2 and MMU */
514 "",
515 "",
516 "",
517 "",
518 "T62x_MMU_HIT",
519 "T62x_MMU_NEW_MISS",
520 "T62x_MMU_REPLAY_FULL",
521 "T62x_MMU_REPLAY_MISS",
522 "T62x_MMU_TABLE_WALK",
523 "",
524 "",
525 "",
526 "",
527 "",
528 "",
529 "",
530 "T62x_UTLB_HIT",
531 "T62x_UTLB_NEW_MISS",
532 "T62x_UTLB_REPLAY_FULL",
533 "T62x_UTLB_REPLAY_MISS",
534 "T62x_UTLB_STALL",
535 "",
536 "",
537 "",
538 "",
539 "",
540 "",
541 "",
542 "",
543 "",
544 "T62x_L2_EXT_WRITE_BEATS",
545 "T62x_L2_EXT_READ_BEATS",
546 "T62x_L2_ANY_LOOKUP",
547 "T62x_L2_READ_LOOKUP",
548 "T62x_L2_SREAD_LOOKUP",
549 "T62x_L2_READ_REPLAY",
550 "T62x_L2_READ_SNOOP",
551 "T62x_L2_READ_HIT",
552 "T62x_L2_CLEAN_MISS",
553 "T62x_L2_WRITE_LOOKUP",
554 "T62x_L2_SWRITE_LOOKUP",
555 "T62x_L2_WRITE_REPLAY",
556 "T62x_L2_WRITE_SNOOP",
557 "T62x_L2_WRITE_HIT",
558 "T62x_L2_EXT_READ_FULL",
559 "T62x_L2_EXT_READ_HALF",
560 "T62x_L2_EXT_WRITE_FULL",
561 "T62x_L2_EXT_WRITE_HALF",
562 "T62x_L2_EXT_READ",
563 "T62x_L2_EXT_READ_LINE",
564 "T62x_L2_EXT_WRITE",
565 "T62x_L2_EXT_WRITE_LINE",
566 "T62x_L2_EXT_WRITE_SMALL",
567 "T62x_L2_EXT_BARRIER",
568 "T62x_L2_EXT_AR_STALL",
569 "T62x_L2_EXT_R_BUF_FULL",
570 "T62x_L2_EXT_RD_BUF_FULL",
571 "T62x_L2_EXT_R_RAW",
572 "T62x_L2_EXT_W_STALL",
573 "T62x_L2_EXT_W_BUF_FULL",
574 "T62x_L2_EXT_R_W_HAZARD",
575 "T62x_L2_TAG_HAZARD",
576 "T62x_L2_SNOOP_FULL",
577 "T62x_L2_REPLAY_FULL"
578 };
579
580 static const char * const hardware_counters_mali_t72x[] = {
581 /* Job Manager */
582 "",
583 "",
584 "",
585 "",
586 "T72x_GPU_ACTIVE",
587 "T72x_IRQ_ACTIVE",
588 "T72x_JS0_JOBS",
589 "T72x_JS0_TASKS",
590 "T72x_JS0_ACTIVE",
591 "T72x_JS1_JOBS",
592 "T72x_JS1_TASKS",
593 "T72x_JS1_ACTIVE",
594 "T72x_JS2_JOBS",
595 "T72x_JS2_TASKS",
596 "T72x_JS2_ACTIVE",
597 "",
598 "",
599 "",
600 "",
601 "",
602 "",
603 "",
604 "",
605 "",
606 "",
607 "",
608 "",
609 "",
610 "",
611 "",
612 "",
613 "",
614 "",
615 "",
616 "",
617 "",
618 "",
619 "",
620 "",
621 "",
622 "",
623 "",
624 "",
625 "",
626 "",
627 "",
628 "",
629 "",
630 "",
631 "",
632 "",
633 "",
634 "",
635 "",
636 "",
637 "",
638 "",
639 "",
640 "",
641 "",
642 "",
643 "",
644 "",
645 "",
646
647 /*Tiler */
648 "",
649 "",
650 "",
651 "T72x_TI_JOBS_PROCESSED",
652 "T72x_TI_TRIANGLES",
653 "T72x_TI_QUADS",
654 "T72x_TI_POLYGONS",
655 "T72x_TI_POINTS",
656 "T72x_TI_LINES",
657 "T72x_TI_FRONT_FACING",
658 "T72x_TI_BACK_FACING",
659 "T72x_TI_PRIM_VISIBLE",
660 "T72x_TI_PRIM_CULLED",
661 "T72x_TI_PRIM_CLIPPED",
662 "",
663 "",
664 "",
665 "",
666 "",
667 "",
668 "",
669 "",
670 "T72x_TI_ACTIVE",
671 "",
672 "",
673 "",
674 "",
675 "",
676 "",
677 "",
678 "",
679 "",
680 "",
681 "",
682 "",
683 "",
684 "",
685 "",
686 "",
687 "",
688 "",
689 "",
690 "",
691 "",
692 "",
693 "",
694 "",
695 "",
696 "",
697 "",
698 "",
699 "",
700 "",
701 "",
702 "",
703 "",
704 "",
705 "",
706 "",
707 "",
708 "",
709 "",
710 "",
711 "",
712
713 /* Shader Core */
714 "",
715 "",
716 "",
717 "",
718 "T72x_FRAG_ACTIVE",
719 "T72x_FRAG_PRIMITIVES",
720 "T72x_FRAG_PRIMITIVES_DROPPED",
721 "T72x_FRAG_THREADS",
722 "T72x_FRAG_DUMMY_THREADS",
723 "T72x_FRAG_QUADS_RAST",
724 "T72x_FRAG_QUADS_EZS_TEST",
725 "T72x_FRAG_QUADS_EZS_KILLED",
726 "T72x_FRAG_THREADS_LZS_TEST",
727 "T72x_FRAG_THREADS_LZS_KILLED",
728 "T72x_FRAG_CYCLES_NO_TILE",
729 "T72x_FRAG_NUM_TILES",
730 "T72x_FRAG_TRANS_ELIM",
731 "T72x_COMPUTE_ACTIVE",
732 "T72x_COMPUTE_TASKS",
733 "T72x_COMPUTE_THREADS",
734 "T72x_TRIPIPE_ACTIVE",
735 "T72x_ARITH_WORDS",
736 "T72x_ARITH_CYCLES_REG",
737 "T72x_LS_WORDS",
738 "T72x_LS_ISSUES",
739 "T72x_LS_RESTARTS",
740 "T72x_LS_REISSUES_MISS",
741 "T72x_TEX_WORDS",
742 "T72x_TEX_BUBBLES",
743 "T72x_TEX_ISSUES",
744 "T72x_LSC_READ_HITS",
745 "T72x_LSC_READ_MISSES",
746 "T72x_LSC_WRITE_HITS",
747 "T72x_LSC_WRITE_MISSES",
748 "T72x_LSC_ATOMIC_HITS",
749 "T72x_LSC_ATOMIC_MISSES",
750 "T72x_LSC_LINE_FETCHES",
751 "T72x_LSC_DIRTY_LINE",
752 "T72x_LSC_SNOOPS",
753 "",
754 "",
755 "",
756 "",
757 "",
758 "",
759 "",
760 "",
761 "",
762 "",
763 "",
764 "",
765 "",
766 "",
767 "",
768 "",
769 "",
770 "",
771 "",
772 "",
773 "",
774 "",
775 "",
776 "",
777 "",
778
779 /*L2 and MMU */
780 "",
781 "",
782 "",
783 "",
784 "T72x_L2_EXT_WRITE_BEAT",
785 "T72x_L2_EXT_READ_BEAT",
786 "T72x_L2_READ_SNOOP",
787 "T72x_L2_READ_HIT",
788 "T72x_L2_WRITE_SNOOP",
789 "T72x_L2_WRITE_HIT",
790 "T72x_L2_EXT_WRITE_SMALL",
791 "T72x_L2_EXT_BARRIER",
792 "T72x_L2_EXT_AR_STALL",
793 "T72x_L2_EXT_W_STALL",
794 "T72x_L2_SNOOP_FULL",
795 "",
796 "",
797 "",
798 "",
799 "",
800 "",
801 "",
802 "",
803 "",
804 "",
805 "",
806 "",
807 "",
808 "",
809 "",
810 "",
811 "",
812 "",
813 "",
814 "",
815 "",
816 "",
817 "",
818 "",
819 "",
820 "",
821 "",
822 "",
823 "",
824 "",
825 "",
826 "",
827 "",
828 "",
829 "",
830 "",
831 "",
832 "",
833 "",
834 "",
835 "",
836 "",
837 "",
838 "",
839 "",
840 "",
841 "",
842 "",
843 ""
844 };
845
846 static const char * const hardware_counters_mali_t76x[] = {
847 /* Job Manager */
848 "",
849 "",
850 "",
851 "",
852 "T76x_MESSAGES_SENT",
853 "T76x_MESSAGES_RECEIVED",
854 "T76x_GPU_ACTIVE",
855 "T76x_IRQ_ACTIVE",
856 "T76x_JS0_JOBS",
857 "T76x_JS0_TASKS",
858 "T76x_JS0_ACTIVE",
859 "",
860 "T76x_JS0_WAIT_READ",
861 "T76x_JS0_WAIT_ISSUE",
862 "T76x_JS0_WAIT_DEPEND",
863 "T76x_JS0_WAIT_FINISH",
864 "T76x_JS1_JOBS",
865 "T76x_JS1_TASKS",
866 "T76x_JS1_ACTIVE",
867 "",
868 "T76x_JS1_WAIT_READ",
869 "T76x_JS1_WAIT_ISSUE",
870 "T76x_JS1_WAIT_DEPEND",
871 "T76x_JS1_WAIT_FINISH",
872 "T76x_JS2_JOBS",
873 "T76x_JS2_TASKS",
874 "T76x_JS2_ACTIVE",
875 "",
876 "T76x_JS2_WAIT_READ",
877 "T76x_JS2_WAIT_ISSUE",
878 "T76x_JS2_WAIT_DEPEND",
879 "T76x_JS2_WAIT_FINISH",
880 "",
881 "",
882 "",
883 "",
884 "",
885 "",
886 "",
887 "",
888 "",
889 "",
890 "",
891 "",
892 "",
893 "",
894 "",
895 "",
896 "",
897 "",
898 "",
899 "",
900 "",
901 "",
902 "",
903 "",
904 "",
905 "",
906 "",
907 "",
908 "",
909 "",
910 "",
911 "",
912
913 /*Tiler */
914 "",
915 "",
916 "",
917 "T76x_TI_JOBS_PROCESSED",
918 "T76x_TI_TRIANGLES",
919 "T76x_TI_QUADS",
920 "T76x_TI_POLYGONS",
921 "T76x_TI_POINTS",
922 "T76x_TI_LINES",
923 "T76x_TI_VCACHE_HIT",
924 "T76x_TI_VCACHE_MISS",
925 "T76x_TI_FRONT_FACING",
926 "T76x_TI_BACK_FACING",
927 "T76x_TI_PRIM_VISIBLE",
928 "T76x_TI_PRIM_CULLED",
929 "T76x_TI_PRIM_CLIPPED",
930 "T76x_TI_LEVEL0",
931 "T76x_TI_LEVEL1",
932 "T76x_TI_LEVEL2",
933 "T76x_TI_LEVEL3",
934 "T76x_TI_LEVEL4",
935 "T76x_TI_LEVEL5",
936 "T76x_TI_LEVEL6",
937 "T76x_TI_LEVEL7",
938 "T76x_TI_COMMAND_1",
939 "T76x_TI_COMMAND_2",
940 "T76x_TI_COMMAND_3",
941 "T76x_TI_COMMAND_4",
942 "T76x_TI_COMMAND_5_7",
943 "T76x_TI_COMMAND_8_15",
944 "T76x_TI_COMMAND_16_63",
945 "T76x_TI_COMMAND_64",
946 "T76x_TI_COMPRESS_IN",
947 "T76x_TI_COMPRESS_OUT",
948 "T76x_TI_COMPRESS_FLUSH",
949 "T76x_TI_TIMESTAMPS",
950 "T76x_TI_PCACHE_HIT",
951 "T76x_TI_PCACHE_MISS",
952 "T76x_TI_PCACHE_LINE",
953 "T76x_TI_PCACHE_STALL",
954 "T76x_TI_WRBUF_HIT",
955 "T76x_TI_WRBUF_MISS",
956 "T76x_TI_WRBUF_LINE",
957 "T76x_TI_WRBUF_PARTIAL",
958 "T76x_TI_WRBUF_STALL",
959 "T76x_TI_ACTIVE",
960 "T76x_TI_LOADING_DESC",
961 "T76x_TI_INDEX_WAIT",
962 "T76x_TI_INDEX_RANGE_WAIT",
963 "T76x_TI_VERTEX_WAIT",
964 "T76x_TI_PCACHE_WAIT",
965 "T76x_TI_WRBUF_WAIT",
966 "T76x_TI_BUS_READ",
967 "T76x_TI_BUS_WRITE",
968 "",
969 "",
970 "",
971 "",
972 "",
973 "T76x_TI_UTLB_HIT",
974 "T76x_TI_UTLB_NEW_MISS",
975 "T76x_TI_UTLB_REPLAY_FULL",
976 "T76x_TI_UTLB_REPLAY_MISS",
977 "T76x_TI_UTLB_STALL",
978
979 /* Shader Core */
980 "",
981 "",
982 "",
983 "",
984 "T76x_FRAG_ACTIVE",
985 "T76x_FRAG_PRIMITIVES",
986 "T76x_FRAG_PRIMITIVES_DROPPED",
987 "T76x_FRAG_CYCLES_DESC",
988 "T76x_FRAG_CYCLES_FPKQ_ACTIVE",
989 "T76x_FRAG_CYCLES_VERT",
990 "T76x_FRAG_CYCLES_TRISETUP",
991 "T76x_FRAG_CYCLES_EZS_ACTIVE",
992 "T76x_FRAG_THREADS",
993 "T76x_FRAG_DUMMY_THREADS",
994 "T76x_FRAG_QUADS_RAST",
995 "T76x_FRAG_QUADS_EZS_TEST",
996 "T76x_FRAG_QUADS_EZS_KILLED",
997 "T76x_FRAG_THREADS_LZS_TEST",
998 "T76x_FRAG_THREADS_LZS_KILLED",
999 "T76x_FRAG_CYCLES_NO_TILE",
1000 "T76x_FRAG_NUM_TILES",
1001 "T76x_FRAG_TRANS_ELIM",
1002 "T76x_COMPUTE_ACTIVE",
1003 "T76x_COMPUTE_TASKS",
1004 "T76x_COMPUTE_THREADS",
1005 "T76x_COMPUTE_CYCLES_DESC",
1006 "T76x_TRIPIPE_ACTIVE",
1007 "T76x_ARITH_WORDS",
1008 "T76x_ARITH_CYCLES_REG",
1009 "T76x_ARITH_CYCLES_L0",
1010 "T76x_ARITH_FRAG_DEPEND",
1011 "T76x_LS_WORDS",
1012 "T76x_LS_ISSUES",
1013 "T76x_LS_REISSUE_ATTR",
1014 "T76x_LS_REISSUES_VARY",
1015 "T76x_LS_VARY_RV_MISS",
1016 "T76x_LS_VARY_RV_HIT",
1017 "T76x_LS_NO_UNPARK",
1018 "T76x_TEX_WORDS",
1019 "T76x_TEX_BUBBLES",
1020 "T76x_TEX_WORDS_L0",
1021 "T76x_TEX_WORDS_DESC",
1022 "T76x_TEX_ISSUES",
1023 "T76x_TEX_RECIRC_FMISS",
1024 "T76x_TEX_RECIRC_DESC",
1025 "T76x_TEX_RECIRC_MULTI",
1026 "T76x_TEX_RECIRC_PMISS",
1027 "T76x_TEX_RECIRC_CONF",
1028 "T76x_LSC_READ_HITS",
1029 "T76x_LSC_READ_OP",
1030 "T76x_LSC_WRITE_HITS",
1031 "T76x_LSC_WRITE_OP",
1032 "T76x_LSC_ATOMIC_HITS",
1033 "T76x_LSC_ATOMIC_OP",
1034 "T76x_LSC_LINE_FETCHES",
1035 "T76x_LSC_DIRTY_LINE",
1036 "T76x_LSC_SNOOPS",
1037 "T76x_AXI_TLB_STALL",
1038 "T76x_AXI_TLB_MISS",
1039 "T76x_AXI_TLB_TRANSACTION",
1040 "T76x_LS_TLB_MISS",
1041 "T76x_LS_TLB_HIT",
1042 "T76x_AXI_BEATS_READ",
1043 "T76x_AXI_BEATS_WRITTEN",
1044
1045 /*L2 and MMU */
1046 "",
1047 "",
1048 "",
1049 "",
1050 "T76x_MMU_HIT",
1051 "T76x_MMU_NEW_MISS",
1052 "T76x_MMU_REPLAY_FULL",
1053 "T76x_MMU_REPLAY_MISS",
1054 "T76x_MMU_TABLE_WALK",
1055 "T76x_MMU_REQUESTS",
1056 "",
1057 "",
1058 "T76x_UTLB_HIT",
1059 "T76x_UTLB_NEW_MISS",
1060 "T76x_UTLB_REPLAY_FULL",
1061 "T76x_UTLB_REPLAY_MISS",
1062 "T76x_UTLB_STALL",
1063 "",
1064 "",
1065 "",
1066 "",
1067 "",
1068 "",
1069 "",
1070 "",
1071 "",
1072 "",
1073 "",
1074 "",
1075 "",
1076 "T76x_L2_EXT_WRITE_BEATS",
1077 "T76x_L2_EXT_READ_BEATS",
1078 "T76x_L2_ANY_LOOKUP",
1079 "T76x_L2_READ_LOOKUP",
1080 "T76x_L2_SREAD_LOOKUP",
1081 "T76x_L2_READ_REPLAY",
1082 "T76x_L2_READ_SNOOP",
1083 "T76x_L2_READ_HIT",
1084 "T76x_L2_CLEAN_MISS",
1085 "T76x_L2_WRITE_LOOKUP",
1086 "T76x_L2_SWRITE_LOOKUP",
1087 "T76x_L2_WRITE_REPLAY",
1088 "T76x_L2_WRITE_SNOOP",
1089 "T76x_L2_WRITE_HIT",
1090 "T76x_L2_EXT_READ_FULL",
1091 "",
1092 "T76x_L2_EXT_WRITE_FULL",
1093 "T76x_L2_EXT_R_W_HAZARD",
1094 "T76x_L2_EXT_READ",
1095 "T76x_L2_EXT_READ_LINE",
1096 "T76x_L2_EXT_WRITE",
1097 "T76x_L2_EXT_WRITE_LINE",
1098 "T76x_L2_EXT_WRITE_SMALL",
1099 "T76x_L2_EXT_BARRIER",
1100 "T76x_L2_EXT_AR_STALL",
1101 "T76x_L2_EXT_R_BUF_FULL",
1102 "T76x_L2_EXT_RD_BUF_FULL",
1103 "T76x_L2_EXT_R_RAW",
1104 "T76x_L2_EXT_W_STALL",
1105 "T76x_L2_EXT_W_BUF_FULL",
1106 "T76x_L2_EXT_R_BUF_FULL",
1107 "T76x_L2_TAG_HAZARD",
1108 "T76x_L2_SNOOP_FULL",
1109 "T76x_L2_REPLAY_FULL"
1110 };
1111
1112 static const char * const hardware_counters_mali_t82x[] = {
1113 /* Job Manager */
1114 "",
1115 "",
1116 "",
1117 "",
1118 "T82x_MESSAGES_SENT",
1119 "T82x_MESSAGES_RECEIVED",
1120 "T82x_GPU_ACTIVE",
1121 "T82x_IRQ_ACTIVE",
1122 "T82x_JS0_JOBS",
1123 "T82x_JS0_TASKS",
1124 "T82x_JS0_ACTIVE",
1125 "",
1126 "T82x_JS0_WAIT_READ",
1127 "T82x_JS0_WAIT_ISSUE",
1128 "T82x_JS0_WAIT_DEPEND",
1129 "T82x_JS0_WAIT_FINISH",
1130 "T82x_JS1_JOBS",
1131 "T82x_JS1_TASKS",
1132 "T82x_JS1_ACTIVE",
1133 "",
1134 "T82x_JS1_WAIT_READ",
1135 "T82x_JS1_WAIT_ISSUE",
1136 "T82x_JS1_WAIT_DEPEND",
1137 "T82x_JS1_WAIT_FINISH",
1138 "T82x_JS2_JOBS",
1139 "T82x_JS2_TASKS",
1140 "T82x_JS2_ACTIVE",
1141 "",
1142 "T82x_JS2_WAIT_READ",
1143 "T82x_JS2_WAIT_ISSUE",
1144 "T82x_JS2_WAIT_DEPEND",
1145 "T82x_JS2_WAIT_FINISH",
1146 "",
1147 "",
1148 "",
1149 "",
1150 "",
1151 "",
1152 "",
1153 "",
1154 "",
1155 "",
1156 "",
1157 "",
1158 "",
1159 "",
1160 "",
1161 "",
1162 "",
1163 "",
1164 "",
1165 "",
1166 "",
1167 "",
1168 "",
1169 "",
1170 "",
1171 "",
1172 "",
1173 "",
1174 "",
1175 "",
1176 "",
1177 "",
1178
1179 /*Tiler */
1180 "",
1181 "",
1182 "",
1183 "T82x_TI_JOBS_PROCESSED",
1184 "T82x_TI_TRIANGLES",
1185 "T82x_TI_QUADS",
1186 "T82x_TI_POLYGONS",
1187 "T82x_TI_POINTS",
1188 "T82x_TI_LINES",
1189 "T82x_TI_FRONT_FACING",
1190 "T82x_TI_BACK_FACING",
1191 "T82x_TI_PRIM_VISIBLE",
1192 "T82x_TI_PRIM_CULLED",
1193 "T82x_TI_PRIM_CLIPPED",
1194 "",
1195 "",
1196 "",
1197 "",
1198 "",
1199 "",
1200 "",
1201 "",
1202 "T82x_TI_ACTIVE",
1203 "",
1204 "",
1205 "",
1206 "",
1207 "",
1208 "",
1209 "",
1210 "",
1211 "",
1212 "",
1213 "",
1214 "",
1215 "",
1216 "",
1217 "",
1218 "",
1219 "",
1220 "",
1221 "",
1222 "",
1223 "",
1224 "",
1225 "",
1226 "",
1227 "",
1228 "",
1229 "",
1230 "",
1231 "",
1232 "",
1233 "",
1234 "",
1235 "",
1236 "",
1237 "",
1238 "",
1239 "",
1240 "",
1241 "",
1242 "",
1243 "",
1244
1245 /* Shader Core */
1246 "",
1247 "",
1248 "",
1249 "",
1250 "T82x_FRAG_ACTIVE",
1251 "T82x_FRAG_PRIMITIVES",
1252 "T82x_FRAG_PRIMITIVES_DROPPED",
1253 "T82x_FRAG_CYCLES_DESC",
1254 "T82x_FRAG_CYCLES_FPKQ_ACTIVE",
1255 "T82x_FRAG_CYCLES_VERT",
1256 "T82x_FRAG_CYCLES_TRISETUP",
1257 "T82x_FRAG_CYCLES_EZS_ACTIVE",
1258 "T82x_FRAG_THREADS",
1259 "T82x_FRAG_DUMMY_THREADS",
1260 "T82x_FRAG_QUADS_RAST",
1261 "T82x_FRAG_QUADS_EZS_TEST",
1262 "T82x_FRAG_QUADS_EZS_KILLED",
1263 "T82x_FRAG_THREADS_LZS_TEST",
1264 "T82x_FRAG_THREADS_LZS_KILLED",
1265 "T82x_FRAG_CYCLES_NO_TILE",
1266 "T82x_FRAG_NUM_TILES",
1267 "T82x_FRAG_TRANS_ELIM",
1268 "T82x_COMPUTE_ACTIVE",
1269 "T82x_COMPUTE_TASKS",
1270 "T82x_COMPUTE_THREADS",
1271 "T82x_COMPUTE_CYCLES_DESC",
1272 "T82x_TRIPIPE_ACTIVE",
1273 "T82x_ARITH_WORDS",
1274 "T82x_ARITH_CYCLES_REG",
1275 "T82x_ARITH_CYCLES_L0",
1276 "T82x_ARITH_FRAG_DEPEND",
1277 "T82x_LS_WORDS",
1278 "T82x_LS_ISSUES",
1279 "T82x_LS_REISSUE_ATTR",
1280 "T82x_LS_REISSUES_VARY",
1281 "T82x_LS_VARY_RV_MISS",
1282 "T82x_LS_VARY_RV_HIT",
1283 "T82x_LS_NO_UNPARK",
1284 "T82x_TEX_WORDS",
1285 "T82x_TEX_BUBBLES",
1286 "T82x_TEX_WORDS_L0",
1287 "T82x_TEX_WORDS_DESC",
1288 "T82x_TEX_ISSUES",
1289 "T82x_TEX_RECIRC_FMISS",
1290 "T82x_TEX_RECIRC_DESC",
1291 "T82x_TEX_RECIRC_MULTI",
1292 "T82x_TEX_RECIRC_PMISS",
1293 "T82x_TEX_RECIRC_CONF",
1294 "T82x_LSC_READ_HITS",
1295 "T82x_LSC_READ_OP",
1296 "T82x_LSC_WRITE_HITS",
1297 "T82x_LSC_WRITE_OP",
1298 "T82x_LSC_ATOMIC_HITS",
1299 "T82x_LSC_ATOMIC_OP",
1300 "T82x_LSC_LINE_FETCHES",
1301 "T82x_LSC_DIRTY_LINE",
1302 "T82x_LSC_SNOOPS",
1303 "T82x_AXI_TLB_STALL",
1304 "T82x_AXI_TLB_MISS",
1305 "T82x_AXI_TLB_TRANSACTION",
1306 "T82x_LS_TLB_MISS",
1307 "T82x_LS_TLB_HIT",
1308 "T82x_AXI_BEATS_READ",
1309 "T82x_AXI_BEATS_WRITTEN",
1310
1311 /*L2 and MMU */
1312 "",
1313 "",
1314 "",
1315 "",
1316 "T82x_MMU_HIT",
1317 "T82x_MMU_NEW_MISS",
1318 "T82x_MMU_REPLAY_FULL",
1319 "T82x_MMU_REPLAY_MISS",
1320 "T82x_MMU_TABLE_WALK",
1321 "T82x_MMU_REQUESTS",
1322 "",
1323 "",
1324 "T82x_UTLB_HIT",
1325 "T82x_UTLB_NEW_MISS",
1326 "T82x_UTLB_REPLAY_FULL",
1327 "T82x_UTLB_REPLAY_MISS",
1328 "T82x_UTLB_STALL",
1329 "",
1330 "",
1331 "",
1332 "",
1333 "",
1334 "",
1335 "",
1336 "",
1337 "",
1338 "",
1339 "",
1340 "",
1341 "",
1342 "T82x_L2_EXT_WRITE_BEATS",
1343 "T82x_L2_EXT_READ_BEATS",
1344 "T82x_L2_ANY_LOOKUP",
1345 "T82x_L2_READ_LOOKUP",
1346 "T82x_L2_SREAD_LOOKUP",
1347 "T82x_L2_READ_REPLAY",
1348 "T82x_L2_READ_SNOOP",
1349 "T82x_L2_READ_HIT",
1350 "T82x_L2_CLEAN_MISS",
1351 "T82x_L2_WRITE_LOOKUP",
1352 "T82x_L2_SWRITE_LOOKUP",
1353 "T82x_L2_WRITE_REPLAY",
1354 "T82x_L2_WRITE_SNOOP",
1355 "T82x_L2_WRITE_HIT",
1356 "T82x_L2_EXT_READ_FULL",
1357 "",
1358 "T82x_L2_EXT_WRITE_FULL",
1359 "T82x_L2_EXT_R_W_HAZARD",
1360 "T82x_L2_EXT_READ",
1361 "T82x_L2_EXT_READ_LINE",
1362 "T82x_L2_EXT_WRITE",
1363 "T82x_L2_EXT_WRITE_LINE",
1364 "T82x_L2_EXT_WRITE_SMALL",
1365 "T82x_L2_EXT_BARRIER",
1366 "T82x_L2_EXT_AR_STALL",
1367 "T82x_L2_EXT_R_BUF_FULL",
1368 "T82x_L2_EXT_RD_BUF_FULL",
1369 "T82x_L2_EXT_R_RAW",
1370 "T82x_L2_EXT_W_STALL",
1371 "T82x_L2_EXT_W_BUF_FULL",
1372 "T82x_L2_EXT_R_BUF_FULL",
1373 "T82x_L2_TAG_HAZARD",
1374 "T82x_L2_SNOOP_FULL",
1375 "T82x_L2_REPLAY_FULL"
1376 };
1377
1378 static const char * const hardware_counters_mali_t83x[] = {
1379 /* Job Manager */
1380 "",
1381 "",
1382 "",
1383 "",
1384 "T83x_MESSAGES_SENT",
1385 "T83x_MESSAGES_RECEIVED",
1386 "T83x_GPU_ACTIVE",
1387 "T83x_IRQ_ACTIVE",
1388 "T83x_JS0_JOBS",
1389 "T83x_JS0_TASKS",
1390 "T83x_JS0_ACTIVE",
1391 "",
1392 "T83x_JS0_WAIT_READ",
1393 "T83x_JS0_WAIT_ISSUE",
1394 "T83x_JS0_WAIT_DEPEND",
1395 "T83x_JS0_WAIT_FINISH",
1396 "T83x_JS1_JOBS",
1397 "T83x_JS1_TASKS",
1398 "T83x_JS1_ACTIVE",
1399 "",
1400 "T83x_JS1_WAIT_READ",
1401 "T83x_JS1_WAIT_ISSUE",
1402 "T83x_JS1_WAIT_DEPEND",
1403 "T83x_JS1_WAIT_FINISH",
1404 "T83x_JS2_JOBS",
1405 "T83x_JS2_TASKS",
1406 "T83x_JS2_ACTIVE",
1407 "",
1408 "T83x_JS2_WAIT_READ",
1409 "T83x_JS2_WAIT_ISSUE",
1410 "T83x_JS2_WAIT_DEPEND",
1411 "T83x_JS2_WAIT_FINISH",
1412 "",
1413 "",
1414 "",
1415 "",
1416 "",
1417 "",
1418 "",
1419 "",
1420 "",
1421 "",
1422 "",
1423 "",
1424 "",
1425 "",
1426 "",
1427 "",
1428 "",
1429 "",
1430 "",
1431 "",
1432 "",
1433 "",
1434 "",
1435 "",
1436 "",
1437 "",
1438 "",
1439 "",
1440 "",
1441 "",
1442 "",
1443 "",
1444
1445 /*Tiler */
1446 "",
1447 "",
1448 "",
1449 "T83x_TI_JOBS_PROCESSED",
1450 "T83x_TI_TRIANGLES",
1451 "T83x_TI_QUADS",
1452 "T83x_TI_POLYGONS",
1453 "T83x_TI_POINTS",
1454 "T83x_TI_LINES",
1455 "T83x_TI_FRONT_FACING",
1456 "T83x_TI_BACK_FACING",
1457 "T83x_TI_PRIM_VISIBLE",
1458 "T83x_TI_PRIM_CULLED",
1459 "T83x_TI_PRIM_CLIPPED",
1460 "",
1461 "",
1462 "",
1463 "",
1464 "",
1465 "",
1466 "",
1467 "",
1468 "T83x_TI_ACTIVE",
1469 "",
1470 "",
1471 "",
1472 "",
1473 "",
1474 "",
1475 "",
1476 "",
1477 "",
1478 "",
1479 "",
1480 "",
1481 "",
1482 "",
1483 "",
1484 "",
1485 "",
1486 "",
1487 "",
1488 "",
1489 "",
1490 "",
1491 "",
1492 "",
1493 "",
1494 "",
1495 "",
1496 "",
1497 "",
1498 "",
1499 "",
1500 "",
1501 "",
1502 "",
1503 "",
1504 "",
1505 "",
1506 "",
1507 "",
1508 "",
1509 "",
1510
1511 /* Shader Core */
1512 "",
1513 "",
1514 "",
1515 "",
1516 "T83x_FRAG_ACTIVE",
1517 "T83x_FRAG_PRIMITIVES",
1518 "T83x_FRAG_PRIMITIVES_DROPPED",
1519 "T83x_FRAG_CYCLES_DESC",
1520 "T83x_FRAG_CYCLES_FPKQ_ACTIVE",
1521 "T83x_FRAG_CYCLES_VERT",
1522 "T83x_FRAG_CYCLES_TRISETUP",
1523 "T83x_FRAG_CYCLES_EZS_ACTIVE",
1524 "T83x_FRAG_THREADS",
1525 "T83x_FRAG_DUMMY_THREADS",
1526 "T83x_FRAG_QUADS_RAST",
1527 "T83x_FRAG_QUADS_EZS_TEST",
1528 "T83x_FRAG_QUADS_EZS_KILLED",
1529 "T83x_FRAG_THREADS_LZS_TEST",
1530 "T83x_FRAG_THREADS_LZS_KILLED",
1531 "T83x_FRAG_CYCLES_NO_TILE",
1532 "T83x_FRAG_NUM_TILES",
1533 "T83x_FRAG_TRANS_ELIM",
1534 "T83x_COMPUTE_ACTIVE",
1535 "T83x_COMPUTE_TASKS",
1536 "T83x_COMPUTE_THREADS",
1537 "T83x_COMPUTE_CYCLES_DESC",
1538 "T83x_TRIPIPE_ACTIVE",
1539 "T83x_ARITH_WORDS",
1540 "T83x_ARITH_CYCLES_REG",
1541 "T83x_ARITH_CYCLES_L0",
1542 "T83x_ARITH_FRAG_DEPEND",
1543 "T83x_LS_WORDS",
1544 "T83x_LS_ISSUES",
1545 "T83x_LS_REISSUE_ATTR",
1546 "T83x_LS_REISSUES_VARY",
1547 "T83x_LS_VARY_RV_MISS",
1548 "T83x_LS_VARY_RV_HIT",
1549 "T83x_LS_NO_UNPARK",
1550 "T83x_TEX_WORDS",
1551 "T83x_TEX_BUBBLES",
1552 "T83x_TEX_WORDS_L0",
1553 "T83x_TEX_WORDS_DESC",
1554 "T83x_TEX_ISSUES",
1555 "T83x_TEX_RECIRC_FMISS",
1556 "T83x_TEX_RECIRC_DESC",
1557 "T83x_TEX_RECIRC_MULTI",
1558 "T83x_TEX_RECIRC_PMISS",
1559 "T83x_TEX_RECIRC_CONF",
1560 "T83x_LSC_READ_HITS",
1561 "T83x_LSC_READ_OP",
1562 "T83x_LSC_WRITE_HITS",
1563 "T83x_LSC_WRITE_OP",
1564 "T83x_LSC_ATOMIC_HITS",
1565 "T83x_LSC_ATOMIC_OP",
1566 "T83x_LSC_LINE_FETCHES",
1567 "T83x_LSC_DIRTY_LINE",
1568 "T83x_LSC_SNOOPS",
1569 "T83x_AXI_TLB_STALL",
1570 "T83x_AXI_TLB_MISS",
1571 "T83x_AXI_TLB_TRANSACTION",
1572 "T83x_LS_TLB_MISS",
1573 "T83x_LS_TLB_HIT",
1574 "T83x_AXI_BEATS_READ",
1575 "T83x_AXI_BEATS_WRITTEN",
1576
1577 /*L2 and MMU */
1578 "",
1579 "",
1580 "",
1581 "",
1582 "T83x_MMU_HIT",
1583 "T83x_MMU_NEW_MISS",
1584 "T83x_MMU_REPLAY_FULL",
1585 "T83x_MMU_REPLAY_MISS",
1586 "T83x_MMU_TABLE_WALK",
1587 "T83x_MMU_REQUESTS",
1588 "",
1589 "",
1590 "T83x_UTLB_HIT",
1591 "T83x_UTLB_NEW_MISS",
1592 "T83x_UTLB_REPLAY_FULL",
1593 "T83x_UTLB_REPLAY_MISS",
1594 "T83x_UTLB_STALL",
1595 "",
1596 "",
1597 "",
1598 "",
1599 "",
1600 "",
1601 "",
1602 "",
1603 "",
1604 "",
1605 "",
1606 "",
1607 "",
1608 "T83x_L2_EXT_WRITE_BEATS",
1609 "T83x_L2_EXT_READ_BEATS",
1610 "T83x_L2_ANY_LOOKUP",
1611 "T83x_L2_READ_LOOKUP",
1612 "T83x_L2_SREAD_LOOKUP",
1613 "T83x_L2_READ_REPLAY",
1614 "T83x_L2_READ_SNOOP",
1615 "T83x_L2_READ_HIT",
1616 "T83x_L2_CLEAN_MISS",
1617 "T83x_L2_WRITE_LOOKUP",
1618 "T83x_L2_SWRITE_LOOKUP",
1619 "T83x_L2_WRITE_REPLAY",
1620 "T83x_L2_WRITE_SNOOP",
1621 "T83x_L2_WRITE_HIT",
1622 "T83x_L2_EXT_READ_FULL",
1623 "",
1624 "T83x_L2_EXT_WRITE_FULL",
1625 "T83x_L2_EXT_R_W_HAZARD",
1626 "T83x_L2_EXT_READ",
1627 "T83x_L2_EXT_READ_LINE",
1628 "T83x_L2_EXT_WRITE",
1629 "T83x_L2_EXT_WRITE_LINE",
1630 "T83x_L2_EXT_WRITE_SMALL",
1631 "T83x_L2_EXT_BARRIER",
1632 "T83x_L2_EXT_AR_STALL",
1633 "T83x_L2_EXT_R_BUF_FULL",
1634 "T83x_L2_EXT_RD_BUF_FULL",
1635 "T83x_L2_EXT_R_RAW",
1636 "T83x_L2_EXT_W_STALL",
1637 "T83x_L2_EXT_W_BUF_FULL",
1638 "T83x_L2_EXT_R_BUF_FULL",
1639 "T83x_L2_TAG_HAZARD",
1640 "T83x_L2_SNOOP_FULL",
1641 "T83x_L2_REPLAY_FULL"
1642 };
1643
1644 static const char * const hardware_counters_mali_t86x[] = {
1645 /* Job Manager */
1646 "",
1647 "",
1648 "",
1649 "",
1650 "T86x_MESSAGES_SENT",
1651 "T86x_MESSAGES_RECEIVED",
1652 "T86x_GPU_ACTIVE",
1653 "T86x_IRQ_ACTIVE",
1654 "T86x_JS0_JOBS",
1655 "T86x_JS0_TASKS",
1656 "T86x_JS0_ACTIVE",
1657 "",
1658 "T86x_JS0_WAIT_READ",
1659 "T86x_JS0_WAIT_ISSUE",
1660 "T86x_JS0_WAIT_DEPEND",
1661 "T86x_JS0_WAIT_FINISH",
1662 "T86x_JS1_JOBS",
1663 "T86x_JS1_TASKS",
1664 "T86x_JS1_ACTIVE",
1665 "",
1666 "T86x_JS1_WAIT_READ",
1667 "T86x_JS1_WAIT_ISSUE",
1668 "T86x_JS1_WAIT_DEPEND",
1669 "T86x_JS1_WAIT_FINISH",
1670 "T86x_JS2_JOBS",
1671 "T86x_JS2_TASKS",
1672 "T86x_JS2_ACTIVE",
1673 "",
1674 "T86x_JS2_WAIT_READ",
1675 "T86x_JS2_WAIT_ISSUE",
1676 "T86x_JS2_WAIT_DEPEND",
1677 "T86x_JS2_WAIT_FINISH",
1678 "",
1679 "",
1680 "",
1681 "",
1682 "",
1683 "",
1684 "",
1685 "",
1686 "",
1687 "",
1688 "",
1689 "",
1690 "",
1691 "",
1692 "",
1693 "",
1694 "",
1695 "",
1696 "",
1697 "",
1698 "",
1699 "",
1700 "",
1701 "",
1702 "",
1703 "",
1704 "",
1705 "",
1706 "",
1707 "",
1708 "",
1709 "",
1710
1711 /*Tiler */
1712 "",
1713 "",
1714 "",
1715 "T86x_TI_JOBS_PROCESSED",
1716 "T86x_TI_TRIANGLES",
1717 "T86x_TI_QUADS",
1718 "T86x_TI_POLYGONS",
1719 "T86x_TI_POINTS",
1720 "T86x_TI_LINES",
1721 "T86x_TI_VCACHE_HIT",
1722 "T86x_TI_VCACHE_MISS",
1723 "T86x_TI_FRONT_FACING",
1724 "T86x_TI_BACK_FACING",
1725 "T86x_TI_PRIM_VISIBLE",
1726 "T86x_TI_PRIM_CULLED",
1727 "T86x_TI_PRIM_CLIPPED",
1728 "T86x_TI_LEVEL0",
1729 "T86x_TI_LEVEL1",
1730 "T86x_TI_LEVEL2",
1731 "T86x_TI_LEVEL3",
1732 "T86x_TI_LEVEL4",
1733 "T86x_TI_LEVEL5",
1734 "T86x_TI_LEVEL6",
1735 "T86x_TI_LEVEL7",
1736 "T86x_TI_COMMAND_1",
1737 "T86x_TI_COMMAND_2",
1738 "T86x_TI_COMMAND_3",
1739 "T86x_TI_COMMAND_4",
1740 "T86x_TI_COMMAND_5_7",
1741 "T86x_TI_COMMAND_8_15",
1742 "T86x_TI_COMMAND_16_63",
1743 "T86x_TI_COMMAND_64",
1744 "T86x_TI_COMPRESS_IN",
1745 "T86x_TI_COMPRESS_OUT",
1746 "T86x_TI_COMPRESS_FLUSH",
1747 "T86x_TI_TIMESTAMPS",
1748 "T86x_TI_PCACHE_HIT",
1749 "T86x_TI_PCACHE_MISS",
1750 "T86x_TI_PCACHE_LINE",
1751 "T86x_TI_PCACHE_STALL",
1752 "T86x_TI_WRBUF_HIT",
1753 "T86x_TI_WRBUF_MISS",
1754 "T86x_TI_WRBUF_LINE",
1755 "T86x_TI_WRBUF_PARTIAL",
1756 "T86x_TI_WRBUF_STALL",
1757 "T86x_TI_ACTIVE",
1758 "T86x_TI_LOADING_DESC",
1759 "T86x_TI_INDEX_WAIT",
1760 "T86x_TI_INDEX_RANGE_WAIT",
1761 "T86x_TI_VERTEX_WAIT",
1762 "T86x_TI_PCACHE_WAIT",
1763 "T86x_TI_WRBUF_WAIT",
1764 "T86x_TI_BUS_READ",
1765 "T86x_TI_BUS_WRITE",
1766 "",
1767 "",
1768 "",
1769 "",
1770 "",
1771 "T86x_TI_UTLB_HIT",
1772 "T86x_TI_UTLB_NEW_MISS",
1773 "T86x_TI_UTLB_REPLAY_FULL",
1774 "T86x_TI_UTLB_REPLAY_MISS",
1775 "T86x_TI_UTLB_STALL",
1776
1777 /* Shader Core */
1778 "",
1779 "",
1780 "",
1781 "",
1782 "T86x_FRAG_ACTIVE",
1783 "T86x_FRAG_PRIMITIVES",
1784 "T86x_FRAG_PRIMITIVES_DROPPED",
1785 "T86x_FRAG_CYCLES_DESC",
1786 "T86x_FRAG_CYCLES_FPKQ_ACTIVE",
1787 "T86x_FRAG_CYCLES_VERT",
1788 "T86x_FRAG_CYCLES_TRISETUP",
1789 "T86x_FRAG_CYCLES_EZS_ACTIVE",
1790 "T86x_FRAG_THREADS",
1791 "T86x_FRAG_DUMMY_THREADS",
1792 "T86x_FRAG_QUADS_RAST",
1793 "T86x_FRAG_QUADS_EZS_TEST",
1794 "T86x_FRAG_QUADS_EZS_KILLED",
1795 "T86x_FRAG_THREADS_LZS_TEST",
1796 "T86x_FRAG_THREADS_LZS_KILLED",
1797 "T86x_FRAG_CYCLES_NO_TILE",
1798 "T86x_FRAG_NUM_TILES",
1799 "T86x_FRAG_TRANS_ELIM",
1800 "T86x_COMPUTE_ACTIVE",
1801 "T86x_COMPUTE_TASKS",
1802 "T86x_COMPUTE_THREADS",
1803 "T86x_COMPUTE_CYCLES_DESC",
1804 "T86x_TRIPIPE_ACTIVE",
1805 "T86x_ARITH_WORDS",
1806 "T86x_ARITH_CYCLES_REG",
1807 "T86x_ARITH_CYCLES_L0",
1808 "T86x_ARITH_FRAG_DEPEND",
1809 "T86x_LS_WORDS",
1810 "T86x_LS_ISSUES",
1811 "T86x_LS_REISSUE_ATTR",
1812 "T86x_LS_REISSUES_VARY",
1813 "T86x_LS_VARY_RV_MISS",
1814 "T86x_LS_VARY_RV_HIT",
1815 "T86x_LS_NO_UNPARK",
1816 "T86x_TEX_WORDS",
1817 "T86x_TEX_BUBBLES",
1818 "T86x_TEX_WORDS_L0",
1819 "T86x_TEX_WORDS_DESC",
1820 "T86x_TEX_ISSUES",
1821 "T86x_TEX_RECIRC_FMISS",
1822 "T86x_TEX_RECIRC_DESC",
1823 "T86x_TEX_RECIRC_MULTI",
1824 "T86x_TEX_RECIRC_PMISS",
1825 "T86x_TEX_RECIRC_CONF",
1826 "T86x_LSC_READ_HITS",
1827 "T86x_LSC_READ_OP",
1828 "T86x_LSC_WRITE_HITS",
1829 "T86x_LSC_WRITE_OP",
1830 "T86x_LSC_ATOMIC_HITS",
1831 "T86x_LSC_ATOMIC_OP",
1832 "T86x_LSC_LINE_FETCHES",
1833 "T86x_LSC_DIRTY_LINE",
1834 "T86x_LSC_SNOOPS",
1835 "T86x_AXI_TLB_STALL",
1836 "T86x_AXI_TLB_MISS",
1837 "T86x_AXI_TLB_TRANSACTION",
1838 "T86x_LS_TLB_MISS",
1839 "T86x_LS_TLB_HIT",
1840 "T86x_AXI_BEATS_READ",
1841 "T86x_AXI_BEATS_WRITTEN",
1842
1843 /*L2 and MMU */
1844 "",
1845 "",
1846 "",
1847 "",
1848 "T86x_MMU_HIT",
1849 "T86x_MMU_NEW_MISS",
1850 "T86x_MMU_REPLAY_FULL",
1851 "T86x_MMU_REPLAY_MISS",
1852 "T86x_MMU_TABLE_WALK",
1853 "T86x_MMU_REQUESTS",
1854 "",
1855 "",
1856 "T86x_UTLB_HIT",
1857 "T86x_UTLB_NEW_MISS",
1858 "T86x_UTLB_REPLAY_FULL",
1859 "T86x_UTLB_REPLAY_MISS",
1860 "T86x_UTLB_STALL",
1861 "",
1862 "",
1863 "",
1864 "",
1865 "",
1866 "",
1867 "",
1868 "",
1869 "",
1870 "",
1871 "",
1872 "",
1873 "",
1874 "T86x_L2_EXT_WRITE_BEATS",
1875 "T86x_L2_EXT_READ_BEATS",
1876 "T86x_L2_ANY_LOOKUP",
1877 "T86x_L2_READ_LOOKUP",
1878 "T86x_L2_SREAD_LOOKUP",
1879 "T86x_L2_READ_REPLAY",
1880 "T86x_L2_READ_SNOOP",
1881 "T86x_L2_READ_HIT",
1882 "T86x_L2_CLEAN_MISS",
1883 "T86x_L2_WRITE_LOOKUP",
1884 "T86x_L2_SWRITE_LOOKUP",
1885 "T86x_L2_WRITE_REPLAY",
1886 "T86x_L2_WRITE_SNOOP",
1887 "T86x_L2_WRITE_HIT",
1888 "T86x_L2_EXT_READ_FULL",
1889 "",
1890 "T86x_L2_EXT_WRITE_FULL",
1891 "T86x_L2_EXT_R_W_HAZARD",
1892 "T86x_L2_EXT_READ",
1893 "T86x_L2_EXT_READ_LINE",
1894 "T86x_L2_EXT_WRITE",
1895 "T86x_L2_EXT_WRITE_LINE",
1896 "T86x_L2_EXT_WRITE_SMALL",
1897 "T86x_L2_EXT_BARRIER",
1898 "T86x_L2_EXT_AR_STALL",
1899 "T86x_L2_EXT_R_BUF_FULL",
1900 "T86x_L2_EXT_RD_BUF_FULL",
1901 "T86x_L2_EXT_R_RAW",
1902 "T86x_L2_EXT_W_STALL",
1903 "T86x_L2_EXT_W_BUF_FULL",
1904 "T86x_L2_EXT_R_BUF_FULL",
1905 "T86x_L2_TAG_HAZARD",
1906 "T86x_L2_SNOOP_FULL",
1907 "T86x_L2_REPLAY_FULL"
1908 };
1909
1910 static const char * const hardware_counters_mali_t88x[] = {
1911 /* Job Manager */
1912 "",
1913 "",
1914 "",
1915 "",
1916 "T88x_MESSAGES_SENT",
1917 "T88x_MESSAGES_RECEIVED",
1918 "T88x_GPU_ACTIVE",
1919 "T88x_IRQ_ACTIVE",
1920 "T88x_JS0_JOBS",
1921 "T88x_JS0_TASKS",
1922 "T88x_JS0_ACTIVE",
1923 "",
1924 "T88x_JS0_WAIT_READ",
1925 "T88x_JS0_WAIT_ISSUE",
1926 "T88x_JS0_WAIT_DEPEND",
1927 "T88x_JS0_WAIT_FINISH",
1928 "T88x_JS1_JOBS",
1929 "T88x_JS1_TASKS",
1930 "T88x_JS1_ACTIVE",
1931 "",
1932 "T88x_JS1_WAIT_READ",
1933 "T88x_JS1_WAIT_ISSUE",
1934 "T88x_JS1_WAIT_DEPEND",
1935 "T88x_JS1_WAIT_FINISH",
1936 "T88x_JS2_JOBS",
1937 "T88x_JS2_TASKS",
1938 "T88x_JS2_ACTIVE",
1939 "",
1940 "T88x_JS2_WAIT_READ",
1941 "T88x_JS2_WAIT_ISSUE",
1942 "T88x_JS2_WAIT_DEPEND",
1943 "T88x_JS2_WAIT_FINISH",
1944 "",
1945 "",
1946 "",
1947 "",
1948 "",
1949 "",
1950 "",
1951 "",
1952 "",
1953 "",
1954 "",
1955 "",
1956 "",
1957 "",
1958 "",
1959 "",
1960 "",
1961 "",
1962 "",
1963 "",
1964 "",
1965 "",
1966 "",
1967 "",
1968 "",
1969 "",
1970 "",
1971 "",
1972 "",
1973 "",
1974 "",
1975 "",
1976
1977 /*Tiler */
1978 "",
1979 "",
1980 "",
1981 "T88x_TI_JOBS_PROCESSED",
1982 "T88x_TI_TRIANGLES",
1983 "T88x_TI_QUADS",
1984 "T88x_TI_POLYGONS",
1985 "T88x_TI_POINTS",
1986 "T88x_TI_LINES",
1987 "T88x_TI_VCACHE_HIT",
1988 "T88x_TI_VCACHE_MISS",
1989 "T88x_TI_FRONT_FACING",
1990 "T88x_TI_BACK_FACING",
1991 "T88x_TI_PRIM_VISIBLE",
1992 "T88x_TI_PRIM_CULLED",
1993 "T88x_TI_PRIM_CLIPPED",
1994 "T88x_TI_LEVEL0",
1995 "T88x_TI_LEVEL1",
1996 "T88x_TI_LEVEL2",
1997 "T88x_TI_LEVEL3",
1998 "T88x_TI_LEVEL4",
1999 "T88x_TI_LEVEL5",
2000 "T88x_TI_LEVEL6",
2001 "T88x_TI_LEVEL7",
2002 "T88x_TI_COMMAND_1",
2003 "T88x_TI_COMMAND_2",
2004 "T88x_TI_COMMAND_3",
2005 "T88x_TI_COMMAND_4",
2006 "T88x_TI_COMMAND_5_7",
2007 "T88x_TI_COMMAND_8_15",
2008 "T88x_TI_COMMAND_16_63",
2009 "T88x_TI_COMMAND_64",
2010 "T88x_TI_COMPRESS_IN",
2011 "T88x_TI_COMPRESS_OUT",
2012 "T88x_TI_COMPRESS_FLUSH",
2013 "T88x_TI_TIMESTAMPS",
2014 "T88x_TI_PCACHE_HIT",
2015 "T88x_TI_PCACHE_MISS",
2016 "T88x_TI_PCACHE_LINE",
2017 "T88x_TI_PCACHE_STALL",
2018 "T88x_TI_WRBUF_HIT",
2019 "T88x_TI_WRBUF_MISS",
2020 "T88x_TI_WRBUF_LINE",
2021 "T88x_TI_WRBUF_PARTIAL",
2022 "T88x_TI_WRBUF_STALL",
2023 "T88x_TI_ACTIVE",
2024 "T88x_TI_LOADING_DESC",
2025 "T88x_TI_INDEX_WAIT",
2026 "T88x_TI_INDEX_RANGE_WAIT",
2027 "T88x_TI_VERTEX_WAIT",
2028 "T88x_TI_PCACHE_WAIT",
2029 "T88x_TI_WRBUF_WAIT",
2030 "T88x_TI_BUS_READ",
2031 "T88x_TI_BUS_WRITE",
2032 "",
2033 "",
2034 "",
2035 "",
2036 "",
2037 "T88x_TI_UTLB_HIT",
2038 "T88x_TI_UTLB_NEW_MISS",
2039 "T88x_TI_UTLB_REPLAY_FULL",
2040 "T88x_TI_UTLB_REPLAY_MISS",
2041 "T88x_TI_UTLB_STALL",
2042
2043 /* Shader Core */
2044 "",
2045 "",
2046 "",
2047 "",
2048 "T88x_FRAG_ACTIVE",
2049 "T88x_FRAG_PRIMITIVES",
2050 "T88x_FRAG_PRIMITIVES_DROPPED",
2051 "T88x_FRAG_CYCLES_DESC",
2052 "T88x_FRAG_CYCLES_FPKQ_ACTIVE",
2053 "T88x_FRAG_CYCLES_VERT",
2054 "T88x_FRAG_CYCLES_TRISETUP",
2055 "T88x_FRAG_CYCLES_EZS_ACTIVE",
2056 "T88x_FRAG_THREADS",
2057 "T88x_FRAG_DUMMY_THREADS",
2058 "T88x_FRAG_QUADS_RAST",
2059 "T88x_FRAG_QUADS_EZS_TEST",
2060 "T88x_FRAG_QUADS_EZS_KILLED",
2061 "T88x_FRAG_THREADS_LZS_TEST",
2062 "T88x_FRAG_THREADS_LZS_KILLED",
2063 "T88x_FRAG_CYCLES_NO_TILE",
2064 "T88x_FRAG_NUM_TILES",
2065 "T88x_FRAG_TRANS_ELIM",
2066 "T88x_COMPUTE_ACTIVE",
2067 "T88x_COMPUTE_TASKS",
2068 "T88x_COMPUTE_THREADS",
2069 "T88x_COMPUTE_CYCLES_DESC",
2070 "T88x_TRIPIPE_ACTIVE",
2071 "T88x_ARITH_WORDS",
2072 "T88x_ARITH_CYCLES_REG",
2073 "T88x_ARITH_CYCLES_L0",
2074 "T88x_ARITH_FRAG_DEPEND",
2075 "T88x_LS_WORDS",
2076 "T88x_LS_ISSUES",
2077 "T88x_LS_REISSUE_ATTR",
2078 "T88x_LS_REISSUES_VARY",
2079 "T88x_LS_VARY_RV_MISS",
2080 "T88x_LS_VARY_RV_HIT",
2081 "T88x_LS_NO_UNPARK",
2082 "T88x_TEX_WORDS",
2083 "T88x_TEX_BUBBLES",
2084 "T88x_TEX_WORDS_L0",
2085 "T88x_TEX_WORDS_DESC",
2086 "T88x_TEX_ISSUES",
2087 "T88x_TEX_RECIRC_FMISS",
2088 "T88x_TEX_RECIRC_DESC",
2089 "T88x_TEX_RECIRC_MULTI",
2090 "T88x_TEX_RECIRC_PMISS",
2091 "T88x_TEX_RECIRC_CONF",
2092 "T88x_LSC_READ_HITS",
2093 "T88x_LSC_READ_OP",
2094 "T88x_LSC_WRITE_HITS",
2095 "T88x_LSC_WRITE_OP",
2096 "T88x_LSC_ATOMIC_HITS",
2097 "T88x_LSC_ATOMIC_OP",
2098 "T88x_LSC_LINE_FETCHES",
2099 "T88x_LSC_DIRTY_LINE",
2100 "T88x_LSC_SNOOPS",
2101 "T88x_AXI_TLB_STALL",
2102 "T88x_AXI_TLB_MISS",
2103 "T88x_AXI_TLB_TRANSACTION",
2104 "T88x_LS_TLB_MISS",
2105 "T88x_LS_TLB_HIT",
2106 "T88x_AXI_BEATS_READ",
2107 "T88x_AXI_BEATS_WRITTEN",
2108
2109 /*L2 and MMU */
2110 "",
2111 "",
2112 "",
2113 "",
2114 "T88x_MMU_HIT",
2115 "T88x_MMU_NEW_MISS",
2116 "T88x_MMU_REPLAY_FULL",
2117 "T88x_MMU_REPLAY_MISS",
2118 "T88x_MMU_TABLE_WALK",
2119 "T88x_MMU_REQUESTS",
2120 "",
2121 "",
2122 "T88x_UTLB_HIT",
2123 "T88x_UTLB_NEW_MISS",
2124 "T88x_UTLB_REPLAY_FULL",
2125 "T88x_UTLB_REPLAY_MISS",
2126 "T88x_UTLB_STALL",
2127 "",
2128 "",
2129 "",
2130 "",
2131 "",
2132 "",
2133 "",
2134 "",
2135 "",
2136 "",
2137 "",
2138 "",
2139 "",
2140 "T88x_L2_EXT_WRITE_BEATS",
2141 "T88x_L2_EXT_READ_BEATS",
2142 "T88x_L2_ANY_LOOKUP",
2143 "T88x_L2_READ_LOOKUP",
2144 "T88x_L2_SREAD_LOOKUP",
2145 "T88x_L2_READ_REPLAY",
2146 "T88x_L2_READ_SNOOP",
2147 "T88x_L2_READ_HIT",
2148 "T88x_L2_CLEAN_MISS",
2149 "T88x_L2_WRITE_LOOKUP",
2150 "T88x_L2_SWRITE_LOOKUP",
2151 "T88x_L2_WRITE_REPLAY",
2152 "T88x_L2_WRITE_SNOOP",
2153 "T88x_L2_WRITE_HIT",
2154 "T88x_L2_EXT_READ_FULL",
2155 "",
2156 "T88x_L2_EXT_WRITE_FULL",
2157 "T88x_L2_EXT_R_W_HAZARD",
2158 "T88x_L2_EXT_READ",
2159 "T88x_L2_EXT_READ_LINE",
2160 "T88x_L2_EXT_WRITE",
2161 "T88x_L2_EXT_WRITE_LINE",
2162 "T88x_L2_EXT_WRITE_SMALL",
2163 "T88x_L2_EXT_BARRIER",
2164 "T88x_L2_EXT_AR_STALL",
2165 "T88x_L2_EXT_R_BUF_FULL",
2166 "T88x_L2_EXT_RD_BUF_FULL",
2167 "T88x_L2_EXT_R_RAW",
2168 "T88x_L2_EXT_W_STALL",
2169 "T88x_L2_EXT_W_BUF_FULL",
2170 "T88x_L2_EXT_R_BUF_FULL",
2171 "T88x_L2_TAG_HAZARD",
2172 "T88x_L2_SNOOP_FULL",
2173 "T88x_L2_REPLAY_FULL"
2174 };
2175
2176 static const char * const hardware_counters_mali_tHEx[] = {
2177 /* Performance counters for the Job Manager */
2178 "",
2179 "",
2180 "",
2181 "",
2182 "THEx_MESSAGES_SENT",
2183 "THEx_MESSAGES_RECEIVED",
2184 "THEx_GPU_ACTIVE",
2185 "THEx_IRQ_ACTIVE",
2186 "THEx_JS0_JOBS",
2187 "THEx_JS0_TASKS",
2188 "THEx_JS0_ACTIVE",
2189 "",
2190 "THEx_JS0_WAIT_READ",
2191 "THEx_JS0_WAIT_ISSUE",
2192 "THEx_JS0_WAIT_DEPEND",
2193 "THEx_JS0_WAIT_FINISH",
2194 "THEx_JS1_JOBS",
2195 "THEx_JS1_TASKS",
2196 "THEx_JS1_ACTIVE",
2197 "",
2198 "THEx_JS1_WAIT_READ",
2199 "THEx_JS1_WAIT_ISSUE",
2200 "THEx_JS1_WAIT_DEPEND",
2201 "THEx_JS1_WAIT_FINISH",
2202 "THEx_JS2_JOBS",
2203 "THEx_JS2_TASKS",
2204 "THEx_JS2_ACTIVE",
2205 "",
2206 "THEx_JS2_WAIT_READ",
2207 "THEx_JS2_WAIT_ISSUE",
2208 "THEx_JS2_WAIT_DEPEND",
2209 "THEx_JS2_WAIT_FINISH",
2210 "",
2211 "",
2212 "",
2213 "",
2214 "",
2215 "",
2216 "",
2217 "",
2218 "",
2219 "",
2220 "",
2221 "",
2222 "",
2223 "",
2224 "",
2225 "",
2226 "",
2227 "",
2228 "",
2229 "",
2230 "",
2231 "",
2232 "",
2233 "",
2234 "",
2235 "",
2236 "",
2237 "",
2238 "",
2239 "",
2240 "",
2241 "",
2242
2243 /* Performance counters for the Tiler */
2244 "",
2245 "",
2246 "",
2247 "",
2248 "THEx_TILER_ACTIVE",
2249 "THEx_JOBS_PROCESSED",
2250 "THEx_TRIANGLES",
2251 "THEx_LINES",
2252 "THEx_POINTS",
2253 "THEx_FRONT_FACING",
2254 "THEx_BACK_FACING",
2255 "THEx_PRIM_VISIBLE",
2256 "THEx_PRIM_CULLED",
2257 "THEx_PRIM_CLIPPED",
2258 "THEx_PRIM_SAT_CULLED",
2259 "",
2260 "",
2261 "THEx_BUS_READ",
2262 "",
2263 "THEx_BUS_WRITE",
2264 "THEx_LOADING_DESC",
2265 "THEx_IDVS_POS_SHAD_REQ",
2266 "THEx_IDVS_POS_SHAD_WAIT",
2267 "THEx_IDVS_POS_SHAD_STALL",
2268 "THEx_IDVS_POS_FIFO_FULL",
2269 "THEx_PREFETCH_STALL",
2270 "THEx_VCACHE_HIT",
2271 "THEx_VCACHE_MISS",
2272 "THEx_VCACHE_LINE_WAIT",
2273 "THEx_VFETCH_POS_READ_WAIT",
2274 "THEx_VFETCH_VERTEX_WAIT",
2275 "THEx_VFETCH_STALL",
2276 "THEx_PRIMASSY_STALL",
2277 "THEx_BBOX_GEN_STALL",
2278 "THEx_IDVS_VBU_HIT",
2279 "THEx_IDVS_VBU_MISS",
2280 "THEx_IDVS_VBU_LINE_DEALLOCATE",
2281 "THEx_IDVS_VAR_SHAD_REQ",
2282 "THEx_IDVS_VAR_SHAD_STALL",
2283 "THEx_BINNER_STALL",
2284 "THEx_ITER_STALL",
2285 "THEx_COMPRESS_MISS",
2286 "THEx_COMPRESS_STALL",
2287 "THEx_PCACHE_HIT",
2288 "THEx_PCACHE_MISS",
2289 "THEx_PCACHE_MISS_STALL",
2290 "THEx_PCACHE_EVICT_STALL",
2291 "THEx_PMGR_PTR_WR_STALL",
2292 "THEx_PMGR_PTR_RD_STALL",
2293 "THEx_PMGR_CMD_WR_STALL",
2294 "THEx_WRBUF_ACTIVE",
2295 "THEx_WRBUF_HIT",
2296 "THEx_WRBUF_MISS",
2297 "THEx_WRBUF_NO_FREE_LINE_STALL",
2298 "THEx_WRBUF_NO_AXI_ID_STALL",
2299 "THEx_WRBUF_AXI_STALL",
2300 "",
2301 "",
2302 "",
2303 "THEx_UTLB_TRANS",
2304 "THEx_UTLB_TRANS_HIT",
2305 "THEx_UTLB_TRANS_STALL",
2306 "THEx_UTLB_TRANS_MISS_DELAY",
2307 "THEx_UTLB_MMU_REQ",
2308
2309 /* Performance counters for the Shader Core */
2310 "",
2311 "",
2312 "",
2313 "",
2314 "THEx_FRAG_ACTIVE",
2315 "THEx_FRAG_PRIMITIVES",
2316 "THEx_FRAG_PRIM_RAST",
2317 "THEx_FRAG_FPK_ACTIVE",
2318 "THEx_FRAG_STARVING",
2319 "THEx_FRAG_WARPS",
2320 "THEx_FRAG_PARTIAL_WARPS",
2321 "THEx_FRAG_QUADS_RAST",
2322 "THEx_FRAG_QUADS_EZS_TEST",
2323 "THEx_FRAG_QUADS_EZS_UPDATE",
2324 "THEx_FRAG_QUADS_EZS_KILL",
2325 "THEx_FRAG_LZS_TEST",
2326 "THEx_FRAG_LZS_KILL",
2327 "",
2328 "THEx_FRAG_PTILES",
2329 "THEx_FRAG_TRANS_ELIM",
2330 "THEx_QUAD_FPK_KILLER",
2331 "",
2332 "THEx_COMPUTE_ACTIVE",
2333 "THEx_COMPUTE_TASKS",
2334 "THEx_COMPUTE_WARPS",
2335 "THEx_COMPUTE_STARVING",
2336 "THEx_EXEC_CORE_ACTIVE",
2337 "THEx_EXEC_ACTIVE",
2338 "THEx_EXEC_INSTR_COUNT",
2339 "THEx_EXEC_INSTR_DIVERGED",
2340 "THEx_EXEC_INSTR_STARVING",
2341 "THEx_ARITH_INSTR_SINGLE_FMA",
2342 "THEx_ARITH_INSTR_DOUBLE",
2343 "THEx_ARITH_INSTR_MSG",
2344 "THEx_ARITH_INSTR_MSG_ONLY",
2345 "THEx_TEX_INSTR",
2346 "THEx_TEX_INSTR_MIPMAP",
2347 "THEx_TEX_INSTR_COMPRESSED",
2348 "THEx_TEX_INSTR_3D",
2349 "THEx_TEX_INSTR_TRILINEAR",
2350 "THEx_TEX_COORD_ISSUE",
2351 "THEx_TEX_COORD_STALL",
2352 "THEx_TEX_STARVE_CACHE",
2353 "THEx_TEX_STARVE_FILTER",
2354 "THEx_LS_MEM_READ_FULL",
2355 "THEx_LS_MEM_READ_SHORT",
2356 "THEx_LS_MEM_WRITE_FULL",
2357 "THEx_LS_MEM_WRITE_SHORT",
2358 "THEx_LS_MEM_ATOMIC",
2359 "THEx_VARY_INSTR",
2360 "THEx_VARY_SLOT_32",
2361 "THEx_VARY_SLOT_16",
2362 "THEx_ATTR_INSTR",
2363 "THEx_ARITH_INSTR_FP_MUL",
2364 "THEx_BEATS_RD_FTC",
2365 "THEx_BEATS_RD_FTC_EXT",
2366 "THEx_BEATS_RD_LSC",
2367 "THEx_BEATS_RD_LSC_EXT",
2368 "THEx_BEATS_RD_TEX",
2369 "THEx_BEATS_RD_TEX_EXT",
2370 "THEx_BEATS_RD_OTHER",
2371 "THEx_BEATS_WR_LSC",
2372 "THEx_BEATS_WR_TIB",
2373 "",
2374
2375 /* Performance counters for the Memory System */
2376 "",
2377 "",
2378 "",
2379 "",
2380 "THEx_MMU_REQUESTS",
2381 "",
2382 "",
2383 "",
2384 "",
2385 "",
2386 "",
2387 "",
2388 "",
2389 "",
2390 "",
2391 "",
2392 "THEx_L2_RD_MSG_IN",
2393 "THEx_L2_RD_MSG_IN_STALL",
2394 "THEx_L2_WR_MSG_IN",
2395 "THEx_L2_WR_MSG_IN_STALL",
2396 "THEx_L2_SNP_MSG_IN",
2397 "THEx_L2_SNP_MSG_IN_STALL",
2398 "THEx_L2_RD_MSG_OUT",
2399 "THEx_L2_RD_MSG_OUT_STALL",
2400 "THEx_L2_WR_MSG_OUT",
2401 "THEx_L2_ANY_LOOKUP",
2402 "THEx_L2_READ_LOOKUP",
2403 "THEx_L2_WRITE_LOOKUP",
2404 "THEx_L2_EXT_SNOOP_LOOKUP",
2405 "THEx_L2_EXT_READ",
2406 "THEx_L2_EXT_READ_NOSNP",
2407 "THEx_L2_EXT_READ_UNIQUE",
2408 "THEx_L2_EXT_READ_BEATS",
2409 "THEx_L2_EXT_AR_STALL",
2410 "THEx_L2_EXT_AR_CNT_Q1",
2411 "THEx_L2_EXT_AR_CNT_Q2",
2412 "THEx_L2_EXT_AR_CNT_Q3",
2413 "THEx_L2_EXT_RRESP_0_127",
2414 "THEx_L2_EXT_RRESP_128_191",
2415 "THEx_L2_EXT_RRESP_192_255",
2416 "THEx_L2_EXT_RRESP_256_319",
2417 "THEx_L2_EXT_RRESP_320_383",
2418 "THEx_L2_EXT_WRITE",
2419 "THEx_L2_EXT_WRITE_NOSNP_FULL",
2420 "THEx_L2_EXT_WRITE_NOSNP_PTL",
2421 "THEx_L2_EXT_WRITE_SNP_FULL",
2422 "THEx_L2_EXT_WRITE_SNP_PTL",
2423 "THEx_L2_EXT_WRITE_BEATS",
2424 "THEx_L2_EXT_W_STALL",
2425 "THEx_L2_EXT_AW_CNT_Q1",
2426 "THEx_L2_EXT_AW_CNT_Q2",
2427 "THEx_L2_EXT_AW_CNT_Q3",
2428 "THEx_L2_EXT_SNOOP",
2429 "THEx_L2_EXT_SNOOP_STALL",
2430 "THEx_L2_EXT_SNOOP_RESP_CLEAN",
2431 "THEx_L2_EXT_SNOOP_RESP_DATA",
2432 "THEx_L2_EXT_SNOOP_INTERNAL",
2433 "",
2434 "",
2435 "",
2436 "",
2437 "",
2438 "",
2439 "",
2440 };
2441
2442 static const char * const hardware_counters_mali_tMIx[] = {
2443 /* Performance counters for the Job Manager */
2444 "",
2445 "",
2446 "",
2447 "",
2448 "TMIx_MESSAGES_SENT",
2449 "TMIx_MESSAGES_RECEIVED",
2450 "TMIx_GPU_ACTIVE",
2451 "TMIx_IRQ_ACTIVE",
2452 "TMIx_JS0_JOBS",
2453 "TMIx_JS0_TASKS",
2454 "TMIx_JS0_ACTIVE",
2455 "",
2456 "TMIx_JS0_WAIT_READ",
2457 "TMIx_JS0_WAIT_ISSUE",
2458 "TMIx_JS0_WAIT_DEPEND",
2459 "TMIx_JS0_WAIT_FINISH",
2460 "TMIx_JS1_JOBS",
2461 "TMIx_JS1_TASKS",
2462 "TMIx_JS1_ACTIVE",
2463 "",
2464 "TMIx_JS1_WAIT_READ",
2465 "TMIx_JS1_WAIT_ISSUE",
2466 "TMIx_JS1_WAIT_DEPEND",
2467 "TMIx_JS1_WAIT_FINISH",
2468 "TMIx_JS2_JOBS",
2469 "TMIx_JS2_TASKS",
2470 "TMIx_JS2_ACTIVE",
2471 "",
2472 "TMIx_JS2_WAIT_READ",
2473 "TMIx_JS2_WAIT_ISSUE",
2474 "TMIx_JS2_WAIT_DEPEND",
2475 "TMIx_JS2_WAIT_FINISH",
2476 "",
2477 "",
2478 "",
2479 "",
2480 "",
2481 "",
2482 "",
2483 "",
2484 "",
2485 "",
2486 "",
2487 "",
2488 "",
2489 "",
2490 "",
2491 "",
2492 "",
2493 "",
2494 "",
2495 "",
2496 "",
2497 "",
2498 "",
2499 "",
2500 "",
2501 "",
2502 "",
2503 "",
2504 "",
2505 "",
2506 "",
2507 "",
2508
2509 /* Performance counters for the Tiler */
2510 "",
2511 "",
2512 "",
2513 "",
2514 "TMIx_TILER_ACTIVE",
2515 "TMIx_JOBS_PROCESSED",
2516 "TMIx_TRIANGLES",
2517 "TMIx_LINES",
2518 "TMIx_POINTS",
2519 "TMIx_FRONT_FACING",
2520 "TMIx_BACK_FACING",
2521 "TMIx_PRIM_VISIBLE",
2522 "TMIx_PRIM_CULLED",
2523 "TMIx_PRIM_CLIPPED",
2524 "TMIx_PRIM_SAT_CULLED",
2525 "",
2526 "",
2527 "TMIx_BUS_READ",
2528 "",
2529 "TMIx_BUS_WRITE",
2530 "TMIx_LOADING_DESC",
2531 "TMIx_IDVS_POS_SHAD_REQ",
2532 "TMIx_IDVS_POS_SHAD_WAIT",
2533 "TMIx_IDVS_POS_SHAD_STALL",
2534 "TMIx_IDVS_POS_FIFO_FULL",
2535 "TMIx_PREFETCH_STALL",
2536 "TMIx_VCACHE_HIT",
2537 "TMIx_VCACHE_MISS",
2538 "TMIx_VCACHE_LINE_WAIT",
2539 "TMIx_VFETCH_POS_READ_WAIT",
2540 "TMIx_VFETCH_VERTEX_WAIT",
2541 "TMIx_VFETCH_STALL",
2542 "TMIx_PRIMASSY_STALL",
2543 "TMIx_BBOX_GEN_STALL",
2544 "TMIx_IDVS_VBU_HIT",
2545 "TMIx_IDVS_VBU_MISS",
2546 "TMIx_IDVS_VBU_LINE_DEALLOCATE",
2547 "TMIx_IDVS_VAR_SHAD_REQ",
2548 "TMIx_IDVS_VAR_SHAD_STALL",
2549 "TMIx_BINNER_STALL",
2550 "TMIx_ITER_STALL",
2551 "TMIx_COMPRESS_MISS",
2552 "TMIx_COMPRESS_STALL",
2553 "TMIx_PCACHE_HIT",
2554 "TMIx_PCACHE_MISS",
2555 "TMIx_PCACHE_MISS_STALL",
2556 "TMIx_PCACHE_EVICT_STALL",
2557 "TMIx_PMGR_PTR_WR_STALL",
2558 "TMIx_PMGR_PTR_RD_STALL",
2559 "TMIx_PMGR_CMD_WR_STALL",
2560 "TMIx_WRBUF_ACTIVE",
2561 "TMIx_WRBUF_HIT",
2562 "TMIx_WRBUF_MISS",
2563 "TMIx_WRBUF_NO_FREE_LINE_STALL",
2564 "TMIx_WRBUF_NO_AXI_ID_STALL",
2565 "TMIx_WRBUF_AXI_STALL",
2566 "",
2567 "",
2568 "",
2569 "TMIx_UTLB_TRANS",
2570 "TMIx_UTLB_TRANS_HIT",
2571 "TMIx_UTLB_TRANS_STALL",
2572 "TMIx_UTLB_TRANS_MISS_DELAY",
2573 "TMIx_UTLB_MMU_REQ",
2574
2575 /* Performance counters for the Shader Core */
2576 "",
2577 "",
2578 "",
2579 "",
2580 "TMIx_FRAG_ACTIVE",
2581 "TMIx_FRAG_PRIMITIVES",
2582 "TMIx_FRAG_PRIM_RAST",
2583 "TMIx_FRAG_FPK_ACTIVE",
2584 "TMIx_FRAG_STARVING",
2585 "TMIx_FRAG_WARPS",
2586 "TMIx_FRAG_PARTIAL_WARPS",
2587 "TMIx_FRAG_QUADS_RAST",
2588 "TMIx_FRAG_QUADS_EZS_TEST",
2589 "TMIx_FRAG_QUADS_EZS_UPDATE",
2590 "TMIx_FRAG_QUADS_EZS_KILL",
2591 "TMIx_FRAG_LZS_TEST",
2592 "TMIx_FRAG_LZS_KILL",
2593 "",
2594 "TMIx_FRAG_PTILES",
2595 "TMIx_FRAG_TRANS_ELIM",
2596 "TMIx_QUAD_FPK_KILLER",
2597 "",
2598 "TMIx_COMPUTE_ACTIVE",
2599 "TMIx_COMPUTE_TASKS",
2600 "TMIx_COMPUTE_WARPS",
2601 "TMIx_COMPUTE_STARVING",
2602 "TMIx_EXEC_CORE_ACTIVE",
2603 "TMIx_EXEC_ACTIVE",
2604 "TMIx_EXEC_INSTR_COUNT",
2605 "TMIx_EXEC_INSTR_DIVERGED",
2606 "TMIx_EXEC_INSTR_STARVING",
2607 "TMIx_ARITH_INSTR_SINGLE_FMA",
2608 "TMIx_ARITH_INSTR_DOUBLE",
2609 "TMIx_ARITH_INSTR_MSG",
2610 "TMIx_ARITH_INSTR_MSG_ONLY",
2611 "TMIx_TEX_INSTR",
2612 "TMIx_TEX_INSTR_MIPMAP",
2613 "TMIx_TEX_INSTR_COMPRESSED",
2614 "TMIx_TEX_INSTR_3D",
2615 "TMIx_TEX_INSTR_TRILINEAR",
2616 "TMIx_TEX_COORD_ISSUE",
2617 "TMIx_TEX_COORD_STALL",
2618 "TMIx_TEX_STARVE_CACHE",
2619 "TMIx_TEX_STARVE_FILTER",
2620 "TMIx_LS_MEM_READ_FULL",
2621 "TMIx_LS_MEM_READ_SHORT",
2622 "TMIx_LS_MEM_WRITE_FULL",
2623 "TMIx_LS_MEM_WRITE_SHORT",
2624 "TMIx_LS_MEM_ATOMIC",
2625 "TMIx_VARY_INSTR",
2626 "TMIx_VARY_SLOT_32",
2627 "TMIx_VARY_SLOT_16",
2628 "TMIx_ATTR_INSTR",
2629 "TMIx_ARITH_INSTR_FP_MUL",
2630 "TMIx_BEATS_RD_FTC",
2631 "TMIx_BEATS_RD_FTC_EXT",
2632 "TMIx_BEATS_RD_LSC",
2633 "TMIx_BEATS_RD_LSC_EXT",
2634 "TMIx_BEATS_RD_TEX",
2635 "TMIx_BEATS_RD_TEX_EXT",
2636 "TMIx_BEATS_RD_OTHER",
2637 "TMIx_BEATS_WR_LSC",
2638 "TMIx_BEATS_WR_TIB",
2639 "",
2640
2641 /* Performance counters for the Memory System */
2642 "",
2643 "",
2644 "",
2645 "",
2646 "TMIx_MMU_REQUESTS",
2647 "",
2648 "",
2649 "",
2650 "",
2651 "",
2652 "",
2653 "",
2654 "",
2655 "",
2656 "",
2657 "",
2658 "TMIx_L2_RD_MSG_IN",
2659 "TMIx_L2_RD_MSG_IN_STALL",
2660 "TMIx_L2_WR_MSG_IN",
2661 "TMIx_L2_WR_MSG_IN_STALL",
2662 "TMIx_L2_SNP_MSG_IN",
2663 "TMIx_L2_SNP_MSG_IN_STALL",
2664 "TMIx_L2_RD_MSG_OUT",
2665 "TMIx_L2_RD_MSG_OUT_STALL",
2666 "TMIx_L2_WR_MSG_OUT",
2667 "TMIx_L2_ANY_LOOKUP",
2668 "TMIx_L2_READ_LOOKUP",
2669 "TMIx_L2_WRITE_LOOKUP",
2670 "TMIx_L2_EXT_SNOOP_LOOKUP",
2671 "TMIx_L2_EXT_READ",
2672 "TMIx_L2_EXT_READ_NOSNP",
2673 "TMIx_L2_EXT_READ_UNIQUE",
2674 "TMIx_L2_EXT_READ_BEATS",
2675 "TMIx_L2_EXT_AR_STALL",
2676 "TMIx_L2_EXT_AR_CNT_Q1",
2677 "TMIx_L2_EXT_AR_CNT_Q2",
2678 "TMIx_L2_EXT_AR_CNT_Q3",
2679 "TMIx_L2_EXT_RRESP_0_127",
2680 "TMIx_L2_EXT_RRESP_128_191",
2681 "TMIx_L2_EXT_RRESP_192_255",
2682 "TMIx_L2_EXT_RRESP_256_319",
2683 "TMIx_L2_EXT_RRESP_320_383",
2684 "TMIx_L2_EXT_WRITE",
2685 "TMIx_L2_EXT_WRITE_NOSNP_FULL",
2686 "TMIx_L2_EXT_WRITE_NOSNP_PTL",
2687 "TMIx_L2_EXT_WRITE_SNP_FULL",
2688 "TMIx_L2_EXT_WRITE_SNP_PTL",
2689 "TMIx_L2_EXT_WRITE_BEATS",
2690 "TMIx_L2_EXT_W_STALL",
2691 "TMIx_L2_EXT_AW_CNT_Q1",
2692 "TMIx_L2_EXT_AW_CNT_Q2",
2693 "TMIx_L2_EXT_AW_CNT_Q3",
2694 "TMIx_L2_EXT_SNOOP",
2695 "TMIx_L2_EXT_SNOOP_STALL",
2696 "TMIx_L2_EXT_SNOOP_RESP_CLEAN",
2697 "TMIx_L2_EXT_SNOOP_RESP_DATA",
2698 "TMIx_L2_EXT_SNOOP_INTERNAL",
2699 "",
2700 "",
2701 "",
2702 "",
2703 "",
2704 "",
2705 "",
2706 };
2707
2708 static const char * const hardware_counters_mali_tSIx[] = {
2709 /* Performance counters for the Job Manager */
2710 "",
2711 "",
2712 "",
2713 "",
2714 "TSIx_MESSAGES_SENT",
2715 "TSIx_MESSAGES_RECEIVED",
2716 "TSIx_GPU_ACTIVE",
2717 "TSIx_IRQ_ACTIVE",
2718 "TSIx_JS0_JOBS",
2719 "TSIx_JS0_TASKS",
2720 "TSIx_JS0_ACTIVE",
2721 "",
2722 "TSIx_JS0_WAIT_READ",
2723 "TSIx_JS0_WAIT_ISSUE",
2724 "TSIx_JS0_WAIT_DEPEND",
2725 "TSIx_JS0_WAIT_FINISH",
2726 "TSIx_JS1_JOBS",
2727 "TSIx_JS1_TASKS",
2728 "TSIx_JS1_ACTIVE",
2729 "",
2730 "TSIx_JS1_WAIT_READ",
2731 "TSIx_JS1_WAIT_ISSUE",
2732 "TSIx_JS1_WAIT_DEPEND",
2733 "TSIx_JS1_WAIT_FINISH",
2734 "TSIx_JS2_JOBS",
2735 "TSIx_JS2_TASKS",
2736 "TSIx_JS2_ACTIVE",
2737 "",
2738 "TSIx_JS2_WAIT_READ",
2739 "TSIx_JS2_WAIT_ISSUE",
2740 "TSIx_JS2_WAIT_DEPEND",
2741 "TSIx_JS2_WAIT_FINISH",
2742 "",
2743 "",
2744 "",
2745 "",
2746 "",
2747 "",
2748 "",
2749 "",
2750 "",
2751 "",
2752 "",
2753 "",
2754 "",
2755 "",
2756 "",
2757 "",
2758 "",
2759 "",
2760 "",
2761 "",
2762 "",
2763 "",
2764 "",
2765 "",
2766 "",
2767 "",
2768 "",
2769 "",
2770 "",
2771 "",
2772 "",
2773 "",
2774
2775 /* Performance counters for the Tiler */
2776 "",
2777 "",
2778 "",
2779 "",
2780 "TSIx_TILER_ACTIVE",
2781 "TSIx_JOBS_PROCESSED",
2782 "TSIx_TRIANGLES",
2783 "TSIx_LINES",
2784 "TSIx_POINTS",
2785 "TSIx_FRONT_FACING",
2786 "TSIx_BACK_FACING",
2787 "TSIx_PRIM_VISIBLE",
2788 "TSIx_PRIM_CULLED",
2789 "TSIx_PRIM_CLIPPED",
2790 "TSIx_PRIM_SAT_CULLED",
2791 "",
2792 "",
2793 "TSIx_BUS_READ",
2794 "",
2795 "TSIx_BUS_WRITE",
2796 "TSIx_LOADING_DESC",
2797 "",
2798 "",
2799 "",
2800 "",
2801 "TSIx_PREFETCH_STALL",
2802 "TSIx_VCACHE_HIT",
2803 "TSIx_VCACHE_MISS",
2804 "TSIx_VCACHE_LINE_WAIT",
2805 "TSIx_VFETCH_POS_READ_WAIT",
2806 "TSIx_VFETCH_VERTEX_WAIT",
2807 "TSIx_VFETCH_STALL",
2808 "TSIx_PRIMASSY_STALL",
2809 "TSIx_BBOX_GEN_STALL",
2810 "",
2811 "",
2812 "",
2813 "",
2814 "",
2815 "TSIx_BINNER_STALL",
2816 "TSIx_ITER_STALL",
2817 "TSIx_COMPRESS_MISS",
2818 "TSIx_COMPRESS_STALL",
2819 "TSIx_PCACHE_HIT",
2820 "TSIx_PCACHE_MISS",
2821 "TSIx_PCACHE_MISS_STALL",
2822 "TSIx_PCACHE_EVICT_STALL",
2823 "TSIx_PMGR_PTR_WR_STALL",
2824 "TSIx_PMGR_PTR_RD_STALL",
2825 "TSIx_PMGR_CMD_WR_STALL",
2826 "TSIx_WRBUF_ACTIVE",
2827 "TSIx_WRBUF_HIT",
2828 "TSIx_WRBUF_MISS",
2829 "TSIx_WRBUF_NO_FREE_LINE_STALL",
2830 "TSIx_WRBUF_NO_AXI_ID_STALL",
2831 "TSIx_WRBUF_AXI_STALL",
2832 "",
2833 "",
2834 "",
2835 "TSIx_UTLB_TRANS",
2836 "TSIx_UTLB_TRANS_HIT",
2837 "TSIx_UTLB_TRANS_STALL",
2838 "TSIx_UTLB_TRANS_MISS_DELAY",
2839 "TSIx_UTLB_MMU_REQ",
2840
2841 /* Performance counters for the Shader Core */
2842 "",
2843 "",
2844 "",
2845 "",
2846 "TSIx_FRAG_ACTIVE",
2847 "TSIx_FRAG_PRIMITIVES",
2848 "TSIx_FRAG_PRIM_RAST",
2849 "TSIx_FRAG_FPK_ACTIVE",
2850 "TSIx_FRAG_STARVING",
2851 "TSIx_FRAG_WARPS",
2852 "TSIx_FRAG_PARTIAL_WARPS",
2853 "TSIx_FRAG_QUADS_RAST",
2854 "TSIx_FRAG_QUADS_EZS_TEST",
2855 "TSIx_FRAG_QUADS_EZS_UPDATE",
2856 "TSIx_FRAG_QUADS_EZS_KILL",
2857 "TSIx_FRAG_LZS_TEST",
2858 "TSIx_FRAG_LZS_KILL",
2859 "",
2860 "TSIx_FRAG_PTILES",
2861 "TSIx_FRAG_TRANS_ELIM",
2862 "TSIx_QUAD_FPK_KILLER",
2863 "",
2864 "TSIx_COMPUTE_ACTIVE",
2865 "TSIx_COMPUTE_TASKS",
2866 "TSIx_COMPUTE_WARPS",
2867 "TSIx_COMPUTE_STARVING",
2868 "TSIx_EXEC_CORE_ACTIVE",
2869 "TSIx_EXEC_ACTIVE",
2870 "TSIx_EXEC_INSTR_COUNT",
2871 "TSIx_EXEC_INSTR_DIVERGED",
2872 "TSIx_EXEC_INSTR_STARVING",
2873 "TSIx_ARITH_INSTR_SINGLE_FMA",
2874 "TSIx_ARITH_INSTR_DOUBLE",
2875 "TSIx_ARITH_INSTR_MSG",
2876 "TSIx_ARITH_INSTR_MSG_ONLY",
2877 "TSIx_TEX_INSTR",
2878 "TSIx_TEX_INSTR_MIPMAP",
2879 "TSIx_TEX_INSTR_COMPRESSED",
2880 "TSIx_TEX_INSTR_3D",
2881 "TSIx_TEX_INSTR_TRILINEAR",
2882 "TSIx_TEX_COORD_ISSUE",
2883 "TSIx_TEX_COORD_STALL",
2884 "TSIx_TEX_STARVE_CACHE",
2885 "TSIx_TEX_STARVE_FILTER",
2886 "TSIx_LS_MEM_READ_FULL",
2887 "TSIx_LS_MEM_READ_SHORT",
2888 "TSIx_LS_MEM_WRITE_FULL",
2889 "TSIx_LS_MEM_WRITE_SHORT",
2890 "TSIx_LS_MEM_ATOMIC",
2891 "TSIx_VARY_INSTR",
2892 "TSIx_VARY_SLOT_32",
2893 "TSIx_VARY_SLOT_16",
2894 "TSIx_ATTR_INSTR",
2895 "TSIx_ARITH_INSTR_FP_MUL",
2896 "TSIx_BEATS_RD_FTC",
2897 "TSIx_BEATS_RD_FTC_EXT",
2898 "TSIx_BEATS_RD_LSC",
2899 "TSIx_BEATS_RD_LSC_EXT",
2900 "TSIx_BEATS_RD_TEX",
2901 "TSIx_BEATS_RD_TEX_EXT",
2902 "TSIx_BEATS_RD_OTHER",
2903 "TSIx_BEATS_WR_LSC",
2904 "TSIx_BEATS_WR_TIB",
2905 "",
2906
2907 /* Performance counters for the Memory System */
2908 "",
2909 "",
2910 "",
2911 "",
2912 "TSIx_MMU_REQUESTS",
2913 "",
2914 "",
2915 "",
2916 "",
2917 "",
2918 "",
2919 "",
2920 "",
2921 "",
2922 "",
2923 "",
2924 "TSIx_L2_RD_MSG_IN",
2925 "TSIx_L2_RD_MSG_IN_STALL",
2926 "TSIx_L2_WR_MSG_IN",
2927 "TSIx_L2_WR_MSG_IN_STALL",
2928 "TSIx_L2_SNP_MSG_IN",
2929 "TSIx_L2_SNP_MSG_IN_STALL",
2930 "TSIx_L2_RD_MSG_OUT",
2931 "TSIx_L2_RD_MSG_OUT_STALL",
2932 "TSIx_L2_WR_MSG_OUT",
2933 "TSIx_L2_ANY_LOOKUP",
2934 "TSIx_L2_READ_LOOKUP",
2935 "TSIx_L2_WRITE_LOOKUP",
2936 "TSIx_L2_EXT_SNOOP_LOOKUP",
2937 "TSIx_L2_EXT_READ",
2938 "TSIx_L2_EXT_READ_NOSNP",
2939 "TSIx_L2_EXT_READ_UNIQUE",
2940 "TSIx_L2_EXT_READ_BEATS",
2941 "TSIx_L2_EXT_AR_STALL",
2942 "TSIx_L2_EXT_AR_CNT_Q1",
2943 "TSIx_L2_EXT_AR_CNT_Q2",
2944 "TSIx_L2_EXT_AR_CNT_Q3",
2945 "TSIx_L2_EXT_RRESP_0_127",
2946 "TSIx_L2_EXT_RRESP_128_191",
2947 "TSIx_L2_EXT_RRESP_192_255",
2948 "TSIx_L2_EXT_RRESP_256_319",
2949 "TSIx_L2_EXT_RRESP_320_383",
2950 "TSIx_L2_EXT_WRITE",
2951 "TSIx_L2_EXT_WRITE_NOSNP_FULL",
2952 "TSIx_L2_EXT_WRITE_NOSNP_PTL",
2953 "TSIx_L2_EXT_WRITE_SNP_FULL",
2954 "TSIx_L2_EXT_WRITE_SNP_PTL",
2955 "TSIx_L2_EXT_WRITE_BEATS",
2956 "TSIx_L2_EXT_W_STALL",
2957 "TSIx_L2_EXT_AW_CNT_Q1",
2958 "TSIx_L2_EXT_AW_CNT_Q2",
2959 "TSIx_L2_EXT_AW_CNT_Q3",
2960 "TSIx_L2_EXT_SNOOP",
2961 "TSIx_L2_EXT_SNOOP_STALL",
2962 "TSIx_L2_EXT_SNOOP_RESP_CLEAN",
2963 "TSIx_L2_EXT_SNOOP_RESP_DATA",
2964 "TSIx_L2_EXT_SNOOP_INTERNAL",
2965 "",
2966 "",
2967 "",
2968 "",
2969 "",
2970 "",
2971 "",
2972 };
2973
2974 enum {
2975 /* product id masks for old and new versions of the id field. NB: the T60x must be tested before anything else as it could exceptionally be
2976 * treated as a new style of id with produce code 0x6006 */
2977 PRODUCT_ID_MASK_OLD = 0xffff,
2978 PRODUCT_ID_MASK_NEW = 0xf00f,
2979 /* Old style product ids */
2980 PRODUCT_ID_T60X = 0x6956,
2981 PRODUCT_ID_T62X = 0x0620,
2982 PRODUCT_ID_T72X = 0x0720,
2983 PRODUCT_ID_T76X = 0x0750,
2984 PRODUCT_ID_T82X = 0x0820,
2985 PRODUCT_ID_T83X = 0x0830,
2986 PRODUCT_ID_T86X = 0x0860,
2987 PRODUCT_ID_TFRX = 0x0880,
2988 /* New style product ids */
2989 PRODUCT_ID_TMIX = 0x6000,
2990 PRODUCT_ID_THEX = 0x6001,
2991 PRODUCT_ID_TSIX = 0x7000
2992 };
2993
2994 struct CounterMapping
2995 {
2996 uint32_t product_mask;
2997 uint32_t product_id;
2998 const char * const *names_lut;
2999 };
3000
3001 static const CounterMapping products[] = {
3002 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T60X, hardware_counters_mali_t60x, },
3003 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T62X, hardware_counters_mali_t62x, },
3004 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T72X, hardware_counters_mali_t72x, },
3005 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T76X, hardware_counters_mali_t76x, },
3006 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T82X, hardware_counters_mali_t82x, },
3007 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T83X, hardware_counters_mali_t83x, },
3008 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_T86X, hardware_counters_mali_t86x, },
3009 { PRODUCT_ID_MASK_OLD, PRODUCT_ID_TFRX, hardware_counters_mali_t88x, },
3010 { PRODUCT_ID_MASK_NEW, PRODUCT_ID_TMIX, hardware_counters_mali_tMIx, },
3011 { PRODUCT_ID_MASK_NEW, PRODUCT_ID_THEX, hardware_counters_mali_tHEx, },
3012 { PRODUCT_ID_MASK_NEW, PRODUCT_ID_TSIX, hardware_counters_mali_tSIx, },
3013 };
3014
3015 enum { NUM_PRODUCTS = sizeof(products) / sizeof(products[0]) };
3016} // namespace mali_userspace
3017#endif /* ARM_COMPUTE_TEST_HWC_NAMES */