Gian Marco Iodice | ab18212 | 2017-10-09 15:05:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017 ARM Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "arm_compute/runtime/NEON/functions/NEGEMMLowpMatrixMultiplyCore.h" |
| 25 | |
| 26 | #include "arm_compute/core/Error.h" |
| 27 | #include "arm_compute/core/Helpers.h" |
| 28 | #include "arm_compute/core/ITensor.h" |
| 29 | #include "arm_compute/core/NEON/kernels/NEGEMMInterleave4x4Kernel.h" |
| 30 | #include "arm_compute/core/NEON/kernels/NEGEMMInterleaveBlockedKernel.h" |
| 31 | #include "arm_compute/core/NEON/kernels/NEGEMMLowpAssemblyBaseKernel.h" |
| 32 | #include "arm_compute/core/NEON/kernels/NEGEMMLowpMatrixMultiplyKernel.h" |
| 33 | #include "arm_compute/core/NEON/kernels/NEGEMMTranspose1xWKernel.h" |
| 34 | #include "arm_compute/core/NEON/kernels/arm64/NEGEMMLowpAArch64V8P4Kernel.h" |
| 35 | #include "arm_compute/core/TensorInfo.h" |
| 36 | #include "arm_compute/core/Types.h" |
| 37 | #include "arm_compute/core/Validate.h" |
| 38 | #include "arm_compute/runtime/NEON/NEScheduler.h" |
| 39 | #include "arm_compute/runtime/TensorAllocator.h" |
| 40 | #include "support/ToolchainSupport.h" |
| 41 | |
| 42 | using namespace arm_compute; |
| 43 | |
| 44 | NEGEMMLowpMatrixMultiplyCore::NEGEMMLowpMatrixMultiplyCore(std::shared_ptr<IMemoryManager> memory_manager) |
| 45 | : _memory_group(std::move(memory_manager)), _mm_kernel(nullptr), _mtx_a_reshape_kernel(nullptr), _mtx_b_reshape_kernel(nullptr), _tmp_a(), _tmp_b() |
| 46 | { |
| 47 | } |
| 48 | |
| 49 | void NEGEMMLowpMatrixMultiplyCore::configure(const ITensor *a, const ITensor *b, ITensor *output) |
| 50 | { |
| 51 | ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(a, 1, DataType::U8); |
| 52 | ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(output, 1, DataType::S32); |
| 53 | ARM_COMPUTE_ERROR_ON_MISMATCHING_DATA_TYPES(a, b); |
| 54 | ARM_COMPUTE_ERROR_ON_MSG((a)->info()->dimension(0) != (b)->info()->dimension(1), "The product AB is defined only if the number of columns in A is equal to the number of rows in B"); |
| 55 | ARM_COMPUTE_ERROR_ON_MSG((a)->info()->dimension(1) != (output)->info()->dimension(1), "The output matrix must have the same number of rows as the matrix A"); |
| 56 | ARM_COMPUTE_ERROR_ON_MSG((b)->info()->dimension(0) != (output)->info()->dimension(0), "The output matrix must have the same number of columns as the matrix B"); |
| 57 | |
| 58 | #ifdef ARM_COMPUTE_AARCH64_V8_2 |
| 59 | // Check for DOT product instruction |
| 60 | const struct CPUInfo ci = NEScheduler::get().cpu_info(); |
| 61 | const int cpu_has_dotprod = static_cast<int>(ci.CPU) & static_cast<int>(CPUTarget::DOT); |
| 62 | |
| 63 | if(cpu_has_dotprod != 0) |
| 64 | { |
| 65 | TensorShape shape_a_int = a->info()->tensor_shape(); |
| 66 | shape_a_int.set(0, a->info()->dimension(0) * 8.f); |
| 67 | shape_a_int.set(1, std::ceil(a->info()->dimension(1) / 8.f)); |
| 68 | |
| 69 | TensorShape shape_b_int = b->info()->tensor_shape(); |
| 70 | shape_b_int.set(0, b->info()->dimension(0) * 12.f); |
| 71 | shape_b_int.set(1, std::ceil(b->info()->dimension(1) / 12.f)); |
| 72 | |
| 73 | TensorInfo info_a_int(shape_a_int, 1, a->info()->data_type()); |
| 74 | TensorInfo info_b_int(shape_b_int, 1, b->info()->data_type()); |
| 75 | _tmp_a.allocator()->init(info_a_int); |
| 76 | _tmp_b.allocator()->init(info_b_int); |
| 77 | _memory_group.manage(&_tmp_a); |
| 78 | _memory_group.manage(&_tmp_b); |
| 79 | |
| 80 | // Configure interleave blocked kernel for matrix A |
| 81 | { |
| 82 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMInterleaveBlockedKernel>(); |
| 83 | k->configure(a, &_tmp_a, 8, 4, false); |
| 84 | _mtx_a_reshape_kernel = std::move(k); |
| 85 | } |
| 86 | |
| 87 | // Configure interleave blocked kernel for matrix B |
| 88 | { |
| 89 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMInterleaveBlockedKernel>(); |
| 90 | k->configure(b, &_tmp_b, 12, 4, true); |
| 91 | _mtx_b_reshape_kernel = std::move(k); |
| 92 | } |
| 93 | |
| 94 | // Configure matrix multiply kernel |
| 95 | { |
| 96 | // NEGEMMLowpAArch64V8P4Kernel only compiled in AArch64 targets |
| 97 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMLowpAArch64V8P4Kernel>(); |
| 98 | k->configure(&_tmp_a, &_tmp_b, output); |
| 99 | _mm_kernel = std::move(k); |
| 100 | } |
| 101 | } |
| 102 | else |
| 103 | #endif /* ARM_COMPUTE_AARCH64_V8_2 */ |
| 104 | { |
| 105 | // The interleaved output matrix will have the following shape: [ a_height * 4, ceil(a_width / 4.0f) ] |
| 106 | TensorShape shape_tmp_a = a->info()->tensor_shape(); |
| 107 | shape_tmp_a.set(0, a->info()->dimension(0) * 4); |
| 108 | shape_tmp_a.set(1, std::ceil(a->info()->dimension(1) / 4.f)); |
| 109 | |
| 110 | // The transpose1xW output matrix will have the following shape: [ b_height * 16, ceil(b_width / 16.0f) ] |
| 111 | TensorShape shape_tmp_b = b->info()->tensor_shape(); |
| 112 | shape_tmp_b.set(0, b->info()->dimension(1) * 16); |
| 113 | shape_tmp_b.set(1, std::ceil(b->info()->dimension(0) / 16.f)); |
| 114 | |
| 115 | TensorInfo info_a(shape_tmp_a, 1, a->info()->data_type()); |
| 116 | TensorInfo info_b(shape_tmp_b, 1, b->info()->data_type()); |
| 117 | _tmp_a.allocator()->init(info_a); |
| 118 | _tmp_b.allocator()->init(info_b); |
| 119 | _memory_group.manage(&_tmp_a); |
| 120 | _memory_group.manage(&_tmp_b); |
| 121 | |
| 122 | // Configure interleave kernel |
| 123 | { |
| 124 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMInterleave4x4Kernel>(); |
| 125 | k->configure(a, &_tmp_a); |
| 126 | _mtx_a_reshape_kernel = std::move(k); |
| 127 | } |
| 128 | |
| 129 | // Configure transpose kernel |
| 130 | { |
| 131 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMTranspose1xWKernel>(); |
| 132 | k->configure(b, &_tmp_b); |
| 133 | _mtx_b_reshape_kernel = std::move(k); |
| 134 | } |
| 135 | |
| 136 | // Configure matrix multiply kernel |
| 137 | { |
| 138 | auto k = arm_compute::support::cpp14::make_unique<NEGEMMLowpMatrixMultiplyKernel>(); |
| 139 | k->configure(&_tmp_a, &_tmp_b, output); |
| 140 | _mm_kernel = std::move(k); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | // Allocate tensors |
| 145 | _tmp_a.allocator()->allocate(); |
| 146 | _tmp_b.allocator()->allocate(); |
| 147 | } |
| 148 | |
| 149 | void NEGEMMLowpMatrixMultiplyCore::run() |
| 150 | { |
| 151 | _memory_group.acquire(); |
| 152 | |
| 153 | // Run reshape matrix A |
| 154 | NEScheduler::get().schedule(_mtx_a_reshape_kernel.get(), Window::DimY); |
| 155 | |
| 156 | // Run reshape matrix B |
| 157 | NEScheduler::get().schedule(_mtx_b_reshape_kernel.get(), Window::DimY); |
| 158 | |
| 159 | // Run matrix multiply kernel |
| 160 | NEScheduler::get().schedule(_mm_kernel.get(), Window::DimY); |
| 161 | |
| 162 | _memory_group.release(); |
| 163 | } |