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SiCong Lif44bbc52022-08-29 18:25:51 +01001/*
SiCong Li5a63d1e2023-01-06 16:28:57 +00002 * Copyright (c) 2022-2023 Arm Limited.
SiCong Lif44bbc52022-08-29 18:25:51 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24#include "ClComponentDirectConv2d.h"
25
26#include "arm_compute/core/Validate.h"
27#include "arm_compute/core/utils/misc/ShapeCalculator.h"
SiCong Li5a63d1e2023-01-06 16:28:57 +000028#include "arm_compute/dynamic_fusion/sketch/attributes/Conv2dAttributes.h"
SiCong Lif44bbc52022-08-29 18:25:51 +010029#include "src/core/CL/CLValidate.h"
30#include "src/dynamic_fusion/sketch/gpu/template_writer/cl/ClTemplateDirectConv2d.h"
31
32namespace arm_compute
33{
34namespace experimental
35{
36namespace dynamic_fusion
37{
Gunes Bayir7dc02342022-11-21 21:46:50 +000038bool ClComponentDirectConv2dSettings::export_to_cl_image() const
SiCong Lif44bbc52022-08-29 18:25:51 +010039{
Viet-Hoa Doe2e6d742023-03-01 15:46:10 +000040 return _desc.export_weights_to_cl_image;
SiCong Lif44bbc52022-08-29 18:25:51 +010041}
42
Gunes Bayir7dc02342022-11-21 21:46:50 +000043ClComponentDirectConv2dSettings &ClComponentDirectConv2dSettings::fast_relaxed_math(bool fast_relaxed_math)
SiCong Lif44bbc52022-08-29 18:25:51 +010044{
45 _fast_relaxed_math = fast_relaxed_math;
46 return *this;
47}
48
Gunes Bayir7dc02342022-11-21 21:46:50 +000049bool ClComponentDirectConv2dSettings::fast_relaxed_math() const
SiCong Lif44bbc52022-08-29 18:25:51 +010050{
51 return _fast_relaxed_math;
52}
53
Ramy Elgammaldf6a3b02022-11-30 16:23:10 +000054ClComponentDirectConv2dSettings &ClComponentDirectConv2dSettings::direct_conv_descriptor(const DirectConvComputeKernelInfo &desc)
55{
56 _desc = desc;
57 return *this;
58}
59
60DirectConvComputeKernelInfo ClComponentDirectConv2dSettings::direct_conv_descriptor() const
61{
62 return _desc;
63}
64
SiCong Lif44bbc52022-08-29 18:25:51 +010065Status ClComponentDirectConv2d::validate(
66 const Properties &properties,
67 const ArgumentPack<ITensorInfo> &tensors,
68 const Attributes &attributes,
69 const Settings &settings)
70{
Ramy Elgammaldf6a3b02022-11-30 16:23:10 +000071 ARM_COMPUTE_UNUSED(properties);
SiCong Lif44bbc52022-08-29 18:25:51 +010072 const auto src = tensors.get_const_tensor(TensorType::ACL_SRC_0);
73 const auto wei = tensors.get_const_tensor(TensorType::ACL_SRC_1);
74 const auto bia = tensors.get_const_tensor(TensorType::ACL_SRC_2);
75 const auto dst = tensors.get_const_tensor(TensorType::ACL_DST_0);
76
77 ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, wei, dst);
78
79 // 1. Check validity
80 // Matching data type
81 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, wei);
82 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
83 if(bia != nullptr)
84 {
85 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, bia);
86 }
87
88 // Matching data layout
89 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, wei);
90 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, dst);
91 if(bia != nullptr)
92 {
93 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, bia);
94 }
95
96 // All tensor infos are initialized
97 ARM_COMPUTE_RETURN_ERROR_ON(src->tensor_shape().total_size() == 0);
98 ARM_COMPUTE_RETURN_ERROR_ON(wei->tensor_shape().total_size() == 0);
99 ARM_COMPUTE_RETURN_ERROR_ON(dst->tensor_shape().total_size() == 0);
100 if(bia != nullptr)
101 {
102 ARM_COMPUTE_RETURN_ERROR_ON(bia->tensor_shape().total_size() == 0);
103 }
104 // Device requirements are met
105 ARM_COMPUTE_RETURN_ERROR_ON_F16_UNSUPPORTED(src);
106 // wei shape is correct
107 const DataLayout data_layout = src->data_layout();
108 const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL);
109 ARM_COMPUTE_RETURN_ERROR_ON_MSG(wei->dimension(channel_idx) != src->dimension(channel_idx), "Weights feature map dimension should match the respective src's one");
110 ARM_COMPUTE_RETURN_ERROR_ON_MSG(wei->num_dimensions() > 4, "Weights can be at most 4 dimensional");
111
112 // dst shape is correct
113 PadStrideInfo legacy_pad_stride(attributes.stride().x(), attributes.stride().y(), attributes.pad().left, attributes.pad().right, attributes.pad().top,
114 attributes.pad().bottom, DimensionRoundingType{});
115 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(dst->tensor_shape(),
116 misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, legacy_pad_stride));
117
118 // bia shape is correct
119 if(bia != nullptr)
120 {
121 ARM_COMPUTE_RETURN_ERROR_ON_MSG(bia->dimension(0) != wei->dimension(3),
122 "Biases size and number of dst feature maps should match");
123 ARM_COMPUTE_RETURN_ERROR_ON_MSG(bia->num_dimensions() > 1,
124 "Biases should be one dimensional");
125 }
126
127 // 2. Check support level
128 // Data type
129 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::F16, DataType::F32);
130 // Data layout
131 ARM_COMPUTE_RETURN_ERROR_ON_DATA_LAYOUT_NOT_IN(src, DataLayout::NHWC);
132
Ramy Elgammaldf6a3b02022-11-30 16:23:10 +0000133 const auto desc = settings.direct_conv_descriptor();
134 ARM_COMPUTE_RETURN_ERROR_ON_MSG(desc.n0 != 1 && desc.n0 != 2 && desc.n0 != 3 && desc.n0 != 4 && desc.n0 != 8 && desc.n0 != 16,
135 "N0 can only be: 1, 2, 3, 4, 8, and 16");
136 ARM_COMPUTE_RETURN_ERROR_ON_MSG(desc.k0 != 1 && desc.k0 != 2 && desc.k0 != 3 && desc.k0 != 4 && desc.k0 != 8 && desc.k0 != 16,
137 "K0 can only be: 1, 2, 3, 4, 8, and 16");
SiCong Lif44bbc52022-08-29 18:25:51 +0100138 return Status{};
139}
140
141ClComponentDirectConv2d::ClComponentDirectConv2d(
142 ComponentId id,
143 const Properties &properties,
144 const ArgumentPack<ITensorInfo> &tensors,
145 const Attributes &attributes,
146 const Settings &settings)
147 : IGpuKernelComponent{ id, properties, tensors },
148 _component_writer{ std::make_unique<ClTemplateDirectConv2d>(id, tensors, attributes, settings) }
149{
150}
151ClComponentDirectConv2d::~ClComponentDirectConv2d()
152{
153}
154const IGpuTemplateComponentWriter *ClComponentDirectConv2d::template_writer() const
155{
156 return _component_writer.get();
157}
158} // namespace dynamic_fusion
159} // namespace experimental
160} // namespace arm_compute