Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 1 | /* |
Gian Marco Iodice | 3cce35d | 2022-12-30 16:07:45 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2023 Arm Limited. |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 24 | #ifndef ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H |
| 25 | #define ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 26 | |
SiCong Li | 9129549 | 2023-07-21 18:16:13 +0100 | [diff] [blame] | 27 | #include "arm_compute/function_info/ActivationLayerInfo.h" |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 28 | #include "src/core/common/Macros.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 29 | #include "src/gpu/cl/ClCompileContext.h" |
| 30 | #include "src/gpu/cl/IClKernel.h" |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 31 | |
| 32 | namespace arm_compute |
| 33 | { |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 34 | // Forward declaration |
| 35 | struct DirectConvComputeKernelInfo; |
| 36 | |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 37 | namespace opencl |
| 38 | { |
| 39 | namespace kernels |
| 40 | { |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 41 | /** Interface for the direct convolution kernel. */ |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 42 | class ClDirectConv2dKernel : public IClKernel |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 43 | { |
| 44 | public: |
Giorgio Arena | 4a95bba | 2021-06-28 11:00:27 +0100 | [diff] [blame] | 45 | ClDirectConv2dKernel(); |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 46 | ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(ClDirectConv2dKernel); |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 47 | /** Set the src, weights, biases and dst tensors info. |
| 48 | * |
Giorgio Arena | 945ae9e | 2021-10-13 11:13:04 +0100 | [diff] [blame] | 49 | * @note: Due to set_valid_region() in NCHW, src/weights/biases cannot be const. Need to change this once the set_valid_region() is removed. |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 50 | * |
Giorgio Arena | 945ae9e | 2021-10-13 11:13:04 +0100 | [diff] [blame] | 51 | * @note: DirectConvolution only works in the following configurations for the NCHW data layout: |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 52 | * 1x1 convolution with stride_x = 1/2/3, stride_y = 1/2/3 |
| 53 | * 3x3 convolution with stride_x = 1/2, stride_y = 1/2 |
| 54 | * 5x5 convolution with stride_x = 1/2, stride_y = 1/2 |
| 55 | * 9x9 convolution with stride_x = 1/2, stride_y = 1/2 |
| 56 | * |
| 57 | * @param[in] compile_context The compile context to be used. |
| 58 | * @param[in] src The src tensor info to convolve. 3 lower dimensions represent a single src [width, height, IFM], |
| 59 | * while every optional dimension from 4 and above represent a batch of inputs. Data types supported: QASYMM8_SIGNED/QASYMM8/F16/F32. |
| 60 | * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. |
| 61 | * The 3rd dimension must be the same as the src's volume 3rd dimension. |
| 62 | * Data type supported:Same as @p src. |
| 63 | * @param[in] biases Biases tensor info. Biases are 1D tensor with dimension [OFM]. |
| 64 | * Data type supported: Should match @p src data type, except for src of QASYMM8 and QASYMM8_SIGNED type where biases should be of S32 type |
| 65 | * @param[out] dst Output tensor info. |
| 66 | * The 3rd dimensions must be equal to the 4th dimension of the @p kernels tensor. Data types supported: Same as @p src. |
| 67 | * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo. |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 68 | * @param[in] act_info Contains activaton information described in @ref ActivationLayerInfo. |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 69 | * @param[in] desc Direct convolution descriptor used to build the NHWC direct convolution kernel. For NCHW, this parameter is ignored. |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 70 | */ |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 71 | void configure(const CLCompileContext &compile_context, ITensorInfo *src, ITensorInfo *weights, ITensorInfo *biases, ITensorInfo *dst, |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 72 | const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc); |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 73 | /** Static function to check if given info will lead to a valid configuration |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 74 | * |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 75 | * Similar to ClDirectConv2dKernel::configure() |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 76 | * |
| 77 | * @return a status |
| 78 | */ |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 79 | static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 80 | const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc); |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 81 | |
| 82 | // Inherited methods overridden: |
| 83 | void run_op(ITensorPack &tensors, const Window &window, cl::CommandQueue &queue) override; |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 84 | |
| 85 | public: |
| 86 | DataLayout _data_layout{}; |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 87 | PadStrideInfo _conv_info{}; |
Gian Marco Iodice | 3cce35d | 2022-12-30 16:07:45 +0000 | [diff] [blame] | 88 | bool _export_weights_to_cl_image{ false }; |
| 89 | bool _export_output_to_cl_image{ false }; |
| 90 | bool _export_input_to_cl_image{ false }; |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 91 | }; |
| 92 | } // namespace kernels |
| 93 | } // namespace opencl |
| 94 | } // namespace arm_compute |
Georgios Pinitas | 2eb5d16 | 2021-07-02 09:01:49 +0100 | [diff] [blame] | 95 | #endif /* ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H */ |