Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 1 | /* |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 2 | * Copyright (c) 2021-2022 Arm Limited. |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 24 | #include "src/gpu/cl/operators/ClDirectConv2d.h" |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 25 | |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 26 | #include "arm_compute/core/KernelDescriptors.h" |
| 27 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 28 | #include "arm_compute/runtime/CL/CLScheduler.h" |
| 29 | #include "src/core/CL/kernels/CLFillBorderKernel.h" |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 30 | #include "src/core/helpers/AutoConfiguration.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 31 | #include "src/gpu/cl/kernels/ClActivationKernel.h" |
| 32 | #include "src/gpu/cl/kernels/ClDirectConv2dKernel.h" |
Ramy Elgammal | df6a3b0 | 2022-11-30 16:23:10 +0000 | [diff] [blame] | 33 | #include "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigBifrost.h" |
| 34 | #include "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigValhall.h" |
| 35 | #include "src/runtime/heuristics/direct_conv/ClDirectConvKernelConfig.h" |
| 36 | #include "src/runtime/heuristics/direct_conv/IClDirectConvKernelConfig.h" |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 37 | |
ramelg01 | 2e53f17 | 2021-09-22 10:48:25 +0100 | [diff] [blame] | 38 | #include "src/common/utils/Log.h" |
| 39 | |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 40 | using namespace arm_compute::cl_direct_conv; |
| 41 | |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 42 | namespace arm_compute |
| 43 | { |
| 44 | namespace opencl |
| 45 | { |
| 46 | namespace |
| 47 | { |
| 48 | ITensorPack select_activation_src_dst(ITensorPack &tensors) |
| 49 | { |
| 50 | ITensorPack pack; |
| 51 | pack.add_tensor(TensorType::ACL_SRC, tensors.get_tensor(TensorType::ACL_DST)); |
| 52 | pack.add_tensor(TensorType::ACL_DST, tensors.get_tensor(TensorType::ACL_DST)); |
| 53 | return pack; |
| 54 | } |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 55 | |
| 56 | DirectConvComputeKernelInfo config_direct_convolution_nhwc(const ITensorInfo *src, const ITensorInfo *weights, const PadStrideInfo &conv_info) |
| 57 | { |
| 58 | // Get GPU target |
| 59 | GPUTarget gpu_target = CLScheduler::get().target(); |
| 60 | |
| 61 | std::unique_ptr<IClDirectConvKernelConfig> t = ClDirectConvKernelConfigurationFactory::create(gpu_target); |
| 62 | |
| 63 | return t->configure(src, weights, conv_info); |
| 64 | } |
| 65 | |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 66 | } // namespace |
| 67 | |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 68 | void ClDirectConv2d::configure(const CLCompileContext &compile_context, ITensorInfo *src, ITensorInfo *weights, ITensorInfo *biases, ITensorInfo *dst, |
| 69 | const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info) |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 70 | { |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 71 | ARM_COMPUTE_ERROR_ON_NULLPTR(src); |
ramelg01 | 2e53f17 | 2021-09-22 10:48:25 +0100 | [diff] [blame] | 72 | ARM_COMPUTE_LOG_PARAMS(src, weights, biases, dst, conv_info, act_info); |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 73 | |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 74 | // Initialize the direct convolution descriptor |
| 75 | const DirectConvComputeKernelInfo desc = config_direct_convolution_nhwc(src, weights, conv_info); |
| 76 | |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 77 | // Configure direct convolution kernel |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 78 | const ActivationLayerInfo conv2d_act_info = (src->data_layout() == DataLayout::NHWC && is_data_type_float(src->data_type())) ? act_info : ActivationLayerInfo(); |
| 79 | auto k = std::make_unique<kernels::ClDirectConv2dKernel>(); |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 80 | k->set_target(CLScheduler::get().target()); |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 81 | k->configure(compile_context, src, weights, biases, dst, conv_info, conv2d_act_info, desc); |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 82 | _direct_conv_kernel = std::move(k); |
| 83 | |
| 84 | // Configure border handler |
| 85 | PixelValue zero_value(0.f); |
| 86 | if(is_data_type_quantized_asymmetric(src->data_type())) |
| 87 | { |
| 88 | zero_value = PixelValue(0, src->data_type(), src->quantization_info()); |
| 89 | } |
| 90 | auto b = std::make_unique<CLFillBorderKernel>(); |
| 91 | b->configure(compile_context, src, _direct_conv_kernel->border_size(), BorderMode::CONSTANT, zero_value); |
| 92 | _src_border_handler = std::move(b); |
| 93 | |
Georgios Pinitas | 9fc3be6 | 2021-05-29 04:01:51 +0100 | [diff] [blame] | 94 | // Fused activation is currently supported for NHWC and floating point types |
| 95 | if(act_info.enabled() && !conv2d_act_info.enabled()) |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 96 | { |
| 97 | auto a = std::make_unique<kernels::ClActivationKernel>(); |
| 98 | a->configure(compile_context, dst, dst, act_info); |
| 99 | _activation_kernel = std::move(a); |
| 100 | } |
| 101 | |
| 102 | // Tune kernels |
| 103 | CLScheduler::get().tune_kernel_static(*_direct_conv_kernel); |
| 104 | } |
| 105 | |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 106 | Status ClDirectConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, |
| 107 | const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info) |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 108 | { |
Gian Marco Iodice | 2cc50b3 | 2022-05-30 14:41:49 +0100 | [diff] [blame] | 109 | // Initialize the direct convolution descriptor |
| 110 | const DirectConvComputeKernelInfo desc = config_direct_convolution_nhwc(src, weights, conv_info); |
| 111 | |
| 112 | ARM_COMPUTE_RETURN_ON_ERROR(kernels::ClDirectConv2dKernel::validate(src, weights, biases, dst, conv_info, ActivationLayerInfo(), desc)); |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 113 | if(act_info.enabled()) |
| 114 | { |
| 115 | ARM_COMPUTE_RETURN_ON_ERROR(kernels::ClActivationKernel::validate(dst, dst, act_info)); |
| 116 | } |
| 117 | return Status{}; |
| 118 | } |
| 119 | |
Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 120 | void ClDirectConv2d::run(ITensorPack &tensors) |
Sheri Zhang | 1efed92 | 2021-03-10 22:43:38 +0000 | [diff] [blame] | 121 | { |
| 122 | // Run border handler |
| 123 | CLScheduler::get().enqueue_op(*_src_border_handler.get(), tensors, false); |
| 124 | // Run direct convolution |
| 125 | CLScheduler::get().enqueue_op(*_direct_conv_kernel.get(), tensors, false); |
| 126 | // Run activation kernel |
| 127 | if(_activation_kernel) |
| 128 | { |
| 129 | auto act_pack = select_activation_src_dst(tensors); |
| 130 | CLScheduler::get().enqueue_op(*_activation_kernel.get(), act_pack, false); |
| 131 | } |
| 132 | } |
| 133 | } // namespace opencl |
| 134 | } // namespace arm_compute |