Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "src/runtime/cpu/operators/CpuGemmDirectConv2d.h" |
| 25 | |
| 26 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
| 27 | #include "arm_compute/core/utils/quantization/AsymmHelpers.h" |
| 28 | #include "arm_compute/runtime/FunctionDescriptors.h" |
| 29 | #include "arm_compute/runtime/NEON/NEScheduler.h" |
| 30 | #include "src/runtime/cpu/operators/CpuActivation.h" |
| 31 | #include "src/runtime/cpu/operators/CpuPermute.h" |
| 32 | #include "src/runtime/cpu/operators/internal/CpuGemmAssemblyDispatch.h" |
| 33 | |
| 34 | #include <set> |
| 35 | |
| 36 | namespace arm_compute |
| 37 | { |
| 38 | namespace cpu |
| 39 | { |
| 40 | namespace |
| 41 | { |
| 42 | GEMMLowpOutputStageInfo calculate_output_stage_metadata(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *dst, const ActivationLayerInfo &act) |
| 43 | { |
| 44 | // Since we need negative offsets for computing convolution, we need to change QuantizationInfo() |
| 45 | // Extract and negate input and weights offset |
| 46 | const QuantizationInfo iqinfo = src->quantization_info(); |
| 47 | const QuantizationInfo wqinfo = weights->quantization_info(); |
| 48 | const QuantizationInfo oqinfo = (dst->total_size() == 0) ? iqinfo : dst->quantization_info(); |
| 49 | const UniformQuantizationInfo uoqinfo = oqinfo.uniform(); |
| 50 | const DataType data_type = src->data_type(); |
| 51 | // Merge activation with output stage |
| 52 | const std::set<ActivationLayerInfo::ActivationFunction> supported_acts = { ActivationLayerInfo::ActivationFunction::RELU, |
| 53 | ActivationLayerInfo::ActivationFunction::BOUNDED_RELU, |
| 54 | ActivationLayerInfo::ActivationFunction::LU_BOUNDED_RELU |
| 55 | }; |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 56 | |
| 57 | PixelValue type_min{}; |
| 58 | PixelValue type_max{}; |
| 59 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 60 | std::tie(type_min, type_max) = get_min_max(data_type); |
| 61 | int32_t min_activation = type_min.get<int32_t>(); |
| 62 | int32_t max_activation = type_max.get<int32_t>(); |
| 63 | if(supported_acts.count(act.activation()) != 0) |
| 64 | { |
| 65 | std::tie(min_activation, max_activation) = get_quantized_activation_min_max(act, data_type, uoqinfo); |
| 66 | } |
| 67 | GEMMLowpOutputStageInfo os_info; |
| 68 | os_info.type = GEMMLowpOutputStageType::QUANTIZE_DOWN_FIXEDPOINT; |
| 69 | os_info.gemmlowp_offset = uoqinfo.offset; |
| 70 | os_info.gemmlowp_min_bound = min_activation; |
| 71 | os_info.gemmlowp_max_bound = max_activation; |
| 72 | os_info.is_quantized_per_channel = (weights->data_type() == DataType::QSYMM8_PER_CHANNEL); |
| 73 | quantization::calculate_quantized_multipliers(iqinfo, wqinfo, oqinfo, os_info); |
| 74 | return os_info; |
| 75 | } |
| 76 | cpu::AsmGemmInfo init_assembly_metadata(const Conv2dInfo &info, bool is_indirect) |
| 77 | { |
| 78 | cpu::AsmGemmInfo asm_info; |
| 79 | asm_info.method = is_indirect ? cpu::AsmConvMethod::Indirect : cpu::AsmConvMethod::Conv; |
| 80 | asm_info.ps_info = info.conv_info; |
| 81 | asm_info.activation_info = info.act_info; |
| 82 | asm_info.depth_output_gemm3d = true; |
| 83 | asm_info.reinterpret_input_as_3d = true; |
| 84 | asm_info.padding_top = info.conv_info.pad_top(); |
| 85 | asm_info.padding_left = info.conv_info.pad_left(); |
| 86 | asm_info.padding_value = 0.f; |
| 87 | asm_info.negated_offsets = false; |
| 88 | return asm_info; |
| 89 | } |
| 90 | } // namespace |
| 91 | |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 92 | CpuGemmDirectConv2d::CpuGemmDirectConv2d() |
| 93 | : _gemm_asm_func(std::make_unique<CpuGemmAssemblyDispatch>()), |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 94 | _activation_func(std::make_unique<CpuActivation>()), |
| 95 | _weights_permute_func(std::make_unique<CpuPermute>()), |
| 96 | _permuted_weights_info(), |
| 97 | _permuted_weights(std::make_unique<Tensor>()) |
| 98 | { |
| 99 | } |
| 100 | |
| 101 | CpuGemmDirectConv2d::~CpuGemmDirectConv2d() = default; |
| 102 | |
| 103 | void CpuGemmDirectConv2d::configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const Conv2dInfo &info) |
| 104 | { |
| 105 | ARM_COMPUTE_ERROR_ON_NULLPTR(src, weights, dst); |
| 106 | ARM_COMPUTE_ERROR_THROW_ON(CpuGemmDirectConv2d::validate(src, |
| 107 | weights, |
| 108 | biases != nullptr ? biases : nullptr, |
| 109 | dst, |
| 110 | info)); |
| 111 | _original_weights_info = weights; |
| 112 | _weights_permute_func->configure(weights, &_permuted_weights_info, PermutationVector{ 3, 0, 1, 2 }); |
| 113 | |
| 114 | // Configure assembly dispatch |
| 115 | cpu::AsmGemmInfo asm_info = init_assembly_metadata(info, false); |
| 116 | if(is_data_type_quantized(src->data_type())) |
| 117 | { |
| 118 | asm_info.output_stage = calculate_output_stage_metadata(src, weights, dst, info.act_info); |
| 119 | } |
| 120 | _gemm_asm_func->configure(src, &_permuted_weights_info, biases, dst, asm_info); |
| 121 | |
| 122 | // Configure activation |
| 123 | if(info.act_info.enabled() && !_gemm_asm_func->is_activation_supported(info.act_info)) |
| 124 | { |
| 125 | _activation_func->configure(dst, nullptr, info.act_info); |
| 126 | _run_activation = true; |
| 127 | } |
| 128 | } |
| 129 | Status CpuGemmDirectConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const Conv2dInfo &info) |
| 130 | { |
| 131 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, weights, dst); |
| 132 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::BFLOAT16, DataType::F16, DataType::F32); |
| 133 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(weights, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM8_PER_CHANNEL, DataType::BFLOAT16, DataType::F16, DataType::F32); |
| 134 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, weights); |
| 135 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.num_groups > 1, "Grouping (num_groups != 1) is not supported on Neon"); |
| 136 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src->data_layout() != DataLayout::NHWC, "Data layout supported is NHWC"); |
| 137 | const DataType data_type = src->data_type(); |
| 138 | const TensorShape i_shape = src->tensor_shape(); |
| 139 | const TensorShape w_shape = weights->tensor_shape(); |
| 140 | ARM_COMPUTE_RETURN_ERROR_ON(w_shape[0] != i_shape[0]); |
| 141 | ARM_COMPUTE_RETURN_ERROR_ON(info.dilation != Size2D(1U, 1U)); |
| 142 | ARM_COMPUTE_RETURN_ERROR_ON(weights->num_dimensions() > 4); |
| 143 | // Validate biases |
| 144 | if(biases != nullptr) |
| 145 | { |
| 146 | if(is_data_type_quantized_asymmetric(data_type)) |
| 147 | { |
| 148 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(biases, 1, DataType::S32); |
| 149 | } |
| 150 | else if(data_type == DataType::BFLOAT16) |
| 151 | { |
| 152 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(biases, 1, DataType::F32); |
| 153 | } |
| 154 | else |
| 155 | { |
| 156 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, biases); |
| 157 | } |
| 158 | ARM_COMPUTE_RETURN_ERROR_ON(biases->dimension(0) != weights->dimension(3)); |
| 159 | ARM_COMPUTE_RETURN_ERROR_ON(biases->num_dimensions() > 1); |
| 160 | } |
| 161 | |
| 162 | cpu::AsmGemmInfo asm_info = init_assembly_metadata(info, false); |
| 163 | ARM_COMPUTE_RETURN_ON_ERROR(cpu::CpuGemmAssemblyDispatch::validate(src, weights, biases, dst, asm_info)); |
| 164 | return Status{}; |
| 165 | } |
| 166 | void CpuGemmDirectConv2d::run(ITensorPack &tensors) |
| 167 | { |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 168 | import_workspace_memory(tensors); |
| 169 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 170 | prepare(tensors); |
| 171 | |
| 172 | _gemm_asm_func->run(tensors); |
| 173 | if(_run_activation) |
| 174 | { |
| 175 | _activation_func->run(tensors); |
| 176 | } |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 177 | |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 178 | free_imported_workspace_memory(); |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | void CpuGemmDirectConv2d::prepare(ITensorPack &tensors) |
| 182 | { |
| 183 | if(!_is_prepared) |
| 184 | { |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 185 | ITensorPack permute_tensors |
| 186 | { |
| 187 | { TensorType::ACL_SRC, tensors.get_const_tensor(TensorType::ACL_SRC_1) }, |
| 188 | { TensorType::ACL_DST, _permuted_weights.get() }, |
| 189 | }; |
| 190 | |
| 191 | _weights_permute_func->run(permute_tensors); |
| 192 | |
| 193 | tensors.get_const_tensor(TensorType::ACL_SRC_1)->mark_as_unused(); |
| 194 | |
| 195 | // switch the original tensor with permuted tensor |
| 196 | tensors.add_const_tensor(TensorType::ACL_SRC_1, _permuted_weights.get()); |
| 197 | _is_prepared = true; |
| 198 | } |
| 199 | } |
| 200 | |
Sang-Hoon Park | b3be457 | 2021-05-18 10:46:00 +0100 | [diff] [blame] | 201 | experimental::MemoryRequirements CpuGemmDirectConv2d::workspace() const |
| 202 | { |
| 203 | experimental::MemoryRequirements req = _gemm_asm_func->workspace(); |
| 204 | |
| 205 | auto index = static_cast<std::underlying_type<TensorType>::type>(TensorType::ACL_INT_0); |
| 206 | |
| 207 | if(req.size() > 0) |
| 208 | { |
| 209 | index = req.back().slot + 1; |
| 210 | |
| 211 | constexpr auto max_index = static_cast<std::underlying_type<TensorType>::type>(TensorType::ACL_INT_4); |
| 212 | ARM_COMPUTE_UNUSED(max_index); // in order to prevent build error with assertion is disabled. |
| 213 | ARM_COMPUTE_ERROR_ON(index > max_index); |
| 214 | } |
| 215 | |
| 216 | req.emplace_back(index, _permuted_weights_info.total_size(), 0); |
| 217 | |
| 218 | return req; |
| 219 | } |
| 220 | |
| 221 | void CpuGemmDirectConv2d::import_workspace_memory(ITensorPack &tensors) |
| 222 | { |
| 223 | auto imported_tensor = tensors.get_tensor(workspace().back().slot); |
| 224 | |
| 225 | ARM_COMPUTE_ERROR_ON_NULLPTR(imported_tensor); |
| 226 | |
| 227 | auto imported_memory = imported_tensor->buffer(); |
| 228 | _permuted_weights->allocator()->init(_permuted_weights_info); |
| 229 | _permuted_weights->allocator()->import_memory(imported_memory); |
| 230 | } |
| 231 | |
| 232 | void CpuGemmDirectConv2d::free_imported_workspace_memory() |
| 233 | { |
| 234 | _permuted_weights->allocator()->free(); |
| 235 | } |
| 236 | |
Sang-Hoon Park | d89e2fa | 2021-05-17 17:04:50 +0100 | [diff] [blame] | 237 | } // namespace cpu |
| 238 | } // namespace arm_compute |