Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_DIRECTCONV3D_H |
| 25 | #define ARM_COMPUTE_CPU_DIRECTCONV3D_H |
| 26 | |
| 27 | #include "arm_compute/core/ITensorInfo.h" |
| 28 | #include "arm_compute/core/Types.h" |
| 29 | #include "arm_compute/core/experimental/Types.h" |
| 30 | #include "arm_compute/runtime/FunctionDescriptors.h" |
| 31 | #include "arm_compute/runtime/IMemoryManager.h" |
| 32 | #include "arm_compute/runtime/MemoryGroup.h" |
| 33 | #include "arm_compute/runtime/NEON/functions/NEActivationLayer.h" |
| 34 | #include "arm_compute/runtime/Tensor.h" |
| 35 | #include "src/core/NEON/kernels/NEFillBorderKernel.h" |
| 36 | #include "src/cpu/ICpuKernel.h" |
| 37 | #include "src/cpu/ICpuOperator.h" |
| 38 | #include "src/cpu/kernels/CpuDirectConv3dKernel.h" |
| 39 | #include "src/cpu/operators/CpuActivation.h" |
| 40 | |
| 41 | #include <memory> |
| 42 | |
| 43 | namespace arm_compute |
| 44 | { |
| 45 | namespace cpu |
| 46 | { |
| 47 | /** Function to run the direct convolution. |
| 48 | * |
| 49 | * This function calls the following kernels: |
| 50 | * |
| 51 | * -# @ref kernels::CpuDirectConv3dKernel |
| 52 | */ |
| 53 | class CpuDirectConv3d : public ICpuOperator |
| 54 | { |
| 55 | public: |
| 56 | CpuDirectConv3d(std::shared_ptr<IMemoryManager> memory_manager = nullptr); |
| 57 | ~CpuDirectConv3d(); |
| 58 | /** Set the input, weights, biases and output tensor info. |
| 59 | * |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 60 | * Valid data layouts: |
| 61 | * - NDHWC |
| 62 | * |
| 63 | * Valid data type configurations: |
| 64 | * |src0 |src1 |src2 |dst | |
| 65 | * |:--------------|:------------------|:------|:--------------| |
| 66 | * |F16 |F16 |F16 |F16 | |
| 67 | * |F32 |F32 |F32 |F32 | |
Freddie Liardet | f727ef4 | 2021-10-18 13:28:57 +0100 | [diff] [blame] | 68 | * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | |
| 69 | * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 70 | * |
| 71 | * @param[in, out] src0 Input tensor info. |
| 72 | * @param[in] src1 Set of kernels to convolve the input volume. |
| 73 | * The 2nd dimension must be the same as the src0's volume 1st dimension. |
| 74 | * @param[in] src2 Set of biases. Can be nullptr. |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 75 | * @param[out] dst Output tensor info. |
| 76 | * The 1st dimensions must be equal to the 1st dimension of the @p kernels tensor. |
| 77 | * @param[in] conv_info Contains padding, stride, acitvation information. |
| 78 | */ |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 79 | void configure(ITensorInfo *src0, ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 80 | /** Static function to check if given info will lead to a valid configuration |
| 81 | * |
| 82 | * Similar to CpuDirectConv3d::configure() |
| 83 | * |
| 84 | * @return a status |
| 85 | */ |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 86 | static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 87 | |
| 88 | // Inherited methods overridden: |
| 89 | void run(ITensorPack &tensors) override; |
| 90 | |
| 91 | private: |
| 92 | MemoryGroup _memory_group; |
| 93 | std::unique_ptr<kernels::CpuDirectConv3dKernel> _conv_kernel; |
| 94 | std::unique_ptr<CpuActivation> _activationlayer_function; |
| 95 | Tensor _accumulator; |
| 96 | bool _is_activationlayer_enabled{ false }; |
| 97 | unsigned int _dim_split{ 0 }; |
| 98 | }; |
| 99 | } // namespace cpu |
| 100 | } // namespace arm_compute |
| 101 | #endif /* ARM_COMPUTE_CPU_DIRECTCONV3D_H */ |