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Sheri Zhang1efed922021-03-10 22:43:38 +00001/*
Gian Marco Iodice3cce35d2022-12-30 16:07:45 +00002 * Copyright (c) 2017-2023 Arm Limited.
Sheri Zhang1efed922021-03-10 22:43:38 +00003 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010024#ifndef ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H
25#define ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H
Sheri Zhang1efed922021-03-10 22:43:38 +000026
27#include "src/core/common/Macros.h"
Georgios Pinitas7891a732021-08-20 21:39:25 +010028#include "src/gpu/cl/ClCompileContext.h"
29#include "src/gpu/cl/IClKernel.h"
Sheri Zhang1efed922021-03-10 22:43:38 +000030
31namespace arm_compute
32{
Gian Marco Iodice2cc50b32022-05-30 14:41:49 +010033// Forward declaration
34struct DirectConvComputeKernelInfo;
35
Sheri Zhang1efed922021-03-10 22:43:38 +000036namespace opencl
37{
38namespace kernels
39{
Georgios Pinitas9fc3be62021-05-29 04:01:51 +010040/** Interface for the direct convolution kernel. */
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010041class ClDirectConv2dKernel : public IClKernel
Sheri Zhang1efed922021-03-10 22:43:38 +000042{
43public:
Giorgio Arena4a95bba2021-06-28 11:00:27 +010044 ClDirectConv2dKernel();
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010045 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(ClDirectConv2dKernel);
Sheri Zhang1efed922021-03-10 22:43:38 +000046 /** Set the src, weights, biases and dst tensors info.
47 *
Giorgio Arena945ae9e2021-10-13 11:13:04 +010048 * @note: Due to set_valid_region() in NCHW, src/weights/biases cannot be const. Need to change this once the set_valid_region() is removed.
Sheri Zhang1efed922021-03-10 22:43:38 +000049 *
Giorgio Arena945ae9e2021-10-13 11:13:04 +010050 * @note: DirectConvolution only works in the following configurations for the NCHW data layout:
Sheri Zhang1efed922021-03-10 22:43:38 +000051 * 1x1 convolution with stride_x = 1/2/3, stride_y = 1/2/3
52 * 3x3 convolution with stride_x = 1/2, stride_y = 1/2
53 * 5x5 convolution with stride_x = 1/2, stride_y = 1/2
54 * 9x9 convolution with stride_x = 1/2, stride_y = 1/2
55 *
56 * @param[in] compile_context The compile context to be used.
57 * @param[in] src The src tensor info to convolve. 3 lower dimensions represent a single src [width, height, IFM],
58 * while every optional dimension from 4 and above represent a batch of inputs. Data types supported: QASYMM8_SIGNED/QASYMM8/F16/F32.
59 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM].
60 * The 3rd dimension must be the same as the src's volume 3rd dimension.
61 * Data type supported:Same as @p src.
62 * @param[in] biases Biases tensor info. Biases are 1D tensor with dimension [OFM].
63 * Data type supported: Should match @p src data type, except for src of QASYMM8 and QASYMM8_SIGNED type where biases should be of S32 type
64 * @param[out] dst Output tensor info.
65 * The 3rd dimensions must be equal to the 4th dimension of the @p kernels tensor. Data types supported: Same as @p src.
66 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
Georgios Pinitas9fc3be62021-05-29 04:01:51 +010067 * @param[in] act_info Contains activaton information described in @ref ActivationLayerInfo.
Gian Marco Iodice2cc50b32022-05-30 14:41:49 +010068 * @param[in] desc Direct convolution descriptor used to build the NHWC direct convolution kernel. For NCHW, this parameter is ignored.
Sheri Zhang1efed922021-03-10 22:43:38 +000069 */
Georgios Pinitas9fc3be62021-05-29 04:01:51 +010070 void configure(const CLCompileContext &compile_context, ITensorInfo *src, ITensorInfo *weights, ITensorInfo *biases, ITensorInfo *dst,
Gian Marco Iodice2cc50b32022-05-30 14:41:49 +010071 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc);
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010072 /** Static function to check if given info will lead to a valid configuration
Sheri Zhang1efed922021-03-10 22:43:38 +000073 *
Manuel Bottinib4bb6a02021-05-24 16:01:32 +010074 * Similar to ClDirectConv2dKernel::configure()
Sheri Zhang1efed922021-03-10 22:43:38 +000075 *
76 * @return a status
77 */
Georgios Pinitas9fc3be62021-05-29 04:01:51 +010078 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst,
Gian Marco Iodice2cc50b32022-05-30 14:41:49 +010079 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc);
Sheri Zhang1efed922021-03-10 22:43:38 +000080
81 // Inherited methods overridden:
82 void run_op(ITensorPack &tensors, const Window &window, cl::CommandQueue &queue) override;
Sheri Zhang1efed922021-03-10 22:43:38 +000083
84public:
85 DataLayout _data_layout{};
Sheri Zhang1efed922021-03-10 22:43:38 +000086 PadStrideInfo _conv_info{};
Gian Marco Iodice3cce35d2022-12-30 16:07:45 +000087 bool _export_weights_to_cl_image{ false };
88 bool _export_output_to_cl_image{ false };
89 bool _export_input_to_cl_image{ false };
Sheri Zhang1efed922021-03-10 22:43:38 +000090};
91} // namespace kernels
92} // namespace opencl
93} // namespace arm_compute
Georgios Pinitas2eb5d162021-07-02 09:01:49 +010094#endif /* ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H */