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Gian Marco Iodice76335eb2022-11-17 11:03:39 +00001/*
2 * Copyright (c) 2022 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24#ifndef ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H
25#define ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H
26
27#include "src/core/common/Macros.h"
28#include "src/gpu/cl/ClCompileContext.h"
29#include "src/gpu/cl/IClKernel.h"
30
31namespace arm_compute
32{
33// Forward declaration
34struct DirectConvComputeKernelInfo;
35
36namespace opencl
37{
38namespace kernels
39{
40/** Interface for the indirect convolution kernel. */
41class ClIndirectConv2dKernel : public IClKernel
42{
43public:
44 ClIndirectConv2dKernel();
45 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(ClIndirectConv2dKernel);
46 /** Set the src, offset, weights, biases and dst tensors info.
47 *
48 * @param[in] compile_context The compile context to be used.
49 * @param[in] src The src tensor info to convolve. 3 lower dimensions represent a single src [IFM, width, height],
50 * while every optional dimension from 4 and above represent a batch of inputs. Data types supported: F16/F32.
51 * @param[in] off The indirect buffer tensor info. Data types supported: S32.
52 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [IFM, kernel_x, kernel_y, OFM].
53 * Data type supported: Same as @p src.
54 * @param[in] biases Biases tensor info. Biases are 1D tensor with dimension [OFM].
55 * Data type supported: Same as @p src.
56 * @param[out] dst Output tensor info.
57 * The 3rd dimension must be equal to the 4th dimension of the @p weights tensor. Data types supported: Same as @p src.
58 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
59 * @param[in] act_info Contains activaton information described in @ref ActivationLayerInfo.
60 * @param[in] desc Direct convolution descriptor used to build the NHWC indirect convolution kernel.
61 */
62 void configure(const CLCompileContext &compile_context, ITensorInfo *src, ITensorInfo *off, ITensorInfo *weights, ITensorInfo *biases, ITensorInfo *dst,
63 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc);
64 /** Static function to check if given info will lead to a valid configuration
65 *
66 * Similar to ClIndirectConv2dKernel::configure()
67 *
68 * @return a status
69 */
70 static Status validate(const ITensorInfo *src, const ITensorInfo *off, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst,
71 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, const DirectConvComputeKernelInfo &desc);
72
73 // Inherited methods overridden:
74 void run_op(ITensorPack &tensors, const Window &window, cl::CommandQueue &queue) override;
75
76public:
77 bool _export_to_cl_image{ false };
78};
79} // namespace kernels
80} // namespace opencl
81} // namespace arm_compute
82#endif /* ARM_COMPUTE_CL_DIRECT_CONV2D_KERNEL_H */