Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1 | /* |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2 | * Copyright (c) 2021-2023 Arm Limited. |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "arm_gemm.hpp" |
| 26 | |
| 27 | #include <cstddef> |
| 28 | #include <cstdint> |
| 29 | |
| 30 | #if defined(__aarch64__) |
| 31 | |
| 32 | namespace arm_conv { |
| 33 | namespace depthwise { |
| 34 | |
| 35 | void a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( |
| 36 | const unsigned int n_channels, |
| 37 | const int8_t *const *const inptrs, |
| 38 | const int8_t *const weights, |
| 39 | const int32_t *const bias, |
| 40 | const arm_gemm::Requantize32 &qp, |
| 41 | const int32_t *const requant_muls, |
| 42 | const int32_t *const requant_shifts, |
| 43 | int8_t *const *const outptrs |
| 44 | ) |
| 45 | { |
| 46 | struct Params |
| 47 | { |
| 48 | long unsigned int n_channels; |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 49 | const void *weights; |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 50 | const int32_t *bias; |
| 51 | const arm_gemm::Requantize32 *requant; |
| 52 | const int32_t *const requant_muls; |
| 53 | const int32_t *const requant_shifts; |
| 54 | int8_t *const *const outptrs; |
| 55 | const int8_t *inptrs[36]; |
| 56 | |
| 57 | Params( |
| 58 | long unsigned int n_channels, |
| 59 | const int8_t *const *inptrs_raw, |
ramelg01 | 8a16488 | 2022-04-07 02:42:52 +0100 | [diff] [blame] | 60 | const void *const weights, |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 61 | const int32_t *const bias, |
| 62 | const arm_gemm::Requantize32 &qp, |
| 63 | const int32_t *const requant_muls, |
| 64 | const int32_t *const requant_shifts, |
| 65 | int8_t *const *outptrs |
| 66 | ) : n_channels(n_channels), weights(weights), bias(bias), |
| 67 | requant(&qp), requant_muls(requant_muls), |
| 68 | requant_shifts(requant_shifts), outptrs(outptrs) |
| 69 | { |
| 70 | inptrs[0] = inptrs_raw[0]; |
| 71 | inptrs[1] = inptrs_raw[1]; |
| 72 | inptrs[2] = inptrs_raw[6]; |
| 73 | inptrs[3] = inptrs_raw[7]; |
| 74 | inptrs[4] = inptrs_raw[2]; |
| 75 | inptrs[5] = inptrs_raw[8]; |
| 76 | inptrs[6] = inptrs_raw[3]; |
| 77 | inptrs[7] = inptrs_raw[4]; |
| 78 | inptrs[8] = inptrs_raw[11]; |
| 79 | inptrs[9] = inptrs_raw[12]; |
| 80 | inptrs[10] = inptrs_raw[9]; |
| 81 | inptrs[11] = inptrs_raw[10]; |
| 82 | inptrs[12] = inptrs_raw[5]; |
| 83 | inptrs[13] = inptrs_raw[13]; |
| 84 | inptrs[14] = inptrs_raw[14]; |
| 85 | inptrs[15] = inptrs_raw[15]; |
| 86 | inptrs[16] = inptrs_raw[16]; |
| 87 | inptrs[17] = inptrs_raw[17]; |
| 88 | inptrs[18] = inptrs_raw[18]; |
| 89 | inptrs[19] = inptrs_raw[19]; |
| 90 | inptrs[20] = inptrs_raw[20]; |
| 91 | inptrs[21] = inptrs_raw[21]; |
| 92 | inptrs[22] = inptrs_raw[22]; |
| 93 | inptrs[23] = inptrs_raw[23]; |
| 94 | inptrs[24] = inptrs_raw[24]; |
| 95 | inptrs[25] = inptrs_raw[25]; |
| 96 | inptrs[26] = inptrs_raw[26]; |
| 97 | inptrs[27] = inptrs_raw[27]; |
| 98 | inptrs[28] = inptrs_raw[28]; |
| 99 | inptrs[29] = inptrs_raw[29]; |
| 100 | inptrs[30] = inptrs_raw[30]; |
| 101 | inptrs[31] = inptrs_raw[31]; |
| 102 | inptrs[32] = inptrs_raw[32]; |
| 103 | inptrs[33] = inptrs_raw[33]; |
| 104 | inptrs[34] = inptrs_raw[34]; |
| 105 | inptrs[35] = inptrs_raw[35]; |
| 106 | |
| 107 | } |
| 108 | }; |
| 109 | |
| 110 | const Params params(n_channels, inptrs, weights, bias, qp, |
| 111 | requant_muls, requant_shifts, outptrs); |
| 112 | |
| 113 | __asm__ __volatile__( |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 114 | "ldr x1, [%x[params], %[offsetof_Params_n_channels]]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 115 | "ldr x23, [%x[params], %[offsetof_Params_requant]]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 116 | "lsr x2, x1, #0x3\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 117 | "add x20, x23, %[offsetof_Requantize32_a_offset]\n" |
| 118 | "ld1r { v18.16b }, [x20]\n" |
| 119 | "ldr x22, [%x[params], %[offsetof_Params_outptrs]]\n" |
| 120 | "add x21, x23, %[offsetof_Requantize32_b_offset]\n" |
| 121 | "add x20, x23, %[offsetof_Requantize32_c_offset]\n" |
| 122 | "ld1r { v13.16b }, [x21]\n" |
| 123 | "ld1r { v26.8h }, [x20]\n" |
| 124 | "add x21, x23, %[offsetof_Requantize32_minval]\n" |
| 125 | "add x20, x23, %[offsetof_Requantize32_maxval]\n" |
| 126 | "ld1r { v11.8h }, [x21]\n" |
| 127 | "ld1r { v0.8h }, [x20]\n" |
| 128 | "mov x3, #0x0\n" |
| 129 | "mov x4, #0x0\n" |
| 130 | "add x5, %x[params], %[offsetof_Params_inptrs]\n" |
| 131 | "ldr x6, [%x[params], %[offsetof_Params_weights]]\n" |
| 132 | "ldr x7, [%x[params], %[offsetof_Params_requant_muls]]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 133 | "ldr x8, [%x[params], %[offsetof_Params_requant_shifts]]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 134 | "ldp x17, x16, [x22, #0x0]\n" |
| 135 | "ldp x15, x14, [x22, #0x10]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 136 | "cbz x2, 3f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 137 | "ldr d6, [x6, #0x0]\n" |
| 138 | "ldr d14, [x6, #0x8]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 139 | "subs x2, x2, #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 140 | "ssubl v6.8h, v6.8b, v13.8b\n" |
| 141 | "ldr d10, [x6, #0x10]\n" |
| 142 | "ldr d21, [x6, #0x18]\n" |
| 143 | "ssubl v14.8h, v14.8b, v13.8b\n" |
| 144 | "ssubl v10.8h, v10.8b, v13.8b\n" |
| 145 | "ldr d12, [x6, #0x20]\n" |
| 146 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 147 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 148 | "ssubl v12.8h, v12.8b, v13.8b\n" |
| 149 | "ldr q7, [x20, #0x0]\n" |
| 150 | "ldr q15, [x20, #0x10]\n" |
| 151 | "add x20, x20, #0x20\n" |
| 152 | "str x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 153 | "ldp x9, x28, [x5, #0x0]\n" |
| 154 | "ldp x27, x26, [x5, #0x10]\n" |
| 155 | "mov v20.16b, v7.16b\n" |
| 156 | "mov v5.16b, v15.16b\n" |
| 157 | "ldp x25, x24, [x5, #0x20]\n" |
| 158 | "ldp x23, x22, [x5, #0x30]\n" |
| 159 | "mov v24.16b, v7.16b\n" |
| 160 | "mov v22.16b, v15.16b\n" |
| 161 | "ldp x21, x20, [x5, #0x40]\n" |
| 162 | "ldr d31, [x9, x3]\n" |
| 163 | "mov v23.16b, v7.16b\n" |
| 164 | "mov v19.16b, v15.16b\n" |
| 165 | "ldr d17, [x28, x3]\n" |
| 166 | "ldr d30, [x27, x3]\n" |
| 167 | "ssubl v31.8h, v31.8b, v18.8b\n" |
| 168 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 169 | "ldr d16, [x26, x3]\n" |
| 170 | "ldr d3, [x25, x3]\n" |
| 171 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 172 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 173 | "ldr d4, [x24, x3]\n" |
| 174 | "ldr d25, [x23, x3]\n" |
| 175 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 176 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 177 | "ldr d9, [x22, x3]\n" |
| 178 | "ldr d29, [x21, x3]\n" |
| 179 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 180 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 181 | "ldr d28, [x20, x3]\n" |
| 182 | "ssubl v29.8h, v29.8b, v18.8b\n" |
| 183 | "ssubl v28.8h, v28.8b, v18.8b\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 184 | "beq 2f\n" |
| 185 | "1:" // Loop |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 186 | "ldr d2, [x6, #0x28]\n" |
| 187 | "ldr d27, [x6, #0x30]\n" |
| 188 | "smlal v7.4s, v31.4h, v6.4h\n" |
| 189 | "smlal2 v15.4s, v31.8h, v6.8h\n" |
| 190 | "ldr d1, [x6, #0x38]\n" |
| 191 | "ldr d31, [x6, #0x40]\n" |
| 192 | "smlal v7.4s, v17.4h, v14.4h\n" |
| 193 | "smlal v20.4s, v17.4h, v6.4h\n" |
| 194 | "ldr d8, [x6, #0x48]\n" |
| 195 | "ldr x22, [x5, #0x50]\n" |
| 196 | "smlal v24.4s, v30.4h, v6.4h\n" |
| 197 | "smlal v23.4s, v16.4h, v6.4h\n" |
| 198 | "smlal2 v15.4s, v17.8h, v14.8h\n" |
| 199 | "smlal v7.4s, v3.4h, v10.4h\n" |
| 200 | "ldr x20, [x5, #0x58]\n" |
| 201 | "ldr x21, [x5, #0x60]\n" |
| 202 | "smlal2 v5.4s, v17.8h, v6.8h\n" |
| 203 | "ldr d17, [x22, x3]\n" |
| 204 | "smlal2 v22.4s, v30.8h, v6.8h\n" |
| 205 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 206 | "smlal2 v19.4s, v16.8h, v6.8h\n" |
| 207 | "ldr d6, [x20, x3]\n" |
| 208 | "smlal v20.4s, v3.4h, v14.4h\n" |
| 209 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 210 | "smlal v24.4s, v16.4h, v14.4h\n" |
| 211 | "smlal v23.4s, v4.4h, v14.4h\n" |
| 212 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 213 | "ldr x20, [x5, #0x68]\n" |
| 214 | "smlal2 v15.4s, v3.8h, v10.8h\n" |
| 215 | "smlal v7.4s, v25.4h, v21.4h\n" |
| 216 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 217 | "ldr x22, [x5, #0x70]\n" |
| 218 | "smlal2 v5.4s, v3.8h, v14.8h\n" |
| 219 | "ldr d3, [x21, x3]\n" |
| 220 | "smlal2 v22.4s, v16.8h, v14.8h\n" |
| 221 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 222 | "smlal2 v19.4s, v4.8h, v14.8h\n" |
| 223 | "ldr d14, [x20, x3]\n" |
| 224 | "smlal v20.4s, v25.4h, v10.4h\n" |
| 225 | "ssubl v14.8h, v14.8b, v18.8b\n" |
| 226 | "smlal v24.4s, v4.4h, v10.4h\n" |
| 227 | "smlal v23.4s, v17.4h, v10.4h\n" |
| 228 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 229 | "ldr x20, [x5, #0x78]\n" |
| 230 | "smlal2 v15.4s, v25.8h, v21.8h\n" |
| 231 | "smlal v7.4s, v9.4h, v12.4h\n" |
| 232 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 233 | "ldr x21, [x5, #0x80]\n" |
| 234 | "smlal2 v5.4s, v25.8h, v10.8h\n" |
| 235 | "ldr d25, [x22, x3]\n" |
| 236 | "smlal2 v22.4s, v4.8h, v10.8h\n" |
| 237 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 238 | "smlal2 v19.4s, v17.8h, v10.8h\n" |
| 239 | "ldr d10, [x20, x3]\n" |
| 240 | "smlal v20.4s, v9.4h, v21.4h\n" |
| 241 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 242 | "smlal v24.4s, v17.4h, v21.4h\n" |
| 243 | "smlal v23.4s, v6.4h, v21.4h\n" |
| 244 | "ssubl v8.8h, v8.8b, v13.8b\n" |
| 245 | "ldr x24, [x5, #0x88]\n" |
| 246 | "smlal2 v15.4s, v9.8h, v12.8h\n" |
| 247 | "smlal v7.4s, v30.4h, v2.4h\n" |
| 248 | "ldr x20, [x5, #0x90]\n" |
| 249 | "ldr x23, [x5, #0x98]\n" |
| 250 | "smlal2 v5.4s, v9.8h, v21.8h\n" |
| 251 | "ldr d9, [x21, x3]\n" |
| 252 | "smlal2 v22.4s, v17.8h, v21.8h\n" |
| 253 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 254 | "smlal2 v19.4s, v6.8h, v21.8h\n" |
| 255 | "ldr d21, [x6, #0x50]\n" |
| 256 | "smlal v20.4s, v3.4h, v12.4h\n" |
| 257 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 258 | "smlal v24.4s, v6.4h, v12.4h\n" |
| 259 | "smlal v23.4s, v29.4h, v12.4h\n" |
| 260 | "ldr x22, [x5, #0xa0]\n" |
| 261 | "ldr x21, [x5, #0xa8]\n" |
| 262 | "smlal2 v15.4s, v30.8h, v2.8h\n" |
| 263 | "ldr d30, [x24, x3]\n" |
| 264 | "smlal v7.4s, v16.4h, v27.4h\n" |
| 265 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 266 | "smlal2 v5.4s, v3.8h, v12.8h\n" |
| 267 | "ldr d3, [x6, #0x58]\n" |
| 268 | "smlal2 v22.4s, v6.8h, v12.8h\n" |
| 269 | "ssubl v3.8h, v3.8b, v13.8b\n" |
| 270 | "smlal2 v19.4s, v29.8h, v12.8h\n" |
| 271 | "ldr d12, [x20, x3]\n" |
| 272 | "smlal v20.4s, v16.4h, v2.4h\n" |
| 273 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 274 | "smlal v24.4s, v28.4h, v2.4h\n" |
| 275 | "smlal v23.4s, v14.4h, v2.4h\n" |
| 276 | "ldr x20, [x5, #0xb0]\n" |
| 277 | "ldr x13, [x5, #0xb8]\n" |
| 278 | "smlal2 v15.4s, v16.8h, v27.8h\n" |
| 279 | "smlal v7.4s, v4.4h, v1.4h\n" |
| 280 | "ldr x12, [x5, #0xc0]\n" |
| 281 | "ldr x11, [x5, #0xc8]\n" |
| 282 | "smlal2 v5.4s, v16.8h, v2.8h\n" |
| 283 | "ldr d16, [x23, x3]\n" |
| 284 | "smlal2 v22.4s, v28.8h, v2.8h\n" |
| 285 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 286 | "smlal2 v19.4s, v14.8h, v2.8h\n" |
| 287 | "ldr d2, [x6, #0x60]\n" |
| 288 | "smlal v20.4s, v4.4h, v27.4h\n" |
| 289 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 290 | "smlal v24.4s, v14.4h, v27.4h\n" |
| 291 | "smlal v23.4s, v25.4h, v27.4h\n" |
| 292 | "ldr x10, [x5, #0xd0]\n" |
| 293 | "ldr x9, [x5, #0xd8]\n" |
| 294 | "smlal2 v15.4s, v4.8h, v1.8h\n" |
| 295 | "smlal v7.4s, v17.4h, v31.4h\n" |
| 296 | "ldr x28, [x5, #0xe0]\n" |
| 297 | "ldr x27, [x5, #0xe8]\n" |
| 298 | "smlal2 v5.4s, v4.8h, v27.8h\n" |
| 299 | "ldr d4, [x22, x3]\n" |
| 300 | "smlal2 v22.4s, v14.8h, v27.8h\n" |
| 301 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 302 | "smlal2 v19.4s, v25.8h, v27.8h\n" |
| 303 | "ldr d27, [x6, #0x68]\n" |
| 304 | "smlal v20.4s, v17.4h, v1.4h\n" |
| 305 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 306 | "smlal v24.4s, v25.4h, v1.4h\n" |
| 307 | "smlal v23.4s, v10.4h, v1.4h\n" |
| 308 | "ldr x26, [x5, #0xf0]\n" |
| 309 | "ldr x25, [x5, #0xf8]\n" |
| 310 | "smlal2 v15.4s, v17.8h, v31.8h\n" |
| 311 | "smlal v7.4s, v6.4h, v8.4h\n" |
| 312 | "ldr x24, [x5, #0x100]\n" |
| 313 | "ldr x23, [x5, #0x108]\n" |
| 314 | "smlal2 v5.4s, v17.8h, v1.8h\n" |
| 315 | "ldr d17, [x21, x3]\n" |
| 316 | "smlal2 v22.4s, v25.8h, v1.8h\n" |
| 317 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 318 | "smlal2 v19.4s, v10.8h, v1.8h\n" |
| 319 | "ldr d1, [x6, #0x70]\n" |
| 320 | "smlal v20.4s, v6.4h, v31.4h\n" |
| 321 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 322 | "smlal v24.4s, v10.4h, v31.4h\n" |
| 323 | "smlal v23.4s, v9.4h, v31.4h\n" |
| 324 | "ldr x22, [x5, #0x110]\n" |
| 325 | "ldr x21, [x5, #0x118]\n" |
| 326 | "smlal2 v15.4s, v6.8h, v8.8h\n" |
| 327 | "smlal v7.4s, v28.4h, v21.4h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 328 | "subs x2, x2, #0x1\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 329 | "smlal2 v5.4s, v6.8h, v31.8h\n" |
| 330 | "ldr d6, [x20, x3]\n" |
| 331 | "smlal2 v22.4s, v10.8h, v31.8h\n" |
| 332 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 333 | "smlal2 v19.4s, v9.8h, v31.8h\n" |
| 334 | "ldr d31, [x6, #0x78]\n" |
| 335 | "smlal v20.4s, v29.4h, v8.4h\n" |
| 336 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 337 | "smlal v24.4s, v9.4h, v8.4h\n" |
| 338 | "smlal v23.4s, v30.4h, v8.4h\n" |
| 339 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 340 | "smlal2 v15.4s, v28.8h, v21.8h\n" |
| 341 | "ldr d28, [x13, x3]\n" |
| 342 | "smlal v7.4s, v14.4h, v3.4h\n" |
| 343 | "ssubl v28.8h, v28.8b, v18.8b\n" |
| 344 | "smlal2 v5.4s, v29.8h, v8.8h\n" |
| 345 | "ldr d29, [x6, #0x80]\n" |
| 346 | "smlal2 v22.4s, v9.8h, v8.8h\n" |
| 347 | "ssubl v29.8h, v29.8b, v13.8b\n" |
| 348 | "smlal2 v19.4s, v30.8h, v8.8h\n" |
| 349 | "ldr d8, [x12, x3]\n" |
| 350 | "smlal v20.4s, v14.4h, v21.4h\n" |
| 351 | "ssubl v8.8h, v8.8b, v18.8b\n" |
| 352 | "smlal v24.4s, v12.4h, v21.4h\n" |
| 353 | "smlal v23.4s, v16.4h, v21.4h\n" |
| 354 | "smlal2 v15.4s, v14.8h, v3.8h\n" |
| 355 | "smlal v7.4s, v25.4h, v2.4h\n" |
| 356 | "smlal2 v5.4s, v14.8h, v21.8h\n" |
| 357 | "ldr d14, [x11, x3]\n" |
| 358 | "smlal2 v22.4s, v12.8h, v21.8h\n" |
| 359 | "ssubl v14.8h, v14.8b, v18.8b\n" |
| 360 | "smlal2 v19.4s, v16.8h, v21.8h\n" |
| 361 | "ldr d21, [x6, #0x88]\n" |
| 362 | "smlal v20.4s, v25.4h, v3.4h\n" |
| 363 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 364 | "smlal v24.4s, v16.4h, v3.4h\n" |
| 365 | "smlal v23.4s, v4.4h, v3.4h\n" |
| 366 | "smlal2 v15.4s, v25.8h, v2.8h\n" |
| 367 | "smlal v7.4s, v10.4h, v27.4h\n" |
| 368 | "smlal2 v5.4s, v25.8h, v3.8h\n" |
| 369 | "ldr d25, [x10, x3]\n" |
| 370 | "smlal2 v22.4s, v16.8h, v3.8h\n" |
| 371 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 372 | "smlal2 v19.4s, v4.8h, v3.8h\n" |
| 373 | "ldr d3, [x6, #0x90]\n" |
| 374 | "smlal v20.4s, v10.4h, v2.4h\n" |
| 375 | "ssubl v3.8h, v3.8b, v13.8b\n" |
| 376 | "smlal v24.4s, v4.4h, v2.4h\n" |
| 377 | "smlal v23.4s, v17.4h, v2.4h\n" |
| 378 | "smlal2 v15.4s, v10.8h, v27.8h\n" |
| 379 | "smlal v7.4s, v9.4h, v1.4h\n" |
| 380 | "smlal2 v5.4s, v10.8h, v2.8h\n" |
| 381 | "ldr d10, [x9, x3]\n" |
| 382 | "smlal2 v22.4s, v4.8h, v2.8h\n" |
| 383 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 384 | "smlal2 v19.4s, v17.8h, v2.8h\n" |
| 385 | "ldr d2, [x6, #0x98]\n" |
| 386 | "smlal v20.4s, v9.4h, v27.4h\n" |
| 387 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 388 | "smlal v24.4s, v17.4h, v27.4h\n" |
| 389 | "smlal v23.4s, v6.4h, v27.4h\n" |
| 390 | "smlal2 v15.4s, v9.8h, v1.8h\n" |
| 391 | "smlal v7.4s, v12.4h, v31.4h\n" |
| 392 | "smlal2 v5.4s, v9.8h, v27.8h\n" |
| 393 | "ldr d9, [x28, x3]\n" |
| 394 | "smlal2 v22.4s, v17.8h, v27.8h\n" |
| 395 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 396 | "smlal2 v19.4s, v6.8h, v27.8h\n" |
| 397 | "ldr d27, [x6, #0xa0]\n" |
| 398 | "smlal v20.4s, v30.4h, v1.4h\n" |
| 399 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 400 | "smlal v24.4s, v6.4h, v1.4h\n" |
| 401 | "smlal v23.4s, v28.4h, v1.4h\n" |
| 402 | "smlal2 v15.4s, v12.8h, v31.8h\n" |
| 403 | "ldr d12, [x27, x3]\n" |
| 404 | "smlal v7.4s, v16.4h, v29.4h\n" |
| 405 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 406 | "smlal2 v5.4s, v30.8h, v1.8h\n" |
| 407 | "ldr d30, [x6, #0xa8]\n" |
| 408 | "smlal2 v22.4s, v6.8h, v1.8h\n" |
| 409 | "ssubl v30.8h, v30.8b, v13.8b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 410 | "smlal2 v19.4s, v28.8h, v1.8h\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 411 | "ldr d1, [x26, x3]\n" |
| 412 | "smlal v20.4s, v16.4h, v31.4h\n" |
| 413 | "ssubl v1.8h, v1.8b, v18.8b\n" |
| 414 | "smlal v24.4s, v8.4h, v31.4h\n" |
| 415 | "smlal v23.4s, v14.4h, v31.4h\n" |
| 416 | "smlal2 v15.4s, v16.8h, v29.8h\n" |
| 417 | "smlal v7.4s, v4.4h, v21.4h\n" |
| 418 | "smlal2 v5.4s, v16.8h, v31.8h\n" |
| 419 | "ldr d16, [x25, x3]\n" |
| 420 | "smlal2 v22.4s, v8.8h, v31.8h\n" |
| 421 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 422 | "smlal2 v19.4s, v14.8h, v31.8h\n" |
| 423 | "ldr d31, [x6, #0xb0]\n" |
| 424 | "smlal v20.4s, v4.4h, v29.4h\n" |
| 425 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 426 | "smlal v24.4s, v14.4h, v29.4h\n" |
| 427 | "smlal v23.4s, v25.4h, v29.4h\n" |
| 428 | "smlal2 v15.4s, v4.8h, v21.8h\n" |
| 429 | "smlal v7.4s, v17.4h, v3.4h\n" |
| 430 | "smlal2 v5.4s, v4.8h, v29.8h\n" |
| 431 | "ldr d4, [x24, x3]\n" |
| 432 | "smlal2 v22.4s, v14.8h, v29.8h\n" |
| 433 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 434 | "smlal2 v19.4s, v25.8h, v29.8h\n" |
| 435 | "ldr d29, [x6, #0xb8]\n" |
| 436 | "smlal v20.4s, v17.4h, v21.4h\n" |
| 437 | "ssubl v29.8h, v29.8b, v13.8b\n" |
| 438 | "smlal v24.4s, v25.4h, v21.4h\n" |
| 439 | "smlal v23.4s, v10.4h, v21.4h\n" |
| 440 | "smlal2 v15.4s, v17.8h, v3.8h\n" |
| 441 | "smlal v7.4s, v6.4h, v2.4h\n" |
| 442 | "smlal2 v5.4s, v17.8h, v21.8h\n" |
| 443 | "ldr d17, [x23, x3]\n" |
| 444 | "smlal2 v22.4s, v25.8h, v21.8h\n" |
| 445 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 446 | "smlal2 v19.4s, v10.8h, v21.8h\n" |
| 447 | "ldr d21, [x6, #0xc0]\n" |
| 448 | "smlal v20.4s, v6.4h, v3.4h\n" |
| 449 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 450 | "smlal v24.4s, v10.4h, v3.4h\n" |
| 451 | "smlal v23.4s, v9.4h, v3.4h\n" |
| 452 | "add x6, x6, #0xc8\n" |
| 453 | "smlal2 v15.4s, v6.8h, v2.8h\n" |
| 454 | "smlal v7.4s, v8.4h, v27.4h\n" |
| 455 | "smlal2 v5.4s, v6.8h, v3.8h\n" |
| 456 | "ldr d6, [x22, x3]\n" |
| 457 | "smlal2 v22.4s, v10.8h, v3.8h\n" |
| 458 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 459 | "smlal2 v19.4s, v9.8h, v3.8h\n" |
| 460 | "ldr d3, [x21, x3]\n" |
| 461 | "smlal v20.4s, v28.4h, v2.4h\n" |
| 462 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 463 | "smlal v24.4s, v9.4h, v2.4h\n" |
| 464 | "smlal v23.4s, v12.4h, v2.4h\n" |
| 465 | "add x3, x3, #0x8\n" |
| 466 | "smlal2 v15.4s, v8.8h, v27.8h\n" |
| 467 | "ldr q8, [x7, #0x0]\n" |
| 468 | "smlal v7.4s, v14.4h, v30.4h\n" |
| 469 | "smlal2 v5.4s, v28.8h, v2.8h\n" |
| 470 | "ldr q28, [x8, #0x0]\n" |
| 471 | "smlal2 v22.4s, v9.8h, v2.8h\n" |
| 472 | "smlal2 v19.4s, v12.8h, v2.8h\n" |
| 473 | "ldr q2, [x7, #0x10]\n" |
| 474 | "smlal v20.4s, v14.4h, v27.4h\n" |
| 475 | "add x7, x7, #0x20\n" |
| 476 | "smlal v24.4s, v1.4h, v27.4h\n" |
| 477 | "smlal v23.4s, v16.4h, v27.4h\n" |
| 478 | "smlal2 v15.4s, v14.8h, v30.8h\n" |
| 479 | "smlal v7.4s, v25.4h, v31.4h\n" |
| 480 | "smlal2 v5.4s, v14.8h, v27.8h\n" |
| 481 | "ldr q14, [x8, #0x10]\n" |
| 482 | "smlal2 v22.4s, v1.8h, v27.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 483 | "add x8, x8, #0x20\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 484 | "smlal2 v19.4s, v16.8h, v27.8h\n" |
| 485 | "smlal v20.4s, v25.4h, v30.4h\n" |
| 486 | "smlal v24.4s, v16.4h, v30.4h\n" |
| 487 | "smlal v23.4s, v4.4h, v30.4h\n" |
| 488 | "smlal2 v15.4s, v25.8h, v31.8h\n" |
| 489 | "smlal v7.4s, v10.4h, v29.4h\n" |
| 490 | "smlal2 v5.4s, v25.8h, v30.8h\n" |
| 491 | "smlal2 v22.4s, v16.8h, v30.8h\n" |
| 492 | "smlal2 v19.4s, v4.8h, v30.8h\n" |
| 493 | "smlal v20.4s, v10.4h, v31.4h\n" |
| 494 | "smlal v24.4s, v4.4h, v31.4h\n" |
| 495 | "smlal v23.4s, v17.4h, v31.4h\n" |
| 496 | "smlal2 v15.4s, v10.8h, v29.8h\n" |
| 497 | "smlal v7.4s, v9.4h, v21.4h\n" |
| 498 | "sqrdmulh v7.4s, v7.4s, v8.4s\n" |
| 499 | "smlal2 v5.4s, v10.8h, v31.8h\n" |
| 500 | "smlal2 v22.4s, v4.8h, v31.8h\n" |
| 501 | "and v27.16b, v7.16b, v28.16b\n" |
| 502 | "smlal2 v19.4s, v17.8h, v31.8h\n" |
| 503 | "smlal v20.4s, v9.4h, v29.4h\n" |
| 504 | "sshr v27.4s, v27.4s, #0x1f\n" |
| 505 | "smlal v24.4s, v17.4h, v29.4h\n" |
| 506 | "smlal v23.4s, v6.4h, v29.4h\n" |
| 507 | "sqadd v7.4s, v7.4s, v27.4s\n" |
| 508 | "smlal2 v15.4s, v9.8h, v21.8h\n" |
| 509 | "smlal2 v5.4s, v9.8h, v29.8h\n" |
| 510 | "sqrdmulh v15.4s, v15.4s, v2.4s\n" |
| 511 | "smlal2 v22.4s, v17.8h, v29.8h\n" |
| 512 | "smlal2 v19.4s, v6.8h, v29.8h\n" |
| 513 | "and v9.16b, v15.16b, v14.16b\n" |
| 514 | "smlal v20.4s, v12.4h, v21.4h\n" |
| 515 | "smlal v24.4s, v6.4h, v21.4h\n" |
| 516 | "sqrdmulh v20.4s, v20.4s, v8.4s\n" |
| 517 | "smlal v23.4s, v3.4h, v21.4h\n" |
| 518 | "smlal2 v5.4s, v12.8h, v21.8h\n" |
| 519 | "sqrdmulh v24.4s, v24.4s, v8.4s\n" |
| 520 | "smlal2 v22.4s, v6.8h, v21.8h\n" |
| 521 | "smlal2 v19.4s, v3.8h, v21.8h\n" |
| 522 | "sqrdmulh v23.4s, v23.4s, v8.4s\n" |
| 523 | "sshr v9.4s, v9.4s, #0x1f\n" |
| 524 | "and v25.16b, v20.16b, v28.16b\n" |
| 525 | "sqrdmulh v5.4s, v5.4s, v2.4s\n" |
| 526 | "and v10.16b, v24.16b, v28.16b\n" |
| 527 | "sqrdmulh v22.4s, v22.4s, v2.4s\n" |
| 528 | "and v21.16b, v23.16b, v28.16b\n" |
| 529 | "sqrdmulh v19.4s, v19.4s, v2.4s\n" |
| 530 | "sqadd v15.4s, v15.4s, v9.4s\n" |
| 531 | "sshr v25.4s, v25.4s, #0x1f\n" |
| 532 | "and v9.16b, v5.16b, v14.16b\n" |
| 533 | "sshr v10.4s, v10.4s, #0x1f\n" |
| 534 | "and v12.16b, v22.16b, v14.16b\n" |
| 535 | "sshr v21.4s, v21.4s, #0x1f\n" |
| 536 | "and v17.16b, v19.16b, v14.16b\n" |
| 537 | "sqadd v20.4s, v20.4s, v25.4s\n" |
| 538 | "sshr v9.4s, v9.4s, #0x1f\n" |
| 539 | "sqadd v24.4s, v24.4s, v10.4s\n" |
| 540 | "sshr v12.4s, v12.4s, #0x1f\n" |
| 541 | "sqadd v23.4s, v23.4s, v21.4s\n" |
| 542 | "sshr v17.4s, v17.4s, #0x1f\n" |
| 543 | "srshl v7.4s, v7.4s, v28.4s\n" |
| 544 | "srshl v20.4s, v20.4s, v28.4s\n" |
| 545 | "sqadd v5.4s, v5.4s, v9.4s\n" |
| 546 | "srshl v24.4s, v24.4s, v28.4s\n" |
| 547 | "sqadd v22.4s, v22.4s, v12.4s\n" |
| 548 | "srshl v23.4s, v23.4s, v28.4s\n" |
| 549 | "sqadd v19.4s, v19.4s, v17.4s\n" |
| 550 | "srshl v15.4s, v15.4s, v14.4s\n" |
| 551 | "sqxtn v7.4h, v7.4s\n" |
| 552 | "srshl v5.4s, v5.4s, v14.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 553 | "sqxtn v20.4h, v20.4s\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 554 | "srshl v22.4s, v22.4s, v14.4s\n" |
| 555 | "sqxtn v24.4h, v24.4s\n" |
| 556 | "srshl v19.4s, v19.4s, v14.4s\n" |
| 557 | "sqxtn v23.4h, v23.4s\n" |
| 558 | "sqxtn2 v7.8h, v15.4s\n" |
| 559 | "sqxtn2 v20.8h, v5.4s\n" |
| 560 | "sqxtn2 v24.8h, v22.4s\n" |
| 561 | "sqxtn2 v23.8h, v19.4s\n" |
| 562 | "sqadd v7.8h, v7.8h, v26.8h\n" |
| 563 | "sqadd v20.8h, v20.8h, v26.8h\n" |
| 564 | "sqadd v24.8h, v24.8h, v26.8h\n" |
| 565 | "sqadd v23.8h, v23.8h, v26.8h\n" |
| 566 | "smax v7.8h, v7.8h, v11.8h\n" |
| 567 | "smax v20.8h, v20.8h, v11.8h\n" |
| 568 | "smax v24.8h, v24.8h, v11.8h\n" |
| 569 | "smax v23.8h, v23.8h, v11.8h\n" |
| 570 | "smin v7.8h, v7.8h, v0.8h\n" |
| 571 | "smin v20.8h, v20.8h, v0.8h\n" |
| 572 | "smin v24.8h, v24.8h, v0.8h\n" |
| 573 | "smin v23.8h, v23.8h, v0.8h\n" |
| 574 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
| 575 | "str d7, [x17, x4]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 576 | "uzp1 v20.16b, v20.16b, v20.16b\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 577 | "uzp1 v24.16b, v24.16b, v24.16b\n" |
| 578 | "str d20, [x16, x4]\n" |
| 579 | "uzp1 v23.16b, v23.16b, v23.16b\n" |
| 580 | "str d24, [x15, x4]\n" |
| 581 | "str d23, [x14, x4]\n" |
| 582 | "ldr q7, [x20, #0x0]\n" |
| 583 | "ldr q15, [x20, #0x10]\n" |
| 584 | "add x20, x20, #0x20\n" |
| 585 | "ldr d6, [x6, #0x0]\n" |
| 586 | "ldr d14, [x6, #0x8]\n" |
| 587 | "add x4, x4, #0x8\n" |
| 588 | "str x20, [%x[params], %[offsetof_Params_bias]]\n" |
| 589 | "ldr d10, [x6, #0x10]\n" |
| 590 | "ldr d21, [x6, #0x18]\n" |
| 591 | "mov v20.16b, v7.16b\n" |
| 592 | "mov v5.16b, v15.16b\n" |
| 593 | "ldr d12, [x6, #0x20]\n" |
| 594 | "ldp x9, x28, [x5, #0x0]\n" |
| 595 | "mov v24.16b, v7.16b\n" |
| 596 | "mov v22.16b, v15.16b\n" |
| 597 | "ldp x27, x26, [x5, #0x10]\n" |
| 598 | "ldp x25, x24, [x5, #0x20]\n" |
| 599 | "mov v23.16b, v7.16b\n" |
| 600 | "mov v19.16b, v15.16b\n" |
| 601 | "ldp x23, x22, [x5, #0x30]\n" |
| 602 | "ldp x21, x20, [x5, #0x40]\n" |
| 603 | "ssubl v6.8h, v6.8b, v13.8b\n" |
| 604 | "ssubl v14.8h, v14.8b, v13.8b\n" |
| 605 | "ldr d31, [x9, x3]\n" |
| 606 | "ldr d17, [x28, x3]\n" |
| 607 | "ssubl v10.8h, v10.8b, v13.8b\n" |
| 608 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 609 | "ldr d30, [x27, x3]\n" |
| 610 | "ldr d16, [x26, x3]\n" |
| 611 | "ssubl v12.8h, v12.8b, v13.8b\n" |
| 612 | "ssubl v31.8h, v31.8b, v18.8b\n" |
| 613 | "ldr d3, [x25, x3]\n" |
| 614 | "ldr d4, [x24, x3]\n" |
| 615 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 616 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 617 | "ldr d25, [x23, x3]\n" |
| 618 | "ldr d9, [x22, x3]\n" |
| 619 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 620 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 621 | "ldr d29, [x21, x3]\n" |
| 622 | "ldr d28, [x20, x3]\n" |
| 623 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 624 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 625 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 626 | "ssubl v29.8h, v29.8b, v18.8b\n" |
| 627 | "ssubl v28.8h, v28.8b, v18.8b\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 628 | "bgt 1b\n" |
| 629 | "2:" // Tail |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 630 | "ldr d27, [x6, #0x28]\n" |
| 631 | "ldr d1, [x6, #0x30]\n" |
| 632 | "smlal v7.4s, v31.4h, v6.4h\n" |
| 633 | "smlal2 v15.4s, v31.8h, v6.8h\n" |
| 634 | "ldr d2, [x6, #0x38]\n" |
| 635 | "ldr d31, [x6, #0x40]\n" |
| 636 | "smlal v7.4s, v17.4h, v14.4h\n" |
| 637 | "smlal v20.4s, v17.4h, v6.4h\n" |
| 638 | "ldr d8, [x6, #0x48]\n" |
| 639 | "ldr x22, [x5, #0x50]\n" |
| 640 | "smlal v24.4s, v30.4h, v6.4h\n" |
| 641 | "smlal v23.4s, v16.4h, v6.4h\n" |
| 642 | "smlal2 v15.4s, v17.8h, v14.8h\n" |
| 643 | "smlal v7.4s, v3.4h, v10.4h\n" |
| 644 | "ldr x20, [x5, #0x58]\n" |
| 645 | "ldr x21, [x5, #0x60]\n" |
| 646 | "smlal2 v5.4s, v17.8h, v6.8h\n" |
| 647 | "ldr d17, [x22, x3]\n" |
| 648 | "smlal2 v22.4s, v30.8h, v6.8h\n" |
| 649 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 650 | "smlal2 v19.4s, v16.8h, v6.8h\n" |
| 651 | "ldr d6, [x20, x3]\n" |
| 652 | "smlal v20.4s, v3.4h, v14.4h\n" |
| 653 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 654 | "smlal v24.4s, v16.4h, v14.4h\n" |
| 655 | "smlal v23.4s, v4.4h, v14.4h\n" |
| 656 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 657 | "ldr x20, [x5, #0x68]\n" |
| 658 | "smlal2 v15.4s, v3.8h, v10.8h\n" |
| 659 | "smlal v7.4s, v25.4h, v21.4h\n" |
| 660 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 661 | "ldr x22, [x5, #0x70]\n" |
| 662 | "smlal2 v5.4s, v3.8h, v14.8h\n" |
| 663 | "ldr d3, [x21, x3]\n" |
| 664 | "smlal2 v22.4s, v16.8h, v14.8h\n" |
| 665 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 666 | "smlal2 v19.4s, v4.8h, v14.8h\n" |
| 667 | "ldr d14, [x20, x3]\n" |
| 668 | "smlal v20.4s, v25.4h, v10.4h\n" |
| 669 | "ssubl v14.8h, v14.8b, v18.8b\n" |
| 670 | "smlal v24.4s, v4.4h, v10.4h\n" |
| 671 | "smlal v23.4s, v17.4h, v10.4h\n" |
| 672 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 673 | "ldr x21, [x5, #0x78]\n" |
| 674 | "smlal2 v15.4s, v25.8h, v21.8h\n" |
| 675 | "smlal v7.4s, v9.4h, v12.4h\n" |
| 676 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 677 | "ldr x20, [x5, #0x80]\n" |
| 678 | "smlal2 v5.4s, v25.8h, v10.8h\n" |
| 679 | "ldr d25, [x22, x3]\n" |
| 680 | "smlal2 v22.4s, v4.8h, v10.8h\n" |
| 681 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 682 | "smlal2 v19.4s, v17.8h, v10.8h\n" |
| 683 | "ldr d10, [x21, x3]\n" |
| 684 | "smlal v20.4s, v9.4h, v21.4h\n" |
| 685 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 686 | "smlal v24.4s, v17.4h, v21.4h\n" |
| 687 | "smlal v23.4s, v6.4h, v21.4h\n" |
| 688 | "ssubl v8.8h, v8.8b, v13.8b\n" |
| 689 | "ldr x24, [x5, #0x88]\n" |
| 690 | "smlal2 v15.4s, v9.8h, v12.8h\n" |
| 691 | "smlal v7.4s, v30.4h, v27.4h\n" |
| 692 | "ldr x23, [x5, #0x90]\n" |
| 693 | "ldr x22, [x5, #0x98]\n" |
| 694 | "smlal2 v5.4s, v9.8h, v21.8h\n" |
| 695 | "ldr d9, [x20, x3]\n" |
| 696 | "smlal2 v22.4s, v17.8h, v21.8h\n" |
| 697 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 698 | "smlal2 v19.4s, v6.8h, v21.8h\n" |
| 699 | "ldr d21, [x6, #0x50]\n" |
| 700 | "smlal v20.4s, v3.4h, v12.4h\n" |
| 701 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 702 | "smlal v24.4s, v6.4h, v12.4h\n" |
| 703 | "smlal v23.4s, v29.4h, v12.4h\n" |
| 704 | "ldr x21, [x5, #0xa0]\n" |
| 705 | "ldr x20, [x5, #0xa8]\n" |
| 706 | "smlal2 v15.4s, v30.8h, v27.8h\n" |
| 707 | "ldr d30, [x24, x3]\n" |
| 708 | "smlal v7.4s, v16.4h, v1.4h\n" |
| 709 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 710 | "smlal2 v5.4s, v3.8h, v12.8h\n" |
| 711 | "ldr d3, [x6, #0x58]\n" |
| 712 | "smlal2 v22.4s, v6.8h, v12.8h\n" |
| 713 | "ssubl v3.8h, v3.8b, v13.8b\n" |
| 714 | "smlal2 v19.4s, v29.8h, v12.8h\n" |
| 715 | "ldr d12, [x23, x3]\n" |
| 716 | "smlal v20.4s, v16.4h, v27.4h\n" |
| 717 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 718 | "smlal v24.4s, v28.4h, v27.4h\n" |
| 719 | "smlal v23.4s, v14.4h, v27.4h\n" |
| 720 | "ldr x13, [x5, #0xb0]\n" |
| 721 | "ldr x12, [x5, #0xb8]\n" |
| 722 | "smlal2 v15.4s, v16.8h, v1.8h\n" |
| 723 | "smlal v7.4s, v4.4h, v2.4h\n" |
| 724 | "ldr x11, [x5, #0xc0]\n" |
| 725 | "ldr x10, [x5, #0xc8]\n" |
| 726 | "smlal2 v5.4s, v16.8h, v27.8h\n" |
| 727 | "ldr d16, [x22, x3]\n" |
| 728 | "smlal2 v22.4s, v28.8h, v27.8h\n" |
| 729 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 730 | "smlal2 v19.4s, v14.8h, v27.8h\n" |
| 731 | "ldr d27, [x6, #0x60]\n" |
| 732 | "smlal v20.4s, v4.4h, v1.4h\n" |
| 733 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 734 | "smlal v24.4s, v14.4h, v1.4h\n" |
| 735 | "smlal v23.4s, v25.4h, v1.4h\n" |
| 736 | "ldr x9, [x5, #0xd0]\n" |
| 737 | "ldr x28, [x5, #0xd8]\n" |
| 738 | "smlal2 v15.4s, v4.8h, v2.8h\n" |
| 739 | "smlal v7.4s, v17.4h, v31.4h\n" |
| 740 | "ldr x27, [x5, #0xe0]\n" |
| 741 | "ldr x26, [x5, #0xe8]\n" |
| 742 | "smlal2 v5.4s, v4.8h, v1.8h\n" |
| 743 | "ldr d4, [x21, x3]\n" |
| 744 | "smlal2 v22.4s, v14.8h, v1.8h\n" |
| 745 | "ssubl v4.8h, v4.8b, v18.8b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 746 | "smlal2 v19.4s, v25.8h, v1.8h\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 747 | "ldr d1, [x6, #0x68]\n" |
| 748 | "smlal v20.4s, v17.4h, v2.4h\n" |
| 749 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 750 | "smlal v24.4s, v25.4h, v2.4h\n" |
| 751 | "smlal v23.4s, v10.4h, v2.4h\n" |
| 752 | "ldr x25, [x5, #0xf0]\n" |
| 753 | "ldr x24, [x5, #0xf8]\n" |
| 754 | "smlal2 v15.4s, v17.8h, v31.8h\n" |
| 755 | "smlal v7.4s, v6.4h, v8.4h\n" |
| 756 | "ldr x23, [x5, #0x100]\n" |
| 757 | "ldr x22, [x5, #0x108]\n" |
| 758 | "smlal2 v5.4s, v17.8h, v2.8h\n" |
| 759 | "ldr d17, [x20, x3]\n" |
| 760 | "smlal2 v22.4s, v25.8h, v2.8h\n" |
| 761 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 762 | "smlal2 v19.4s, v10.8h, v2.8h\n" |
| 763 | "ldr d2, [x6, #0x70]\n" |
| 764 | "smlal v20.4s, v6.4h, v31.4h\n" |
| 765 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 766 | "smlal v24.4s, v10.4h, v31.4h\n" |
| 767 | "smlal v23.4s, v9.4h, v31.4h\n" |
| 768 | "ldr x21, [x5, #0x110]\n" |
| 769 | "ldr x20, [x5, #0x118]\n" |
| 770 | "smlal2 v15.4s, v6.8h, v8.8h\n" |
| 771 | "smlal v7.4s, v28.4h, v21.4h\n" |
| 772 | "tst x1, #0x7\n" |
| 773 | "smlal2 v5.4s, v6.8h, v31.8h\n" |
| 774 | "ldr d6, [x13, x3]\n" |
| 775 | "smlal2 v22.4s, v10.8h, v31.8h\n" |
| 776 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 777 | "smlal2 v19.4s, v9.8h, v31.8h\n" |
| 778 | "ldr d31, [x6, #0x78]\n" |
| 779 | "smlal v20.4s, v29.4h, v8.4h\n" |
| 780 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 781 | "smlal v24.4s, v9.4h, v8.4h\n" |
| 782 | "smlal v23.4s, v30.4h, v8.4h\n" |
| 783 | "smlal2 v15.4s, v28.8h, v21.8h\n" |
| 784 | "ldr d28, [x12, x3]\n" |
| 785 | "smlal v7.4s, v14.4h, v3.4h\n" |
| 786 | "ssubl v28.8h, v28.8b, v18.8b\n" |
| 787 | "smlal2 v5.4s, v29.8h, v8.8h\n" |
| 788 | "ldr d29, [x6, #0x80]\n" |
| 789 | "smlal2 v22.4s, v9.8h, v8.8h\n" |
| 790 | "ssubl v29.8h, v29.8b, v13.8b\n" |
| 791 | "smlal2 v19.4s, v30.8h, v8.8h\n" |
| 792 | "ldr d8, [x11, x3]\n" |
| 793 | "smlal v20.4s, v14.4h, v21.4h\n" |
| 794 | "ssubl v8.8h, v8.8b, v18.8b\n" |
| 795 | "smlal v24.4s, v12.4h, v21.4h\n" |
| 796 | "smlal v23.4s, v16.4h, v21.4h\n" |
| 797 | "smlal2 v15.4s, v14.8h, v3.8h\n" |
| 798 | "smlal v7.4s, v25.4h, v27.4h\n" |
| 799 | "smlal2 v5.4s, v14.8h, v21.8h\n" |
| 800 | "ldr d14, [x10, x3]\n" |
| 801 | "smlal2 v22.4s, v12.8h, v21.8h\n" |
| 802 | "ssubl v14.8h, v14.8b, v18.8b\n" |
| 803 | "smlal2 v19.4s, v16.8h, v21.8h\n" |
| 804 | "ldr d21, [x6, #0x88]\n" |
| 805 | "smlal v20.4s, v25.4h, v3.4h\n" |
| 806 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 807 | "smlal v24.4s, v16.4h, v3.4h\n" |
| 808 | "smlal v23.4s, v4.4h, v3.4h\n" |
| 809 | "smlal2 v15.4s, v25.8h, v27.8h\n" |
| 810 | "smlal v7.4s, v10.4h, v1.4h\n" |
| 811 | "smlal2 v5.4s, v25.8h, v3.8h\n" |
| 812 | "ldr d25, [x9, x3]\n" |
| 813 | "smlal2 v22.4s, v16.8h, v3.8h\n" |
| 814 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 815 | "smlal2 v19.4s, v4.8h, v3.8h\n" |
| 816 | "ldr d3, [x6, #0x90]\n" |
| 817 | "smlal v20.4s, v10.4h, v27.4h\n" |
| 818 | "ssubl v3.8h, v3.8b, v13.8b\n" |
| 819 | "smlal v24.4s, v4.4h, v27.4h\n" |
| 820 | "smlal v23.4s, v17.4h, v27.4h\n" |
| 821 | "smlal2 v15.4s, v10.8h, v1.8h\n" |
| 822 | "smlal v7.4s, v9.4h, v2.4h\n" |
| 823 | "smlal2 v5.4s, v10.8h, v27.8h\n" |
| 824 | "ldr d10, [x28, x3]\n" |
| 825 | "smlal2 v22.4s, v4.8h, v27.8h\n" |
| 826 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 827 | "smlal2 v19.4s, v17.8h, v27.8h\n" |
| 828 | "ldr d27, [x6, #0x98]\n" |
| 829 | "smlal v20.4s, v9.4h, v1.4h\n" |
| 830 | "ssubl v27.8h, v27.8b, v13.8b\n" |
| 831 | "smlal v24.4s, v17.4h, v1.4h\n" |
| 832 | "smlal v23.4s, v6.4h, v1.4h\n" |
| 833 | "smlal2 v15.4s, v9.8h, v2.8h\n" |
| 834 | "smlal v7.4s, v12.4h, v31.4h\n" |
| 835 | "smlal2 v5.4s, v9.8h, v1.8h\n" |
| 836 | "ldr d9, [x27, x3]\n" |
| 837 | "smlal2 v22.4s, v17.8h, v1.8h\n" |
| 838 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 839 | "smlal2 v19.4s, v6.8h, v1.8h\n" |
| 840 | "ldr d1, [x6, #0xa0]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 841 | "smlal v20.4s, v30.4h, v2.4h\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 842 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 843 | "smlal v24.4s, v6.4h, v2.4h\n" |
| 844 | "smlal v23.4s, v28.4h, v2.4h\n" |
| 845 | "smlal2 v15.4s, v12.8h, v31.8h\n" |
| 846 | "ldr d12, [x26, x3]\n" |
| 847 | "smlal v7.4s, v16.4h, v29.4h\n" |
| 848 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 849 | "smlal2 v5.4s, v30.8h, v2.8h\n" |
| 850 | "ldr d30, [x6, #0xa8]\n" |
| 851 | "smlal2 v22.4s, v6.8h, v2.8h\n" |
| 852 | "ssubl v30.8h, v30.8b, v13.8b\n" |
| 853 | "smlal2 v19.4s, v28.8h, v2.8h\n" |
| 854 | "ldr d2, [x25, x3]\n" |
| 855 | "smlal v20.4s, v16.4h, v31.4h\n" |
| 856 | "ssubl v2.8h, v2.8b, v18.8b\n" |
| 857 | "smlal v24.4s, v8.4h, v31.4h\n" |
| 858 | "smlal v23.4s, v14.4h, v31.4h\n" |
| 859 | "smlal2 v15.4s, v16.8h, v29.8h\n" |
| 860 | "smlal v7.4s, v4.4h, v21.4h\n" |
| 861 | "smlal2 v5.4s, v16.8h, v31.8h\n" |
| 862 | "ldr d16, [x24, x3]\n" |
| 863 | "smlal2 v22.4s, v8.8h, v31.8h\n" |
| 864 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 865 | "smlal2 v19.4s, v14.8h, v31.8h\n" |
| 866 | "ldr d31, [x6, #0xb0]\n" |
| 867 | "smlal v20.4s, v4.4h, v29.4h\n" |
| 868 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 869 | "smlal v24.4s, v14.4h, v29.4h\n" |
| 870 | "smlal v23.4s, v25.4h, v29.4h\n" |
| 871 | "smlal2 v15.4s, v4.8h, v21.8h\n" |
| 872 | "smlal v7.4s, v17.4h, v3.4h\n" |
| 873 | "smlal2 v5.4s, v4.8h, v29.8h\n" |
| 874 | "ldr d4, [x23, x3]\n" |
| 875 | "smlal2 v22.4s, v14.8h, v29.8h\n" |
| 876 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 877 | "smlal2 v19.4s, v25.8h, v29.8h\n" |
| 878 | "ldr d29, [x6, #0xb8]\n" |
| 879 | "smlal v20.4s, v17.4h, v21.4h\n" |
| 880 | "ssubl v29.8h, v29.8b, v13.8b\n" |
| 881 | "smlal v24.4s, v25.4h, v21.4h\n" |
| 882 | "smlal v23.4s, v10.4h, v21.4h\n" |
| 883 | "smlal2 v15.4s, v17.8h, v3.8h\n" |
| 884 | "smlal v7.4s, v6.4h, v27.4h\n" |
| 885 | "smlal2 v5.4s, v17.8h, v21.8h\n" |
| 886 | "ldr d17, [x22, x3]\n" |
| 887 | "smlal2 v22.4s, v25.8h, v21.8h\n" |
| 888 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 889 | "smlal2 v19.4s, v10.8h, v21.8h\n" |
| 890 | "ldr d21, [x6, #0xc0]\n" |
| 891 | "smlal v20.4s, v6.4h, v3.4h\n" |
| 892 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 893 | "smlal v24.4s, v10.4h, v3.4h\n" |
| 894 | "smlal v23.4s, v9.4h, v3.4h\n" |
| 895 | "smlal2 v15.4s, v6.8h, v27.8h\n" |
| 896 | "smlal v7.4s, v8.4h, v1.4h\n" |
| 897 | "smlal2 v5.4s, v6.8h, v3.8h\n" |
| 898 | "ldr d6, [x21, x3]\n" |
| 899 | "smlal2 v22.4s, v10.8h, v3.8h\n" |
| 900 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 901 | "smlal2 v19.4s, v9.8h, v3.8h\n" |
| 902 | "ldr d3, [x20, x3]\n" |
| 903 | "smlal v20.4s, v28.4h, v27.4h\n" |
| 904 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 905 | "smlal v24.4s, v9.4h, v27.4h\n" |
| 906 | "smlal v23.4s, v12.4h, v27.4h\n" |
| 907 | "add x3, x3, #0x8\n" |
| 908 | "smlal2 v15.4s, v8.8h, v1.8h\n" |
| 909 | "ldr q8, [x7, #0x0]\n" |
| 910 | "smlal v7.4s, v14.4h, v30.4h\n" |
| 911 | "smlal2 v5.4s, v28.8h, v27.8h\n" |
| 912 | "ldr q28, [x8, #0x0]\n" |
| 913 | "smlal2 v22.4s, v9.8h, v27.8h\n" |
| 914 | "smlal2 v19.4s, v12.8h, v27.8h\n" |
| 915 | "ldr q27, [x7, #0x10]\n" |
| 916 | "smlal v20.4s, v14.4h, v1.4h\n" |
| 917 | "add x7, x7, #0x20\n" |
| 918 | "smlal v24.4s, v2.4h, v1.4h\n" |
| 919 | "smlal v23.4s, v16.4h, v1.4h\n" |
| 920 | "smlal2 v15.4s, v14.8h, v30.8h\n" |
| 921 | "smlal v7.4s, v25.4h, v31.4h\n" |
| 922 | "smlal2 v5.4s, v14.8h, v1.8h\n" |
| 923 | "ldr q14, [x8, #0x10]\n" |
| 924 | "smlal2 v22.4s, v2.8h, v1.8h\n" |
| 925 | "add x8, x8, #0x20\n" |
| 926 | "smlal2 v19.4s, v16.8h, v1.8h\n" |
| 927 | "smlal v20.4s, v25.4h, v30.4h\n" |
| 928 | "smlal v24.4s, v16.4h, v30.4h\n" |
| 929 | "smlal v23.4s, v4.4h, v30.4h\n" |
| 930 | "smlal2 v15.4s, v25.8h, v31.8h\n" |
| 931 | "smlal v7.4s, v10.4h, v29.4h\n" |
| 932 | "smlal2 v5.4s, v25.8h, v30.8h\n" |
| 933 | "smlal2 v22.4s, v16.8h, v30.8h\n" |
| 934 | "smlal2 v19.4s, v4.8h, v30.8h\n" |
| 935 | "smlal v20.4s, v10.4h, v31.4h\n" |
| 936 | "smlal v24.4s, v4.4h, v31.4h\n" |
| 937 | "smlal v23.4s, v17.4h, v31.4h\n" |
| 938 | "smlal2 v15.4s, v10.8h, v29.8h\n" |
| 939 | "smlal v7.4s, v9.4h, v21.4h\n" |
| 940 | "sqrdmulh v7.4s, v7.4s, v8.4s\n" |
| 941 | "smlal2 v5.4s, v10.8h, v31.8h\n" |
| 942 | "smlal2 v22.4s, v4.8h, v31.8h\n" |
| 943 | "and v4.16b, v7.16b, v28.16b\n" |
| 944 | "smlal2 v19.4s, v17.8h, v31.8h\n" |
| 945 | "smlal v20.4s, v9.4h, v29.4h\n" |
| 946 | "sshr v4.4s, v4.4s, #0x1f\n" |
| 947 | "smlal v24.4s, v17.4h, v29.4h\n" |
| 948 | "smlal v23.4s, v6.4h, v29.4h\n" |
| 949 | "sqadd v7.4s, v7.4s, v4.4s\n" |
| 950 | "smlal2 v15.4s, v9.8h, v21.8h\n" |
| 951 | "smlal2 v5.4s, v9.8h, v29.8h\n" |
| 952 | "sqrdmulh v15.4s, v15.4s, v27.4s\n" |
| 953 | "smlal2 v22.4s, v17.8h, v29.8h\n" |
| 954 | "smlal2 v19.4s, v6.8h, v29.8h\n" |
| 955 | "and v30.16b, v15.16b, v14.16b\n" |
| 956 | "smlal v20.4s, v12.4h, v21.4h\n" |
| 957 | "smlal v24.4s, v6.4h, v21.4h\n" |
| 958 | "sqrdmulh v20.4s, v20.4s, v8.4s\n" |
| 959 | "smlal v23.4s, v3.4h, v21.4h\n" |
| 960 | "smlal2 v5.4s, v12.8h, v21.8h\n" |
| 961 | "sqrdmulh v24.4s, v24.4s, v8.4s\n" |
| 962 | "smlal2 v22.4s, v6.8h, v21.8h\n" |
| 963 | "smlal2 v19.4s, v3.8h, v21.8h\n" |
| 964 | "sqrdmulh v23.4s, v23.4s, v8.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 965 | "sshr v30.4s, v30.4s, #0x1f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 966 | "and v3.16b, v20.16b, v28.16b\n" |
| 967 | "sqrdmulh v5.4s, v5.4s, v27.4s\n" |
| 968 | "and v25.16b, v24.16b, v28.16b\n" |
| 969 | "sqrdmulh v22.4s, v22.4s, v27.4s\n" |
| 970 | "and v16.16b, v23.16b, v28.16b\n" |
| 971 | "sqrdmulh v19.4s, v19.4s, v27.4s\n" |
| 972 | "sqadd v15.4s, v15.4s, v30.4s\n" |
| 973 | "sshr v3.4s, v3.4s, #0x1f\n" |
| 974 | "and v4.16b, v5.16b, v14.16b\n" |
| 975 | "sshr v25.4s, v25.4s, #0x1f\n" |
| 976 | "and v10.16b, v22.16b, v14.16b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 977 | "sshr v16.4s, v16.4s, #0x1f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 978 | "and v12.16b, v19.16b, v14.16b\n" |
| 979 | "sqadd v20.4s, v20.4s, v3.4s\n" |
| 980 | "sshr v4.4s, v4.4s, #0x1f\n" |
| 981 | "sqadd v24.4s, v24.4s, v25.4s\n" |
| 982 | "sshr v10.4s, v10.4s, #0x1f\n" |
| 983 | "sqadd v23.4s, v23.4s, v16.4s\n" |
| 984 | "sshr v12.4s, v12.4s, #0x1f\n" |
| 985 | "srshl v7.4s, v7.4s, v28.4s\n" |
| 986 | "srshl v20.4s, v20.4s, v28.4s\n" |
| 987 | "sqadd v5.4s, v5.4s, v4.4s\n" |
| 988 | "srshl v24.4s, v24.4s, v28.4s\n" |
| 989 | "sqadd v22.4s, v22.4s, v10.4s\n" |
| 990 | "srshl v23.4s, v23.4s, v28.4s\n" |
| 991 | "sqadd v19.4s, v19.4s, v12.4s\n" |
| 992 | "srshl v15.4s, v15.4s, v14.4s\n" |
| 993 | "sqxtn v7.4h, v7.4s\n" |
| 994 | "srshl v5.4s, v5.4s, v14.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 995 | "sqxtn v20.4h, v20.4s\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 996 | "srshl v22.4s, v22.4s, v14.4s\n" |
| 997 | "sqxtn v24.4h, v24.4s\n" |
| 998 | "srshl v19.4s, v19.4s, v14.4s\n" |
| 999 | "sqxtn v23.4h, v23.4s\n" |
| 1000 | "sqxtn2 v7.8h, v15.4s\n" |
| 1001 | "sqxtn2 v20.8h, v5.4s\n" |
| 1002 | "sqxtn2 v24.8h, v22.4s\n" |
| 1003 | "sqxtn2 v23.8h, v19.4s\n" |
| 1004 | "sqadd v7.8h, v7.8h, v26.8h\n" |
| 1005 | "sqadd v20.8h, v20.8h, v26.8h\n" |
| 1006 | "sqadd v24.8h, v24.8h, v26.8h\n" |
| 1007 | "sqadd v23.8h, v23.8h, v26.8h\n" |
| 1008 | "smax v7.8h, v7.8h, v11.8h\n" |
| 1009 | "smax v20.8h, v20.8h, v11.8h\n" |
| 1010 | "smax v24.8h, v24.8h, v11.8h\n" |
| 1011 | "smax v23.8h, v23.8h, v11.8h\n" |
| 1012 | "smin v7.8h, v7.8h, v0.8h\n" |
| 1013 | "smin v20.8h, v20.8h, v0.8h\n" |
| 1014 | "smin v24.8h, v24.8h, v0.8h\n" |
| 1015 | "smin v23.8h, v23.8h, v0.8h\n" |
| 1016 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
| 1017 | "str d7, [x17, x4]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1018 | "uzp1 v20.16b, v20.16b, v20.16b\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1019 | "uzp1 v24.16b, v24.16b, v24.16b\n" |
| 1020 | "str d20, [x16, x4]\n" |
| 1021 | "uzp1 v23.16b, v23.16b, v23.16b\n" |
| 1022 | "str d24, [x15, x4]\n" |
| 1023 | "str d23, [x14, x4]\n" |
| 1024 | "add x4, x4, #0x8\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1025 | "beq 124f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1026 | "add x6, x6, #0xc8\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1027 | "3:" // Oddments |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1028 | "ldr x20, [%x[params], %[offsetof_Params_bias]]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1029 | "tbz x1, #2, 5f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1030 | "ld1 { v7.4s }, [x20], #0x10\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1031 | "tbz x1, #1, 4f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1032 | "ld1 { v15.d }[0], [x20], #0x8\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1033 | "tbz x1, #0, 7f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1034 | "ld1 { v15.s }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1035 | "b 7f\n" |
| 1036 | "4:" // Oddments: Load bias: Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1037 | "tbz x1, #0, 7f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1038 | "ld1 { v15.s }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1039 | "b 7f\n" |
| 1040 | "5:" // Oddments: Load bias: Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1041 | "tbz x1, #1, 6f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1042 | "ld1 { v7.d }[0], [x20], #0x8\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1043 | "tbz x1, #0, 7f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1044 | "ld1 { v7.s }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1045 | "b 7f\n" |
| 1046 | "6:" // Oddments: Load bias: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1047 | "tbz x1, #0, 7f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1048 | "ld1 { v7.s }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1049 | "7:" // Oddments: Load bias: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1050 | "ldr d6, [x6, #0x0]\n" |
| 1051 | "ldr d14, [x6, #0x8]\n" |
| 1052 | "mov v20.16b, v7.16b\n" |
| 1053 | "mov v5.16b, v15.16b\n" |
| 1054 | "ldr d10, [x6, #0x10]\n" |
| 1055 | "ldr d21, [x6, #0x18]\n" |
| 1056 | "mov v24.16b, v7.16b\n" |
| 1057 | "mov v22.16b, v15.16b\n" |
| 1058 | "ldr d12, [x6, #0x20]\n" |
| 1059 | "ldp x9, x28, [x5, #0x0]\n" |
| 1060 | "mov v23.16b, v7.16b\n" |
| 1061 | "mov v19.16b, v15.16b\n" |
| 1062 | "ldp x27, x26, [x5, #0x10]\n" |
| 1063 | "ldp x25, x24, [x5, #0x20]\n" |
| 1064 | "ssubl v6.8h, v6.8b, v13.8b\n" |
| 1065 | "ssubl v14.8h, v14.8b, v13.8b\n" |
| 1066 | "ldp x23, x22, [x5, #0x30]\n" |
| 1067 | "ldp x21, x20, [x5, #0x40]\n" |
| 1068 | "ssubl v10.8h, v10.8b, v13.8b\n" |
| 1069 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 1070 | "ssubl v12.8h, v12.8b, v13.8b\n" |
| 1071 | "add x9, x9, x3\n" |
| 1072 | "add x28, x28, x3\n" |
| 1073 | "add x27, x27, x3\n" |
| 1074 | "add x26, x26, x3\n" |
| 1075 | "add x25, x25, x3\n" |
| 1076 | "add x24, x24, x3\n" |
| 1077 | "add x23, x23, x3\n" |
| 1078 | "add x22, x22, x3\n" |
| 1079 | "add x21, x21, x3\n" |
| 1080 | "add x20, x20, x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1081 | "tbz x1, #2, 9f\n" |
| 1082 | "ld1 { v31.s }[0], [x9], #0x4\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1083 | "ld1 { v17.s }[0], [x28], #0x4\n" |
| 1084 | "ld1 { v30.s }[0], [x27], #0x4\n" |
| 1085 | "ld1 { v16.s }[0], [x26], #0x4\n" |
| 1086 | "ld1 { v3.s }[0], [x25], #0x4\n" |
| 1087 | "ld1 { v4.s }[0], [x24], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1088 | "ld1 { v25.s }[0], [x23], #0x4\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1089 | "ld1 { v9.s }[0], [x22], #0x4\n" |
| 1090 | "ld1 { v29.s }[0], [x21], #0x4\n" |
| 1091 | "ld1 { v28.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1092 | "tbz x1, #1, 8f\n" |
| 1093 | "ld1 { v31.h }[2], [x9], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1094 | "ld1 { v17.h }[2], [x28], #0x2\n" |
| 1095 | "ld1 { v30.h }[2], [x27], #0x2\n" |
| 1096 | "ld1 { v16.h }[2], [x26], #0x2\n" |
| 1097 | "ld1 { v3.h }[2], [x25], #0x2\n" |
| 1098 | "ld1 { v4.h }[2], [x24], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1099 | "ld1 { v25.h }[2], [x23], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1100 | "ld1 { v9.h }[2], [x22], #0x2\n" |
| 1101 | "ld1 { v29.h }[2], [x21], #0x2\n" |
| 1102 | "ld1 { v28.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1103 | "tbz x1, #0, 11f\n" |
| 1104 | "ld1 { v31.b }[6], [x9]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1105 | "ld1 { v17.b }[6], [x28]\n" |
| 1106 | "ld1 { v30.b }[6], [x27]\n" |
| 1107 | "ld1 { v16.b }[6], [x26]\n" |
| 1108 | "ld1 { v3.b }[6], [x25]\n" |
| 1109 | "ld1 { v4.b }[6], [x24]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1110 | "ld1 { v25.b }[6], [x23]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1111 | "ld1 { v9.b }[6], [x22]\n" |
| 1112 | "ld1 { v29.b }[6], [x21]\n" |
| 1113 | "ld1 { v28.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1114 | "b 11f\n" |
| 1115 | "8:" // Oddments: Initial loads: Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1116 | "tbz x1, #0, 11f\n" |
| 1117 | "ld1 { v31.b }[4], [x9]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1118 | "ld1 { v17.b }[4], [x28]\n" |
| 1119 | "ld1 { v30.b }[4], [x27]\n" |
| 1120 | "ld1 { v16.b }[4], [x26]\n" |
| 1121 | "ld1 { v3.b }[4], [x25]\n" |
| 1122 | "ld1 { v4.b }[4], [x24]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1123 | "ld1 { v25.b }[4], [x23]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1124 | "ld1 { v9.b }[4], [x22]\n" |
| 1125 | "ld1 { v29.b }[4], [x21]\n" |
| 1126 | "ld1 { v28.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1127 | "b 11f\n" |
| 1128 | "9:" // Oddments: Initial loads: Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1129 | "tbz x1, #1, 10f\n" |
| 1130 | "ld1 { v31.h }[0], [x9], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1131 | "ld1 { v17.h }[0], [x28], #0x2\n" |
| 1132 | "ld1 { v30.h }[0], [x27], #0x2\n" |
| 1133 | "ld1 { v16.h }[0], [x26], #0x2\n" |
| 1134 | "ld1 { v3.h }[0], [x25], #0x2\n" |
| 1135 | "ld1 { v4.h }[0], [x24], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1136 | "ld1 { v25.h }[0], [x23], #0x2\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1137 | "ld1 { v9.h }[0], [x22], #0x2\n" |
| 1138 | "ld1 { v29.h }[0], [x21], #0x2\n" |
| 1139 | "ld1 { v28.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1140 | "tbz x1, #0, 11f\n" |
| 1141 | "ld1 { v31.b }[2], [x9]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1142 | "ld1 { v17.b }[2], [x28]\n" |
| 1143 | "ld1 { v30.b }[2], [x27]\n" |
| 1144 | "ld1 { v16.b }[2], [x26]\n" |
| 1145 | "ld1 { v3.b }[2], [x25]\n" |
| 1146 | "ld1 { v4.b }[2], [x24]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1147 | "ld1 { v25.b }[2], [x23]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1148 | "ld1 { v9.b }[2], [x22]\n" |
| 1149 | "ld1 { v29.b }[2], [x21]\n" |
| 1150 | "ld1 { v28.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1151 | "b 11f\n" |
| 1152 | "10:" // Oddments: Initial loads: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1153 | "tbz x1, #0, 11f\n" |
| 1154 | "ld1 { v31.b }[0], [x9]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1155 | "ld1 { v17.b }[0], [x28]\n" |
| 1156 | "ld1 { v30.b }[0], [x27]\n" |
| 1157 | "ld1 { v16.b }[0], [x26]\n" |
| 1158 | "ld1 { v3.b }[0], [x25]\n" |
| 1159 | "ld1 { v4.b }[0], [x24]\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1160 | "ld1 { v25.b }[0], [x23]\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1161 | "ld1 { v9.b }[0], [x22]\n" |
| 1162 | "ld1 { v29.b }[0], [x21]\n" |
| 1163 | "ld1 { v28.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1164 | "11:" // Oddments: Initial loads: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1165 | "ssubl v31.8h, v31.8b, v18.8b\n" |
| 1166 | "ssubl v17.8h, v17.8b, v18.8b\n" |
| 1167 | "smlal v7.4s, v31.4h, v6.4h\n" |
| 1168 | "ldr x20, [x5, #0x50]\n" |
| 1169 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 1170 | "smlal2 v15.4s, v31.8h, v6.8h\n" |
| 1171 | "smlal v20.4s, v17.4h, v6.4h\n" |
| 1172 | "smlal2 v5.4s, v17.8h, v6.8h\n" |
| 1173 | "smlal v24.4s, v30.4h, v6.4h\n" |
| 1174 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 1175 | "add x20, x20, x3\n" |
| 1176 | "smlal2 v22.4s, v30.8h, v6.8h\n" |
| 1177 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 1178 | "smlal v23.4s, v16.4h, v6.4h\n" |
| 1179 | "smlal2 v19.4s, v16.8h, v6.8h\n" |
| 1180 | "smlal v7.4s, v17.4h, v14.4h\n" |
| 1181 | "ssubl v4.8h, v4.8b, v18.8b\n" |
| 1182 | "smlal2 v15.4s, v17.8h, v14.8h\n" |
| 1183 | "smlal v20.4s, v3.4h, v14.4h\n" |
| 1184 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 1185 | "smlal2 v5.4s, v3.8h, v14.8h\n" |
| 1186 | "smlal v24.4s, v16.4h, v14.4h\n" |
| 1187 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 1188 | "smlal2 v22.4s, v16.8h, v14.8h\n" |
| 1189 | "ssubl v29.8h, v29.8b, v18.8b\n" |
| 1190 | "smlal v23.4s, v4.4h, v14.4h\n" |
| 1191 | "ssubl v28.8h, v28.8b, v18.8b\n" |
| 1192 | "smlal2 v19.4s, v4.8h, v14.8h\n" |
| 1193 | "smlal v7.4s, v3.4h, v10.4h\n" |
| 1194 | "smlal2 v15.4s, v3.8h, v10.8h\n" |
| 1195 | "smlal v20.4s, v25.4h, v10.4h\n" |
| 1196 | "smlal2 v5.4s, v25.8h, v10.8h\n" |
| 1197 | "smlal v24.4s, v4.4h, v10.4h\n" |
| 1198 | "smlal2 v22.4s, v4.8h, v10.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1199 | "tbz x1, #2, 13f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1200 | "ld1 { v27.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1201 | "tbz x1, #1, 12f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1202 | "ld1 { v27.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1203 | "tbz x1, #0, 15f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1204 | "ld1 { v27.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1205 | "b 15f\n" |
| 1206 | "12:" // Oddments: Load (1, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1207 | "tbz x1, #0, 15f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1208 | "ld1 { v27.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1209 | "b 15f\n" |
| 1210 | "13:" // Oddments: Load (1, 3): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1211 | "tbz x1, #1, 14f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1212 | "ld1 { v27.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1213 | "tbz x1, #0, 15f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1214 | "ld1 { v27.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1215 | "b 15f\n" |
| 1216 | "14:" // Oddments: Load (1, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1217 | "tbz x1, #0, 15f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1218 | "ld1 { v27.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1219 | "15:" // Oddments: Load (1, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1220 | "ssubl v27.8h, v27.8b, v18.8b\n" |
| 1221 | "ldr x20, [x5, #0x58]\n" |
| 1222 | "smlal v23.4s, v27.4h, v10.4h\n" |
| 1223 | "smlal2 v19.4s, v27.8h, v10.8h\n" |
| 1224 | "smlal v7.4s, v25.4h, v21.4h\n" |
| 1225 | "smlal2 v15.4s, v25.8h, v21.8h\n" |
| 1226 | "add x20, x20, x3\n" |
| 1227 | "smlal v20.4s, v9.4h, v21.4h\n" |
| 1228 | "smlal2 v5.4s, v9.8h, v21.8h\n" |
| 1229 | "smlal v24.4s, v27.4h, v21.4h\n" |
| 1230 | "smlal2 v22.4s, v27.8h, v21.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1231 | "tbz x1, #2, 17f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1232 | "ld1 { v6.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1233 | "tbz x1, #1, 16f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1234 | "ld1 { v6.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1235 | "tbz x1, #0, 19f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1236 | "ld1 { v6.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1237 | "b 19f\n" |
| 1238 | "16:" // Oddments: Load (1, 4): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1239 | "tbz x1, #0, 19f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1240 | "ld1 { v6.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1241 | "b 19f\n" |
| 1242 | "17:" // Oddments: Load (1, 4): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1243 | "tbz x1, #1, 18f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1244 | "ld1 { v6.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1245 | "tbz x1, #0, 19f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1246 | "ld1 { v6.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1247 | "b 19f\n" |
| 1248 | "18:" // Oddments: Load (1, 4): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1249 | "tbz x1, #0, 19f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1250 | "ld1 { v6.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1251 | "19:" // Oddments: Load (1, 4): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1252 | "ssubl v6.8h, v6.8b, v18.8b\n" |
| 1253 | "ldr x20, [x5, #0x60]\n" |
| 1254 | "smlal v23.4s, v6.4h, v21.4h\n" |
| 1255 | "smlal2 v19.4s, v6.8h, v21.8h\n" |
| 1256 | "smlal v7.4s, v9.4h, v12.4h\n" |
| 1257 | "smlal2 v15.4s, v9.8h, v12.8h\n" |
| 1258 | "add x20, x20, x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1259 | "tbz x1, #2, 21f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1260 | "ld1 { v9.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1261 | "tbz x1, #1, 20f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1262 | "ld1 { v9.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1263 | "tbz x1, #0, 23f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1264 | "ld1 { v9.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1265 | "b 23f\n" |
| 1266 | "20:" // Oddments: Load (0, 5): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1267 | "tbz x1, #0, 23f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1268 | "ld1 { v9.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1269 | "b 23f\n" |
| 1270 | "21:" // Oddments: Load (0, 5): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1271 | "tbz x1, #1, 22f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1272 | "ld1 { v9.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1273 | "tbz x1, #0, 23f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1274 | "ld1 { v9.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1275 | "b 23f\n" |
| 1276 | "22:" // Oddments: Load (0, 5): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1277 | "tbz x1, #0, 23f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1278 | "ld1 { v9.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1279 | "23:" // Oddments: Load (0, 5): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1280 | "ldr d14, [x6, #0x28]\n" |
| 1281 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 1282 | "smlal v20.4s, v9.4h, v12.4h\n" |
| 1283 | "smlal2 v5.4s, v9.8h, v12.8h\n" |
| 1284 | "smlal v24.4s, v6.4h, v12.4h\n" |
| 1285 | "smlal2 v22.4s, v6.8h, v12.8h\n" |
| 1286 | "ssubl v14.8h, v14.8b, v13.8b\n" |
| 1287 | "ldr x20, [x5, #0x68]\n" |
| 1288 | "smlal v23.4s, v29.4h, v12.4h\n" |
| 1289 | "smlal2 v19.4s, v29.8h, v12.8h\n" |
| 1290 | "add x20, x20, x3\n" |
| 1291 | "smlal v7.4s, v30.4h, v14.4h\n" |
| 1292 | "smlal2 v15.4s, v30.8h, v14.8h\n" |
| 1293 | "smlal v20.4s, v16.4h, v14.4h\n" |
| 1294 | "smlal2 v5.4s, v16.8h, v14.8h\n" |
| 1295 | "smlal v24.4s, v28.4h, v14.4h\n" |
| 1296 | "smlal2 v22.4s, v28.8h, v14.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1297 | "tbz x1, #2, 25f\n" |
| 1298 | "ld1 { v25.s }[0], [x20], #0x4\n" |
| 1299 | "tbz x1, #1, 24f\n" |
| 1300 | "ld1 { v25.h }[2], [x20], #0x2\n" |
| 1301 | "tbz x1, #0, 27f\n" |
| 1302 | "ld1 { v25.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1303 | "b 27f\n" |
| 1304 | "24:" // Oddments: Load (2, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1305 | "tbz x1, #0, 27f\n" |
| 1306 | "ld1 { v25.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1307 | "b 27f\n" |
| 1308 | "25:" // Oddments: Load (2, 1): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1309 | "tbz x1, #1, 26f\n" |
| 1310 | "ld1 { v25.h }[0], [x20], #0x2\n" |
| 1311 | "tbz x1, #0, 27f\n" |
| 1312 | "ld1 { v25.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1313 | "b 27f\n" |
| 1314 | "26:" // Oddments: Load (2, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1315 | "tbz x1, #0, 27f\n" |
| 1316 | "ld1 { v25.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1317 | "27:" // Oddments: Load (2, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1318 | "ldr d21, [x6, #0x30]\n" |
| 1319 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 1320 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 1321 | "ldr x20, [x5, #0x70]\n" |
| 1322 | "smlal v23.4s, v25.4h, v14.4h\n" |
| 1323 | "smlal2 v19.4s, v25.8h, v14.8h\n" |
| 1324 | "add x20, x20, x3\n" |
| 1325 | "smlal v7.4s, v16.4h, v21.4h\n" |
| 1326 | "smlal2 v15.4s, v16.8h, v21.8h\n" |
| 1327 | "smlal v20.4s, v4.4h, v21.4h\n" |
| 1328 | "smlal2 v5.4s, v4.8h, v21.8h\n" |
| 1329 | "smlal v24.4s, v25.4h, v21.4h\n" |
| 1330 | "smlal2 v22.4s, v25.8h, v21.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1331 | "tbz x1, #2, 29f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1332 | "ld1 { v10.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1333 | "tbz x1, #1, 28f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1334 | "ld1 { v10.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1335 | "tbz x1, #0, 31f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1336 | "ld1 { v10.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1337 | "b 31f\n" |
| 1338 | "28:" // Oddments: Load (2, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1339 | "tbz x1, #0, 31f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1340 | "ld1 { v10.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1341 | "b 31f\n" |
| 1342 | "29:" // Oddments: Load (2, 2): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1343 | "tbz x1, #1, 30f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1344 | "ld1 { v10.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1345 | "tbz x1, #0, 31f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1346 | "ld1 { v10.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1347 | "b 31f\n" |
| 1348 | "30:" // Oddments: Load (2, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1349 | "tbz x1, #0, 31f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1350 | "ld1 { v10.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1351 | "31:" // Oddments: Load (2, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1352 | "ldr d9, [x6, #0x38]\n" |
| 1353 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 1354 | "ssubl v9.8h, v9.8b, v13.8b\n" |
| 1355 | "ldr x20, [x5, #0x78]\n" |
| 1356 | "smlal v23.4s, v10.4h, v21.4h\n" |
| 1357 | "smlal2 v19.4s, v10.8h, v21.8h\n" |
| 1358 | "add x20, x20, x3\n" |
| 1359 | "smlal v7.4s, v4.4h, v9.4h\n" |
| 1360 | "smlal2 v15.4s, v4.8h, v9.8h\n" |
| 1361 | "smlal v20.4s, v27.4h, v9.4h\n" |
| 1362 | "smlal2 v5.4s, v27.8h, v9.8h\n" |
| 1363 | "smlal v24.4s, v10.4h, v9.4h\n" |
| 1364 | "smlal2 v22.4s, v10.8h, v9.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1365 | "tbz x1, #2, 33f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1366 | "ld1 { v12.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1367 | "tbz x1, #1, 32f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1368 | "ld1 { v12.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1369 | "tbz x1, #0, 35f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1370 | "ld1 { v12.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1371 | "b 35f\n" |
| 1372 | "32:" // Oddments: Load (2, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1373 | "tbz x1, #0, 35f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1374 | "ld1 { v12.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1375 | "b 35f\n" |
| 1376 | "33:" // Oddments: Load (2, 3): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1377 | "tbz x1, #1, 34f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1378 | "ld1 { v12.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1379 | "tbz x1, #0, 35f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1380 | "ld1 { v12.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1381 | "b 35f\n" |
| 1382 | "34:" // Oddments: Load (2, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1383 | "tbz x1, #0, 35f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1384 | "ld1 { v12.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1385 | "35:" // Oddments: Load (2, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1386 | "ldr d31, [x6, #0x40]\n" |
| 1387 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 1388 | "ssubl v31.8h, v31.8b, v13.8b\n" |
| 1389 | "ldr x20, [x5, #0x80]\n" |
| 1390 | "smlal v23.4s, v12.4h, v9.4h\n" |
| 1391 | "smlal2 v19.4s, v12.8h, v9.8h\n" |
| 1392 | "add x20, x20, x3\n" |
| 1393 | "smlal v7.4s, v27.4h, v31.4h\n" |
| 1394 | "smlal2 v15.4s, v27.8h, v31.8h\n" |
| 1395 | "smlal v20.4s, v6.4h, v31.4h\n" |
| 1396 | "smlal2 v5.4s, v6.8h, v31.8h\n" |
| 1397 | "smlal v24.4s, v12.4h, v31.4h\n" |
| 1398 | "smlal2 v22.4s, v12.8h, v31.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1399 | "tbz x1, #2, 37f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1400 | "ld1 { v8.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1401 | "tbz x1, #1, 36f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1402 | "ld1 { v8.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1403 | "tbz x1, #0, 39f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1404 | "ld1 { v8.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1405 | "b 39f\n" |
| 1406 | "36:" // Oddments: Load (2, 4): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1407 | "tbz x1, #0, 39f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1408 | "ld1 { v8.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1409 | "b 39f\n" |
| 1410 | "37:" // Oddments: Load (2, 4): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1411 | "tbz x1, #1, 38f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1412 | "ld1 { v8.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1413 | "tbz x1, #0, 39f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1414 | "ld1 { v8.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1415 | "b 39f\n" |
| 1416 | "38:" // Oddments: Load (2, 4): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1417 | "tbz x1, #0, 39f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1418 | "ld1 { v8.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1419 | "39:" // Oddments: Load (2, 4): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1420 | "ldr d16, [x6, #0x48]\n" |
| 1421 | "ssubl v8.8h, v8.8b, v18.8b\n" |
| 1422 | "ssubl v16.8h, v16.8b, v13.8b\n" |
| 1423 | "ldr x20, [x5, #0x88]\n" |
| 1424 | "smlal v23.4s, v8.4h, v31.4h\n" |
| 1425 | "smlal2 v19.4s, v8.8h, v31.8h\n" |
| 1426 | "add x20, x20, x3\n" |
| 1427 | "smlal v7.4s, v6.4h, v16.4h\n" |
| 1428 | "smlal2 v15.4s, v6.8h, v16.8h\n" |
| 1429 | "smlal v20.4s, v29.4h, v16.4h\n" |
| 1430 | "smlal2 v5.4s, v29.8h, v16.8h\n" |
| 1431 | "smlal v24.4s, v8.4h, v16.4h\n" |
| 1432 | "smlal2 v22.4s, v8.8h, v16.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1433 | "tbz x1, #2, 41f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1434 | "ld1 { v27.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1435 | "tbz x1, #1, 40f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1436 | "ld1 { v27.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1437 | "tbz x1, #0, 43f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1438 | "ld1 { v27.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1439 | "b 43f\n" |
| 1440 | "40:" // Oddments: Load (2, 5): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1441 | "tbz x1, #0, 43f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1442 | "ld1 { v27.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1443 | "b 43f\n" |
| 1444 | "41:" // Oddments: Load (2, 5): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1445 | "tbz x1, #1, 42f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1446 | "ld1 { v27.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1447 | "tbz x1, #0, 43f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1448 | "ld1 { v27.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1449 | "b 43f\n" |
| 1450 | "42:" // Oddments: Load (2, 5): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1451 | "tbz x1, #0, 43f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1452 | "ld1 { v27.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1453 | "43:" // Oddments: Load (2, 5): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1454 | "ldr d21, [x6, #0x50]\n" |
| 1455 | "ssubl v27.8h, v27.8b, v18.8b\n" |
| 1456 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 1457 | "ldr x20, [x5, #0x90]\n" |
| 1458 | "smlal v23.4s, v27.4h, v16.4h\n" |
| 1459 | "smlal2 v19.4s, v27.8h, v16.8h\n" |
| 1460 | "add x20, x20, x3\n" |
| 1461 | "smlal v7.4s, v28.4h, v21.4h\n" |
| 1462 | "smlal2 v15.4s, v28.8h, v21.8h\n" |
| 1463 | "smlal v20.4s, v25.4h, v21.4h\n" |
| 1464 | "smlal2 v5.4s, v25.8h, v21.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1465 | "tbz x1, #2, 45f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1466 | "ld1 { v31.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1467 | "tbz x1, #1, 44f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1468 | "ld1 { v31.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1469 | "tbz x1, #0, 47f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1470 | "ld1 { v31.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1471 | "b 47f\n" |
| 1472 | "44:" // Oddments: Load (3, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1473 | "tbz x1, #0, 47f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1474 | "ld1 { v31.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1475 | "b 47f\n" |
| 1476 | "45:" // Oddments: Load (3, 0): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1477 | "tbz x1, #1, 46f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1478 | "ld1 { v31.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1479 | "tbz x1, #0, 47f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1480 | "ld1 { v31.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1481 | "b 47f\n" |
| 1482 | "46:" // Oddments: Load (3, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1483 | "tbz x1, #0, 47f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1484 | "ld1 { v31.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1485 | "47:" // Oddments: Load (3, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1486 | "ssubl v31.8h, v31.8b, v18.8b\n" |
| 1487 | "ldr x20, [x5, #0x98]\n" |
| 1488 | "smlal v24.4s, v31.4h, v21.4h\n" |
| 1489 | "smlal2 v22.4s, v31.8h, v21.8h\n" |
| 1490 | "add x20, x20, x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1491 | "tbz x1, #2, 49f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1492 | "ld1 { v28.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1493 | "tbz x1, #1, 48f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1494 | "ld1 { v28.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1495 | "tbz x1, #0, 51f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1496 | "ld1 { v28.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1497 | "b 51f\n" |
| 1498 | "48:" // Oddments: Load (3, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1499 | "tbz x1, #0, 51f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1500 | "ld1 { v28.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1501 | "b 51f\n" |
| 1502 | "49:" // Oddments: Load (3, 1): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1503 | "tbz x1, #1, 50f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1504 | "ld1 { v28.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1505 | "tbz x1, #0, 51f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1506 | "ld1 { v28.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1507 | "b 51f\n" |
| 1508 | "50:" // Oddments: Load (3, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1509 | "tbz x1, #0, 51f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1510 | "ld1 { v28.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1511 | "51:" // Oddments: Load (3, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1512 | "ldr d2, [x6, #0x58]\n" |
| 1513 | "ssubl v28.8h, v28.8b, v18.8b\n" |
| 1514 | "ssubl v2.8h, v2.8b, v13.8b\n" |
| 1515 | "ldr x20, [x5, #0xa0]\n" |
| 1516 | "smlal v23.4s, v28.4h, v21.4h\n" |
| 1517 | "smlal2 v19.4s, v28.8h, v21.8h\n" |
| 1518 | "add x20, x20, x3\n" |
| 1519 | "smlal v7.4s, v25.4h, v2.4h\n" |
| 1520 | "smlal2 v15.4s, v25.8h, v2.8h\n" |
| 1521 | "smlal v20.4s, v10.4h, v2.4h\n" |
| 1522 | "smlal2 v5.4s, v10.8h, v2.8h\n" |
| 1523 | "smlal v24.4s, v28.4h, v2.4h\n" |
| 1524 | "smlal2 v22.4s, v28.8h, v2.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1525 | "tbz x1, #2, 53f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1526 | "ld1 { v21.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1527 | "tbz x1, #1, 52f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1528 | "ld1 { v21.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1529 | "tbz x1, #0, 55f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1530 | "ld1 { v21.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1531 | "b 55f\n" |
| 1532 | "52:" // Oddments: Load (3, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1533 | "tbz x1, #0, 55f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1534 | "ld1 { v21.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1535 | "b 55f\n" |
| 1536 | "53:" // Oddments: Load (3, 2): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1537 | "tbz x1, #1, 54f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1538 | "ld1 { v21.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1539 | "tbz x1, #0, 55f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1540 | "ld1 { v21.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1541 | "b 55f\n" |
| 1542 | "54:" // Oddments: Load (3, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1543 | "tbz x1, #0, 55f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1544 | "ld1 { v21.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1545 | "55:" // Oddments: Load (3, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1546 | "ldr d25, [x6, #0x60]\n" |
| 1547 | "ssubl v21.8h, v21.8b, v18.8b\n" |
| 1548 | "ssubl v25.8h, v25.8b, v13.8b\n" |
| 1549 | "ldr x20, [x5, #0xa8]\n" |
| 1550 | "smlal v23.4s, v21.4h, v2.4h\n" |
| 1551 | "smlal2 v19.4s, v21.8h, v2.8h\n" |
| 1552 | "add x20, x20, x3\n" |
| 1553 | "smlal v7.4s, v10.4h, v25.4h\n" |
| 1554 | "smlal2 v15.4s, v10.8h, v25.8h\n" |
| 1555 | "smlal v20.4s, v12.4h, v25.4h\n" |
| 1556 | "smlal2 v5.4s, v12.8h, v25.8h\n" |
| 1557 | "smlal v24.4s, v21.4h, v25.4h\n" |
| 1558 | "smlal2 v22.4s, v21.8h, v25.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1559 | "tbz x1, #2, 57f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1560 | "ld1 { v9.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1561 | "tbz x1, #1, 56f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1562 | "ld1 { v9.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1563 | "tbz x1, #0, 59f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1564 | "ld1 { v9.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1565 | "b 59f\n" |
| 1566 | "56:" // Oddments: Load (3, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1567 | "tbz x1, #0, 59f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1568 | "ld1 { v9.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1569 | "b 59f\n" |
| 1570 | "57:" // Oddments: Load (3, 3): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1571 | "tbz x1, #1, 58f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1572 | "ld1 { v9.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1573 | "tbz x1, #0, 59f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1574 | "ld1 { v9.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1575 | "b 59f\n" |
| 1576 | "58:" // Oddments: Load (3, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1577 | "tbz x1, #0, 59f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1578 | "ld1 { v9.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1579 | "59:" // Oddments: Load (3, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1580 | "ldr d1, [x6, #0x68]\n" |
| 1581 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 1582 | "ssubl v1.8h, v1.8b, v13.8b\n" |
| 1583 | "ldr x20, [x5, #0xb0]\n" |
| 1584 | "smlal v23.4s, v9.4h, v25.4h\n" |
| 1585 | "smlal2 v19.4s, v9.8h, v25.8h\n" |
| 1586 | "add x20, x20, x3\n" |
| 1587 | "smlal v7.4s, v12.4h, v1.4h\n" |
| 1588 | "smlal2 v15.4s, v12.8h, v1.8h\n" |
| 1589 | "smlal v20.4s, v8.4h, v1.4h\n" |
| 1590 | "smlal2 v5.4s, v8.8h, v1.8h\n" |
| 1591 | "smlal v24.4s, v9.4h, v1.4h\n" |
| 1592 | "smlal2 v22.4s, v9.8h, v1.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1593 | "tbz x1, #2, 61f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1594 | "ld1 { v3.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1595 | "tbz x1, #1, 60f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1596 | "ld1 { v3.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1597 | "tbz x1, #0, 63f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1598 | "ld1 { v3.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1599 | "b 63f\n" |
| 1600 | "60:" // Oddments: Load (3, 4): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1601 | "tbz x1, #0, 63f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1602 | "ld1 { v3.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1603 | "b 63f\n" |
| 1604 | "61:" // Oddments: Load (3, 4): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1605 | "tbz x1, #1, 62f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1606 | "ld1 { v3.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1607 | "tbz x1, #0, 63f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1608 | "ld1 { v3.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1609 | "b 63f\n" |
| 1610 | "62:" // Oddments: Load (3, 4): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1611 | "tbz x1, #0, 63f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1612 | "ld1 { v3.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1613 | "63:" // Oddments: Load (3, 4): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1614 | "ldr d16, [x6, #0x70]\n" |
| 1615 | "ssubl v3.8h, v3.8b, v18.8b\n" |
| 1616 | "ssubl v16.8h, v16.8b, v13.8b\n" |
| 1617 | "ldr x20, [x5, #0xb8]\n" |
| 1618 | "smlal v23.4s, v3.4h, v1.4h\n" |
| 1619 | "smlal2 v19.4s, v3.8h, v1.8h\n" |
| 1620 | "add x20, x20, x3\n" |
| 1621 | "smlal v7.4s, v8.4h, v16.4h\n" |
| 1622 | "smlal2 v15.4s, v8.8h, v16.8h\n" |
| 1623 | "smlal v20.4s, v27.4h, v16.4h\n" |
| 1624 | "smlal2 v5.4s, v27.8h, v16.8h\n" |
| 1625 | "smlal v24.4s, v3.4h, v16.4h\n" |
| 1626 | "smlal2 v22.4s, v3.8h, v16.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1627 | "tbz x1, #2, 65f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1628 | "ld1 { v14.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1629 | "tbz x1, #1, 64f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1630 | "ld1 { v14.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1631 | "tbz x1, #0, 67f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1632 | "ld1 { v14.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1633 | "b 67f\n" |
| 1634 | "64:" // Oddments: Load (3, 5): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1635 | "tbz x1, #0, 67f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1636 | "ld1 { v14.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1637 | "b 67f\n" |
| 1638 | "65:" // Oddments: Load (3, 5): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1639 | "tbz x1, #1, 66f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1640 | "ld1 { v14.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1641 | "tbz x1, #0, 67f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1642 | "ld1 { v14.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1643 | "b 67f\n" |
| 1644 | "66:" // Oddments: Load (3, 5): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1645 | "tbz x1, #0, 67f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1646 | "ld1 { v14.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1647 | "67:" // Oddments: Load (3, 5): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1648 | "ldr d17, [x6, #0x78]\n" |
| 1649 | "ssubl v14.8h, v14.8b, v18.8b\n" |
| 1650 | "ssubl v17.8h, v17.8b, v13.8b\n" |
| 1651 | "ldr x20, [x5, #0xc0]\n" |
| 1652 | "smlal v23.4s, v14.4h, v16.4h\n" |
| 1653 | "smlal2 v19.4s, v14.8h, v16.8h\n" |
| 1654 | "add x20, x20, x3\n" |
| 1655 | "smlal v7.4s, v31.4h, v17.4h\n" |
| 1656 | "smlal2 v15.4s, v31.8h, v17.8h\n" |
| 1657 | "smlal v20.4s, v28.4h, v17.4h\n" |
| 1658 | "smlal2 v5.4s, v28.8h, v17.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1659 | "tbz x1, #2, 69f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1660 | "ld1 { v1.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1661 | "tbz x1, #1, 68f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1662 | "ld1 { v1.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1663 | "tbz x1, #0, 71f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1664 | "ld1 { v1.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1665 | "b 71f\n" |
| 1666 | "68:" // Oddments: Load (4, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1667 | "tbz x1, #0, 71f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1668 | "ld1 { v1.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1669 | "b 71f\n" |
| 1670 | "69:" // Oddments: Load (4, 0): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1671 | "tbz x1, #1, 70f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1672 | "ld1 { v1.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1673 | "tbz x1, #0, 71f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1674 | "ld1 { v1.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1675 | "b 71f\n" |
| 1676 | "70:" // Oddments: Load (4, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1677 | "tbz x1, #0, 71f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1678 | "ld1 { v1.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1679 | "71:" // Oddments: Load (4, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1680 | "ssubl v1.8h, v1.8b, v18.8b\n" |
| 1681 | "ldr x20, [x5, #0xc8]\n" |
| 1682 | "smlal v24.4s, v1.4h, v17.4h\n" |
| 1683 | "smlal2 v22.4s, v1.8h, v17.8h\n" |
| 1684 | "add x20, x20, x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1685 | "tbz x1, #2, 73f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1686 | "ld1 { v16.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1687 | "tbz x1, #1, 72f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1688 | "ld1 { v16.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1689 | "tbz x1, #0, 75f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1690 | "ld1 { v16.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1691 | "b 75f\n" |
| 1692 | "72:" // Oddments: Load (4, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1693 | "tbz x1, #0, 75f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1694 | "ld1 { v16.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1695 | "b 75f\n" |
| 1696 | "73:" // Oddments: Load (4, 1): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1697 | "tbz x1, #1, 74f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1698 | "ld1 { v16.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1699 | "tbz x1, #0, 75f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1700 | "ld1 { v16.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1701 | "b 75f\n" |
| 1702 | "74:" // Oddments: Load (4, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1703 | "tbz x1, #0, 75f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1704 | "ld1 { v16.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1705 | "75:" // Oddments: Load (4, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1706 | "ldr d29, [x6, #0x80]\n" |
| 1707 | "ssubl v16.8h, v16.8b, v18.8b\n" |
| 1708 | "ssubl v29.8h, v29.8b, v13.8b\n" |
| 1709 | "ldr x20, [x5, #0xd0]\n" |
| 1710 | "smlal v23.4s, v16.4h, v17.4h\n" |
| 1711 | "smlal2 v19.4s, v16.8h, v17.8h\n" |
| 1712 | "add x20, x20, x3\n" |
| 1713 | "smlal v7.4s, v28.4h, v29.4h\n" |
| 1714 | "smlal2 v15.4s, v28.8h, v29.8h\n" |
| 1715 | "smlal v20.4s, v21.4h, v29.4h\n" |
| 1716 | "smlal2 v5.4s, v21.8h, v29.8h\n" |
| 1717 | "smlal v24.4s, v16.4h, v29.4h\n" |
| 1718 | "smlal2 v22.4s, v16.8h, v29.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1719 | "tbz x1, #2, 77f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1720 | "ld1 { v30.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1721 | "tbz x1, #1, 76f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1722 | "ld1 { v30.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1723 | "tbz x1, #0, 79f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1724 | "ld1 { v30.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1725 | "b 79f\n" |
| 1726 | "76:" // Oddments: Load (4, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1727 | "tbz x1, #0, 79f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1728 | "ld1 { v30.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1729 | "b 79f\n" |
| 1730 | "77:" // Oddments: Load (4, 2): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1731 | "tbz x1, #1, 78f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1732 | "ld1 { v30.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1733 | "tbz x1, #0, 79f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1734 | "ld1 { v30.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1735 | "b 79f\n" |
| 1736 | "78:" // Oddments: Load (4, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1737 | "tbz x1, #0, 79f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1738 | "ld1 { v30.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1739 | "79:" // Oddments: Load (4, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1740 | "ldr d12, [x6, #0x88]\n" |
| 1741 | "ssubl v30.8h, v30.8b, v18.8b\n" |
| 1742 | "ssubl v12.8h, v12.8b, v13.8b\n" |
| 1743 | "ldr x20, [x5, #0xd8]\n" |
| 1744 | "smlal v23.4s, v30.4h, v29.4h\n" |
| 1745 | "smlal2 v19.4s, v30.8h, v29.8h\n" |
| 1746 | "add x20, x20, x3\n" |
| 1747 | "smlal v7.4s, v21.4h, v12.4h\n" |
| 1748 | "smlal2 v15.4s, v21.8h, v12.8h\n" |
| 1749 | "smlal v20.4s, v9.4h, v12.4h\n" |
| 1750 | "smlal2 v5.4s, v9.8h, v12.8h\n" |
| 1751 | "smlal v24.4s, v30.4h, v12.4h\n" |
| 1752 | "smlal2 v22.4s, v30.8h, v12.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1753 | "tbz x1, #2, 81f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1754 | "ld1 { v29.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1755 | "tbz x1, #1, 80f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1756 | "ld1 { v29.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1757 | "tbz x1, #0, 83f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1758 | "ld1 { v29.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1759 | "b 83f\n" |
| 1760 | "80:" // Oddments: Load (4, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1761 | "tbz x1, #0, 83f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1762 | "ld1 { v29.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1763 | "b 83f\n" |
| 1764 | "81:" // Oddments: Load (4, 3): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1765 | "tbz x1, #1, 82f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1766 | "ld1 { v29.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1767 | "tbz x1, #0, 83f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1768 | "ld1 { v29.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1769 | "b 83f\n" |
| 1770 | "82:" // Oddments: Load (4, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1771 | "tbz x1, #0, 83f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1772 | "ld1 { v29.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1773 | "83:" // Oddments: Load (4, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1774 | "ldr d21, [x6, #0x90]\n" |
| 1775 | "ssubl v29.8h, v29.8b, v18.8b\n" |
| 1776 | "ssubl v21.8h, v21.8b, v13.8b\n" |
| 1777 | "ldr x20, [x5, #0xe0]\n" |
| 1778 | "smlal v23.4s, v29.4h, v12.4h\n" |
| 1779 | "smlal2 v19.4s, v29.8h, v12.8h\n" |
| 1780 | "add x20, x20, x3\n" |
| 1781 | "smlal v7.4s, v9.4h, v21.4h\n" |
| 1782 | "smlal2 v15.4s, v9.8h, v21.8h\n" |
| 1783 | "smlal v20.4s, v3.4h, v21.4h\n" |
| 1784 | "smlal2 v5.4s, v3.8h, v21.8h\n" |
| 1785 | "smlal v24.4s, v29.4h, v21.4h\n" |
| 1786 | "smlal2 v22.4s, v29.8h, v21.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1787 | "tbz x1, #2, 85f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1788 | "ld1 { v25.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1789 | "tbz x1, #1, 84f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1790 | "ld1 { v25.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1791 | "tbz x1, #0, 87f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1792 | "ld1 { v25.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1793 | "b 87f\n" |
| 1794 | "84:" // Oddments: Load (4, 4): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1795 | "tbz x1, #0, 87f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1796 | "ld1 { v25.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1797 | "b 87f\n" |
| 1798 | "85:" // Oddments: Load (4, 4): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1799 | "tbz x1, #1, 86f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1800 | "ld1 { v25.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1801 | "tbz x1, #0, 87f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1802 | "ld1 { v25.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1803 | "b 87f\n" |
| 1804 | "86:" // Oddments: Load (4, 4): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1805 | "tbz x1, #0, 87f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1806 | "ld1 { v25.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1807 | "87:" // Oddments: Load (4, 4): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1808 | "ldr d8, [x6, #0x98]\n" |
| 1809 | "ssubl v25.8h, v25.8b, v18.8b\n" |
| 1810 | "ssubl v8.8h, v8.8b, v13.8b\n" |
| 1811 | "ldr x20, [x5, #0xe8]\n" |
| 1812 | "smlal v23.4s, v25.4h, v21.4h\n" |
| 1813 | "smlal2 v19.4s, v25.8h, v21.8h\n" |
| 1814 | "add x20, x20, x3\n" |
| 1815 | "smlal v7.4s, v3.4h, v8.4h\n" |
| 1816 | "smlal2 v15.4s, v3.8h, v8.8h\n" |
| 1817 | "smlal v20.4s, v14.4h, v8.4h\n" |
| 1818 | "smlal2 v5.4s, v14.8h, v8.8h\n" |
| 1819 | "smlal v24.4s, v25.4h, v8.4h\n" |
| 1820 | "smlal2 v22.4s, v25.8h, v8.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1821 | "tbz x1, #2, 89f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1822 | "ld1 { v21.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1823 | "tbz x1, #1, 88f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1824 | "ld1 { v21.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1825 | "tbz x1, #0, 91f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1826 | "ld1 { v21.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1827 | "b 91f\n" |
| 1828 | "88:" // Oddments: Load (4, 5): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1829 | "tbz x1, #0, 91f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1830 | "ld1 { v21.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1831 | "b 91f\n" |
| 1832 | "89:" // Oddments: Load (4, 5): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1833 | "tbz x1, #1, 90f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1834 | "ld1 { v21.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1835 | "tbz x1, #0, 91f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1836 | "ld1 { v21.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1837 | "b 91f\n" |
| 1838 | "90:" // Oddments: Load (4, 5): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1839 | "tbz x1, #0, 91f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1840 | "ld1 { v21.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1841 | "91:" // Oddments: Load (4, 5): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1842 | "ldr d9, [x6, #0xa0]\n" |
| 1843 | "ssubl v21.8h, v21.8b, v18.8b\n" |
| 1844 | "ssubl v9.8h, v9.8b, v13.8b\n" |
| 1845 | "ldr x20, [x5, #0xf0]\n" |
| 1846 | "smlal v23.4s, v21.4h, v8.4h\n" |
| 1847 | "smlal2 v19.4s, v21.8h, v8.8h\n" |
| 1848 | "add x20, x20, x3\n" |
| 1849 | "smlal v7.4s, v1.4h, v9.4h\n" |
| 1850 | "smlal2 v15.4s, v1.8h, v9.8h\n" |
| 1851 | "smlal v20.4s, v16.4h, v9.4h\n" |
| 1852 | "smlal2 v5.4s, v16.8h, v9.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1853 | "tbz x1, #2, 93f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1854 | "ld1 { v12.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1855 | "tbz x1, #1, 92f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1856 | "ld1 { v12.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1857 | "tbz x1, #0, 95f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1858 | "ld1 { v12.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1859 | "b 95f\n" |
| 1860 | "92:" // Oddments: Load (5, 0): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1861 | "tbz x1, #0, 95f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1862 | "ld1 { v12.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1863 | "b 95f\n" |
| 1864 | "93:" // Oddments: Load (5, 0): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1865 | "tbz x1, #1, 94f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1866 | "ld1 { v12.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1867 | "tbz x1, #0, 95f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1868 | "ld1 { v12.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1869 | "b 95f\n" |
| 1870 | "94:" // Oddments: Load (5, 0): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1871 | "tbz x1, #0, 95f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1872 | "ld1 { v12.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1873 | "95:" // Oddments: Load (5, 0): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1874 | "ssubl v12.8h, v12.8b, v18.8b\n" |
| 1875 | "ldr x20, [x5, #0xf8]\n" |
| 1876 | "smlal v24.4s, v12.4h, v9.4h\n" |
| 1877 | "smlal2 v22.4s, v12.8h, v9.8h\n" |
| 1878 | "add x20, x20, x3\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1879 | "tbz x1, #2, 97f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1880 | "ld1 { v10.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1881 | "tbz x1, #1, 96f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1882 | "ld1 { v10.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1883 | "tbz x1, #0, 99f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1884 | "ld1 { v10.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1885 | "b 99f\n" |
| 1886 | "96:" // Oddments: Load (5, 1): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1887 | "tbz x1, #0, 99f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1888 | "ld1 { v10.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1889 | "b 99f\n" |
| 1890 | "97:" // Oddments: Load (5, 1): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1891 | "tbz x1, #1, 98f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1892 | "ld1 { v10.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1893 | "tbz x1, #0, 99f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1894 | "ld1 { v10.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1895 | "b 99f\n" |
| 1896 | "98:" // Oddments: Load (5, 1): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1897 | "tbz x1, #0, 99f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1898 | "ld1 { v10.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1899 | "99:" // Oddments: Load (5, 1): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1900 | "ldr d12, [x6, #0xa8]\n" |
| 1901 | "ssubl v10.8h, v10.8b, v18.8b\n" |
| 1902 | "ssubl v12.8h, v12.8b, v13.8b\n" |
| 1903 | "ldr x20, [x5, #0x100]\n" |
| 1904 | "smlal v23.4s, v10.4h, v9.4h\n" |
| 1905 | "smlal2 v19.4s, v10.8h, v9.8h\n" |
| 1906 | "add x20, x20, x3\n" |
| 1907 | "smlal v7.4s, v16.4h, v12.4h\n" |
| 1908 | "smlal2 v15.4s, v16.8h, v12.8h\n" |
| 1909 | "smlal v20.4s, v30.4h, v12.4h\n" |
| 1910 | "smlal2 v5.4s, v30.8h, v12.8h\n" |
| 1911 | "smlal v24.4s, v10.4h, v12.4h\n" |
| 1912 | "smlal2 v22.4s, v10.8h, v12.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1913 | "tbz x1, #2, 101f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1914 | "ld1 { v9.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1915 | "tbz x1, #1, 100f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1916 | "ld1 { v9.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1917 | "tbz x1, #0, 103f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1918 | "ld1 { v9.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1919 | "b 103f\n" |
| 1920 | "100:" // Oddments: Load (5, 2): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1921 | "tbz x1, #0, 103f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1922 | "ld1 { v9.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1923 | "b 103f\n" |
| 1924 | "101:" // Oddments: Load (5, 2): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1925 | "tbz x1, #1, 102f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1926 | "ld1 { v9.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1927 | "tbz x1, #0, 103f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1928 | "ld1 { v9.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1929 | "b 103f\n" |
| 1930 | "102:" // Oddments: Load (5, 2): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1931 | "tbz x1, #0, 103f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1932 | "ld1 { v9.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1933 | "103:" // Oddments: Load (5, 2): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1934 | "ldr d28, [x6, #0xb0]\n" |
| 1935 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 1936 | "ssubl v28.8h, v28.8b, v13.8b\n" |
| 1937 | "ldr x20, [x5, #0x108]\n" |
| 1938 | "smlal v23.4s, v9.4h, v12.4h\n" |
| 1939 | "smlal2 v19.4s, v9.8h, v12.8h\n" |
| 1940 | "add x20, x20, x3\n" |
| 1941 | "smlal v7.4s, v30.4h, v28.4h\n" |
| 1942 | "smlal2 v15.4s, v30.8h, v28.8h\n" |
| 1943 | "smlal v20.4s, v29.4h, v28.4h\n" |
| 1944 | "smlal2 v5.4s, v29.8h, v28.8h\n" |
| 1945 | "smlal v24.4s, v9.4h, v28.4h\n" |
| 1946 | "smlal2 v22.4s, v9.8h, v28.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1947 | "tbz x1, #2, 105f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1948 | "ld1 { v2.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1949 | "tbz x1, #1, 104f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1950 | "ld1 { v2.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1951 | "tbz x1, #0, 107f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1952 | "ld1 { v2.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1953 | "b 107f\n" |
| 1954 | "104:" // Oddments: Load (5, 3): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1955 | "tbz x1, #0, 107f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1956 | "ld1 { v2.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1957 | "b 107f\n" |
| 1958 | "105:" // Oddments: Load (5, 3): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1959 | "tbz x1, #1, 106f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1960 | "ld1 { v2.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1961 | "tbz x1, #0, 107f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1962 | "ld1 { v2.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1963 | "b 107f\n" |
| 1964 | "106:" // Oddments: Load (5, 3): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1965 | "tbz x1, #0, 107f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1966 | "ld1 { v2.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1967 | "107:" // Oddments: Load (5, 3): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1968 | "ldr d30, [x6, #0xb8]\n" |
| 1969 | "ssubl v2.8h, v2.8b, v18.8b\n" |
| 1970 | "ssubl v30.8h, v30.8b, v13.8b\n" |
| 1971 | "ldr x20, [x5, #0x110]\n" |
| 1972 | "smlal v23.4s, v2.4h, v28.4h\n" |
| 1973 | "smlal2 v19.4s, v2.8h, v28.8h\n" |
| 1974 | "add x20, x20, x3\n" |
| 1975 | "smlal v7.4s, v29.4h, v30.4h\n" |
| 1976 | "smlal2 v15.4s, v29.8h, v30.8h\n" |
| 1977 | "smlal v20.4s, v25.4h, v30.4h\n" |
| 1978 | "smlal2 v5.4s, v25.8h, v30.8h\n" |
| 1979 | "smlal v24.4s, v2.4h, v30.4h\n" |
| 1980 | "smlal2 v22.4s, v2.8h, v30.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1981 | "tbz x1, #2, 109f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1982 | "ld1 { v27.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1983 | "tbz x1, #1, 108f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1984 | "ld1 { v27.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1985 | "tbz x1, #0, 111f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1986 | "ld1 { v27.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1987 | "b 111f\n" |
| 1988 | "108:" // Oddments: Load (5, 4): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1989 | "tbz x1, #0, 111f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1990 | "ld1 { v27.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1991 | "b 111f\n" |
| 1992 | "109:" // Oddments: Load (5, 4): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1993 | "tbz x1, #1, 110f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1994 | "ld1 { v27.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1995 | "tbz x1, #0, 111f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 1996 | "ld1 { v27.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 1997 | "b 111f\n" |
| 1998 | "110:" // Oddments: Load (5, 4): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 1999 | "tbz x1, #0, 111f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2000 | "ld1 { v27.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2001 | "111:" // Oddments: Load (5, 4): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2002 | "ldr d8, [x6, #0xc0]\n" |
| 2003 | "ssubl v27.8h, v27.8b, v18.8b\n" |
| 2004 | "ssubl v8.8h, v8.8b, v13.8b\n" |
| 2005 | "ldr x20, [x5, #0x118]\n" |
| 2006 | "smlal v23.4s, v27.4h, v30.4h\n" |
| 2007 | "smlal2 v19.4s, v27.8h, v30.8h\n" |
| 2008 | "add x20, x20, x3\n" |
| 2009 | "smlal v7.4s, v25.4h, v8.4h\n" |
| 2010 | "smlal2 v15.4s, v25.8h, v8.8h\n" |
| 2011 | "smlal v20.4s, v21.4h, v8.4h\n" |
| 2012 | "smlal2 v5.4s, v21.8h, v8.8h\n" |
| 2013 | "smlal v24.4s, v27.4h, v8.4h\n" |
| 2014 | "smlal2 v22.4s, v27.8h, v8.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2015 | "tbz x1, #2, 113f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2016 | "ld1 { v9.s }[0], [x20], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2017 | "tbz x1, #1, 112f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2018 | "ld1 { v9.h }[2], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2019 | "tbz x1, #0, 115f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2020 | "ld1 { v9.b }[6], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2021 | "b 115f\n" |
| 2022 | "112:" // Oddments: Load (5, 5): Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2023 | "tbz x1, #0, 115f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2024 | "ld1 { v9.b }[4], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2025 | "b 115f\n" |
| 2026 | "113:" // Oddments: Load (5, 5): Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2027 | "tbz x1, #1, 114f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2028 | "ld1 { v9.h }[0], [x20], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2029 | "tbz x1, #0, 115f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2030 | "ld1 { v9.b }[2], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2031 | "b 115f\n" |
| 2032 | "114:" // Oddments: Load (5, 5): Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2033 | "tbz x1, #0, 115f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2034 | "ld1 { v9.b }[0], [x20]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2035 | "115:" // Oddments: Load (5, 5): Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2036 | "ssubl v9.8h, v9.8b, v18.8b\n" |
| 2037 | "smlal v23.4s, v9.4h, v8.4h\n" |
| 2038 | "smlal2 v19.4s, v9.8h, v8.8h\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2039 | "tbz x1, #2, 117f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2040 | "ld1 { v30.4s }, [x7], #0x10\n" |
| 2041 | "ld1 { v12.4s }, [x8], #0x10\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2042 | "tbz x1, #1, 116f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2043 | "ld1 { v14.d }[0], [x7], #0x8\n" |
| 2044 | "ld1 { v27.d }[0], [x8], #0x8\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2045 | "tbz x1, #0, 119f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2046 | "ld1 { v14.s }[2], [x7]\n" |
| 2047 | "ld1 { v27.s }[2], [x8]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2048 | "b 119f\n" |
| 2049 | "116:" // Oddments: Load requant params: Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2050 | "tbz x1, #0, 119f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2051 | "ld1 { v14.s }[0], [x7]\n" |
| 2052 | "ld1 { v27.s }[0], [x8]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2053 | "b 119f\n" |
| 2054 | "117:" // Oddments: Load requant params: Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2055 | "tbz x1, #1, 118f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2056 | "ld1 { v30.d }[0], [x7], #0x8\n" |
| 2057 | "ld1 { v12.d }[0], [x8], #0x8\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2058 | "tbz x1, #0, 119f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2059 | "ld1 { v30.s }[2], [x7]\n" |
| 2060 | "ld1 { v12.s }[2], [x8]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2061 | "b 119f\n" |
| 2062 | "118:" // Oddments: Load requant params: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2063 | "tbz x1, #0, 119f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2064 | "ld1 { v30.s }[0], [x7]\n" |
| 2065 | "ld1 { v12.s }[0], [x8]\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2066 | "119:" // Oddments: Load requant params: Bit 2: End |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2067 | "sqrdmulh v7.4s, v7.4s, v30.4s\n" |
| 2068 | "and v16.16b, v7.16b, v12.16b\n" |
| 2069 | "add x17, x17, x4\n" |
| 2070 | "add x16, x16, x4\n" |
| 2071 | "sqrdmulh v15.4s, v15.4s, v14.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2072 | "sshr v16.4s, v16.4s, #0x1f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2073 | "add x15, x15, x4\n" |
| 2074 | "add x14, x14, x4\n" |
| 2075 | "and v2.16b, v15.16b, v27.16b\n" |
| 2076 | "sqrdmulh v20.4s, v20.4s, v30.4s\n" |
| 2077 | "sqrdmulh v24.4s, v24.4s, v30.4s\n" |
| 2078 | "sqrdmulh v23.4s, v23.4s, v30.4s\n" |
| 2079 | "sqadd v7.4s, v7.4s, v16.4s\n" |
| 2080 | "sshr v2.4s, v2.4s, #0x1f\n" |
| 2081 | "and v21.16b, v20.16b, v12.16b\n" |
| 2082 | "sqrdmulh v5.4s, v5.4s, v14.4s\n" |
| 2083 | "and v18.16b, v24.16b, v12.16b\n" |
| 2084 | "sqrdmulh v22.4s, v22.4s, v14.4s\n" |
| 2085 | "and v31.16b, v23.16b, v12.16b\n" |
| 2086 | "sqrdmulh v19.4s, v19.4s, v14.4s\n" |
| 2087 | "sqadd v15.4s, v15.4s, v2.4s\n" |
| 2088 | "sshr v21.4s, v21.4s, #0x1f\n" |
| 2089 | "and v9.16b, v5.16b, v27.16b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2090 | "sshr v18.4s, v18.4s, #0x1f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2091 | "and v4.16b, v22.16b, v27.16b\n" |
| 2092 | "sshr v31.4s, v31.4s, #0x1f\n" |
| 2093 | "and v28.16b, v19.16b, v27.16b\n" |
| 2094 | "sqadd v20.4s, v20.4s, v21.4s\n" |
| 2095 | "sshr v9.4s, v9.4s, #0x1f\n" |
| 2096 | "sqadd v24.4s, v24.4s, v18.4s\n" |
| 2097 | "sshr v4.4s, v4.4s, #0x1f\n" |
| 2098 | "sqadd v23.4s, v23.4s, v31.4s\n" |
| 2099 | "sshr v28.4s, v28.4s, #0x1f\n" |
| 2100 | "srshl v7.4s, v7.4s, v12.4s\n" |
| 2101 | "srshl v20.4s, v20.4s, v12.4s\n" |
| 2102 | "sqadd v5.4s, v5.4s, v9.4s\n" |
| 2103 | "srshl v24.4s, v24.4s, v12.4s\n" |
| 2104 | "sqadd v22.4s, v22.4s, v4.4s\n" |
| 2105 | "srshl v23.4s, v23.4s, v12.4s\n" |
| 2106 | "sqadd v19.4s, v19.4s, v28.4s\n" |
| 2107 | "srshl v15.4s, v15.4s, v27.4s\n" |
| 2108 | "sqxtn v7.4h, v7.4s\n" |
| 2109 | "srshl v5.4s, v5.4s, v27.4s\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2110 | "sqxtn v20.4h, v20.4s\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2111 | "srshl v22.4s, v22.4s, v27.4s\n" |
| 2112 | "sqxtn v24.4h, v24.4s\n" |
| 2113 | "srshl v19.4s, v19.4s, v27.4s\n" |
| 2114 | "sqxtn v23.4h, v23.4s\n" |
| 2115 | "sqxtn2 v7.8h, v15.4s\n" |
| 2116 | "sqxtn2 v20.8h, v5.4s\n" |
| 2117 | "sqxtn2 v24.8h, v22.4s\n" |
| 2118 | "sqxtn2 v23.8h, v19.4s\n" |
| 2119 | "sqadd v7.8h, v7.8h, v26.8h\n" |
| 2120 | "sqadd v20.8h, v20.8h, v26.8h\n" |
| 2121 | "sqadd v24.8h, v24.8h, v26.8h\n" |
| 2122 | "sqadd v23.8h, v23.8h, v26.8h\n" |
| 2123 | "smax v7.8h, v7.8h, v11.8h\n" |
| 2124 | "smax v20.8h, v20.8h, v11.8h\n" |
| 2125 | "smax v24.8h, v24.8h, v11.8h\n" |
| 2126 | "smax v23.8h, v23.8h, v11.8h\n" |
| 2127 | "smin v7.8h, v7.8h, v0.8h\n" |
| 2128 | "smin v20.8h, v20.8h, v0.8h\n" |
| 2129 | "smin v24.8h, v24.8h, v0.8h\n" |
| 2130 | "smin v23.8h, v23.8h, v0.8h\n" |
| 2131 | "uzp1 v7.16b, v7.16b, v7.16b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2132 | "uzp1 v20.16b, v20.16b, v20.16b\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2133 | "uzp1 v24.16b, v24.16b, v24.16b\n" |
| 2134 | "uzp1 v23.16b, v23.16b, v23.16b\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2135 | "tbz x1, #2, 121f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2136 | "st1 { v7.s }[0], [x17], #0x4\n" |
| 2137 | "st1 { v20.s }[0], [x16], #0x4\n" |
| 2138 | "st1 { v24.s }[0], [x15], #0x4\n" |
| 2139 | "st1 { v23.s }[0], [x14], #0x4\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2140 | "tbz x1, #1, 120f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2141 | "st1 { v7.h }[2], [x17], #0x2\n" |
| 2142 | "st1 { v20.h }[2], [x16], #0x2\n" |
| 2143 | "st1 { v24.h }[2], [x15], #0x2\n" |
| 2144 | "st1 { v23.h }[2], [x14], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2145 | "tbz x1, #0, 123f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2146 | "st1 { v7.b }[6], [x17], #0x1\n" |
| 2147 | "st1 { v20.b }[6], [x16], #0x1\n" |
| 2148 | "st1 { v24.b }[6], [x15], #0x1\n" |
| 2149 | "st1 { v23.b }[6], [x14], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2150 | "b 123f\n" |
| 2151 | "120:" // Oddments: Bit 2: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2152 | "tbz x1, #0, 123f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2153 | "st1 { v7.b }[4], [x17], #0x1\n" |
| 2154 | "st1 { v20.b }[4], [x16], #0x1\n" |
| 2155 | "st1 { v24.b }[4], [x15], #0x1\n" |
| 2156 | "st1 { v23.b }[4], [x14], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2157 | "b 123f\n" |
| 2158 | "121:" // Oddments: Bit 2: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2159 | "tbz x1, #1, 122f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2160 | "st1 { v7.h }[0], [x17], #0x2\n" |
| 2161 | "st1 { v20.h }[0], [x16], #0x2\n" |
| 2162 | "st1 { v24.h }[0], [x15], #0x2\n" |
| 2163 | "st1 { v23.h }[0], [x14], #0x2\n" |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2164 | "tbz x1, #0, 123f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2165 | "st1 { v7.b }[2], [x17], #0x1\n" |
| 2166 | "st1 { v20.b }[2], [x16], #0x1\n" |
| 2167 | "st1 { v24.b }[2], [x15], #0x1\n" |
| 2168 | "st1 { v23.b }[2], [x14], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2169 | "b 123f\n" |
| 2170 | "122:" // Oddments: Bit 2: Unset: Bit 1: Unset |
Michael Tyler | 7d9a626 | 2023-02-01 16:37:07 +0000 | [diff] [blame] | 2171 | "tbz x1, #0, 123f\n" |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2172 | "st1 { v7.b }[0], [x17], #0x1\n" |
| 2173 | "st1 { v20.b }[0], [x16], #0x1\n" |
| 2174 | "st1 { v24.b }[0], [x15], #0x1\n" |
| 2175 | "st1 { v23.b }[0], [x14], #0x1\n" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2176 | "123:" // Oddments: Bit 2: End |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2177 | "124:" // End |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2178 | : |
| 2179 | : [offsetof_Params_bias] "I" (offsetof(Params, bias)), [offsetof_Params_inptrs] "I" (offsetof(Params, inptrs)), [offsetof_Params_n_channels] "I" (offsetof(Params, n_channels)), [offsetof_Params_outptrs] "I" (offsetof(Params, outptrs)), [offsetof_Params_requant] "I" (offsetof(Params, requant)), [offsetof_Params_requant_muls] "I" (offsetof(Params, requant_muls)), [offsetof_Params_requant_shifts] "I" (offsetof(Params, requant_shifts)), [offsetof_Params_weights] "I" (offsetof(Params, weights)), [offsetof_Requantize32_a_offset] "I" (offsetof(arm_gemm::Requantize32, a_offset)), [offsetof_Requantize32_b_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [offsetof_Requantize32_c_offset] "I" (offsetof(arm_gemm::Requantize32, c_offset)), [offsetof_Requantize32_maxval] "I" (offsetof(arm_gemm::Requantize32, maxval)), [offsetof_Requantize32_minval] "I" (offsetof(arm_gemm::Requantize32, minval)), [params] "r" (¶ms) |
Michael Tyler | 74921ee | 2023-04-12 17:43:17 +0100 | [diff] [blame] | 2180 | : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" |
Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame] | 2181 | ); |
| 2182 | } |
| 2183 | |
| 2184 | } // namespace depthwise |
| 2185 | } // namespace arm_conv |
| 2186 | |
| 2187 | #endif // defined(__aarch64__) |