Manuel Bottini | b4bb6a0 | 2021-05-24 16:01:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_DEPTHWISECONV2DASSEMBLYDISPATCH_H |
| 25 | #define ARM_COMPUTE_CPU_DEPTHWISECONV2DASSEMBLYDISPATCH_H |
| 26 | |
| 27 | #include "src/core/common/Macros.h" |
| 28 | #include "src/runtime/cpu/ICpuOperator.h" |
| 29 | |
| 30 | namespace arm_compute |
| 31 | { |
| 32 | namespace cpu |
| 33 | { |
| 34 | /** Depthwise convolution assembly kernel glue */ |
| 35 | class CpuDepthwiseConv2dAssemblyDispatch : public ICpuOperator |
| 36 | { |
| 37 | public: |
| 38 | /** Default constructor */ |
| 39 | CpuDepthwiseConv2dAssemblyDispatch(); |
| 40 | ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDepthwiseConv2dAssemblyDispatch); |
| 41 | /** Default destructor */ |
| 42 | ~CpuDepthwiseConv2dAssemblyDispatch(); |
| 43 | |
| 44 | /** Initialize the function's source, destination, kernels and border_size. |
| 45 | * |
| 46 | * @note Supports only NHWC format |
| 47 | * |
| 48 | * @param[in] src Source tensor info. Data type supported: QASYMM8/F16/F32. (Written to only for border filling). |
| 49 | * @param[in] weights Weights tensor info. These are 3D tensors with shape [W, H, IFM]. Data type supported: Same as @p src. |
| 50 | * @param[in] bias (Optional) Biases tensor info. A 1D tensor with shape [IFM]. Must be nullptr if not needed. |
| 51 | * Data type supported: Same as @p src. |
| 52 | * @param[out] dst Destination tensor info. Data type supported: same as @p src. |
| 53 | * @param[in] info Depthwise convolution meta-data. |
| 54 | */ |
| 55 | void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, ITensorInfo *dst, const ConvolutionInfo &info); |
| 56 | /** Static function to check if given info will lead to a valid configuration |
| 57 | * |
| 58 | * Similar to CpuDepthwiseConv2dAssemblyDispatch::configure() |
| 59 | * |
| 60 | * @return a status |
| 61 | */ |
| 62 | static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, const ITensorInfo *dst, const ConvolutionInfo &info); |
| 63 | /** Check if the optimized kernel can be used for the given kernel sizes and strides |
| 64 | * |
| 65 | * @warning Even if this return true the inputs and outputs might need to get permuted as the only layout supported is NHWC |
| 66 | * |
| 67 | * @param[in] src Input tensor info. |
| 68 | * @param[in] weights Weights tensor info. |
| 69 | * @param[in] info Depthwise convolution meta-data. |
| 70 | * |
| 71 | * @return True if the assembly kernel could be used else false. Note that transformations of input/output could be needed. |
| 72 | */ |
| 73 | static bool is_optimized_supported(const ITensorInfo *src, const ITensorInfo *weights, const ConvolutionInfo &info); |
| 74 | |
| 75 | // Inherited methods overridden: |
| 76 | void run(ITensorPack &tensors) override; |
| 77 | void prepare(ITensorPack &tensors) override; |
| 78 | experimental::MemoryRequirements workspace() const override; |
| 79 | |
| 80 | private: |
| 81 | struct LocalImpl; |
| 82 | std::unique_ptr<LocalImpl> _pImpl; |
| 83 | }; |
| 84 | } // namespace cpu |
| 85 | } // namespace arm_compute |
| 86 | #endif /* ARM_COMPUTE_CPU_DEPTHWISECONV2DASSEMBLYDISPATCH_H */ |