Michele Di Giorgio | d02d5ed | 2021-01-22 09:47:04 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019-2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H |
| 25 | #define ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H |
| 26 | |
| 27 | #include "arm_compute/core/Types.h" |
| 28 | #include "src/core/common/Macros.h" |
| 29 | #include "src/core/cpu/ICpuKernel.h" |
| 30 | |
| 31 | namespace arm_conv |
| 32 | { |
| 33 | namespace depthwise |
| 34 | { |
| 35 | // Forward declarations |
| 36 | class IDepthwiseCommon; |
| 37 | } // depthwise |
| 38 | } // arm_conv |
| 39 | |
| 40 | namespace arm_compute |
| 41 | { |
| 42 | namespace cpu |
| 43 | { |
| 44 | namespace kernels |
| 45 | { |
| 46 | /** This class is a wrapper for the depthwise convolution assembly kernels. */ |
| 47 | class CpuDepthwiseConv2dAssemblyWrapperKernel final : public ICpuKernel |
| 48 | { |
| 49 | public: |
| 50 | /** Default constructor */ |
| 51 | CpuDepthwiseConv2dAssemblyWrapperKernel(); |
| 52 | ~CpuDepthwiseConv2dAssemblyWrapperKernel(); |
| 53 | ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDepthwiseConv2dAssemblyWrapperKernel); |
| 54 | |
| 55 | /** Initialise the kernel's src and dst. |
| 56 | * |
| 57 | * @param[in] src Source tensor info. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. |
| 58 | * @param[in] weights Weights tensor info. These are 3D tensors with shape [kernel_x, kernel_y, IFM]. |
| 59 | * Data type supported: same as @p src or QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL when @p src is QASYMM8/QASYMM8_SIGNED. |
| 60 | * @param[in] bias Bias tensor. A 1D tensor with shape [IFM]. Must be nullptr if not needed. |
| 61 | * Data type supported: same as @p src, S32 when @p src is QASYMM8/QASYMM8_SIGNED. |
| 62 | * @param[out] dst Destination tensor info. Data type supported: same as @p input. |
| 63 | * @param[in] info Depthwise convolution layer meta-data. |
| 64 | * @param[in] cpu_info CPU information needed to select the most appropriate kernel. |
| 65 | */ |
| 66 | void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, ITensorInfo *dst, const ConvolutionInfo &info, const CPUInfo &cpu_info); |
| 67 | |
| 68 | /** Indicates whether or not this function can be used to process the given parameters. |
| 69 | * |
| 70 | * Similar to @ref CpuDepthwiseConv2dAssemblyWrapperKernel::configure() |
| 71 | * |
| 72 | * @return a status. |
| 73 | */ |
| 74 | static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, const ITensorInfo *dst, const ConvolutionInfo &info); |
| 75 | |
| 76 | // Inherited methods overridden: |
| 77 | void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; |
| 78 | const char *name() const override; |
| 79 | |
| 80 | /** Pack bias and weights in a storage space for the assembly kernel |
| 81 | * |
| 82 | * @param[in] parameters_ptr Pointer to storage space. |
| 83 | * @param[in] bias_ptr Pointer to bias buffer. |
| 84 | * @param[in] weights_ptr Pointer to weights buffer. |
| 85 | * @param[in] ld_weights_col Columns displacement for the weights tensor. |
| 86 | * @param[in] ld_weights_row Rows displacement for the weights tensor. |
| 87 | */ |
| 88 | void pack_parameters(void *parameters_ptr, void *bias_ptr, void *weights_ptr, size_t ld_weights_col, size_t ld_weights_row); |
| 89 | |
| 90 | /** Get the amount of storage space required for the rearranged weights and bias. |
| 91 | * |
| 92 | * @return size of workspace |
| 93 | */ |
| 94 | size_t get_storage_size() const; |
| 95 | |
| 96 | /** Get size of the workspace needed by the assembly kernel. |
| 97 | * |
| 98 | * @param[in] num_threads Maximum number of threads that are going to be spawned. |
| 99 | * @param[in] num_input_channels Number of channels of the input tensor. |
| 100 | * |
| 101 | * @return size of workspace |
| 102 | */ |
| 103 | size_t get_working_size(unsigned int num_threads, unsigned int num_input_channels) const; |
| 104 | |
| 105 | /** Was the asm kernel successfully configured? |
| 106 | * |
| 107 | * @return True if the asm kernel is configured and ready to run |
| 108 | */ |
| 109 | bool is_configured() const; |
| 110 | |
| 111 | private: |
| 112 | std::unique_ptr<arm_conv::depthwise::IDepthwiseCommon> _kernel_asm; |
| 113 | std::vector<int32_t> _multipliers{}; |
| 114 | std::vector<int32_t> _left_shifts{}; |
| 115 | std::vector<int32_t> _right_shifts{}; |
| 116 | }; |
| 117 | } // namespace kernels |
| 118 | } // namespace cpu |
| 119 | } // namespace arm_compute |
| 120 | #endif /* ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H */ |