Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 1 | /* |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 2 | * Copyright (c) 2021-2022 Arm Limited. |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #ifndef ARM_COMPUTE_CPU_DIRECT_CONV3D_KERNEL_H |
| 25 | #define ARM_COMPUTE_CPU_DIRECT_CONV3D_KERNEL_H |
| 26 | |
| 27 | #include "arm_compute/runtime/FunctionDescriptors.h" |
| 28 | #include "src/core/common/Macros.h" |
| 29 | #include "src/cpu/ICpuKernel.h" |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 30 | |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 31 | namespace arm_compute |
| 32 | { |
| 33 | namespace cpu |
| 34 | { |
| 35 | namespace kernels |
| 36 | { |
| 37 | /** Interface for the kernel to perform 3D Direct Convolution Layer. */ |
Yair Schwarzbaum | 46d44d2 | 2022-01-12 16:38:58 +0200 | [diff] [blame] | 38 | class CpuDirectConv3dKernel : public ICpuKernel<CpuDirectConv3dKernel> |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 39 | { |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 40 | private: |
| 41 | /* Template function for convolution 3d NDHWC */ |
| 42 | using DirectConv3dKernelPtr = std::add_pointer<void(const ITensor *, const ITensor *, const ITensor *, ITensor *, const Conv3dInfo &, const Window &)>::type; |
| 43 | |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 44 | public: |
| 45 | CpuDirectConv3dKernel() = default; |
| 46 | ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDirectConv3dKernel); |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 47 | /** Set the src, weights, biases and dst tensor info. |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 48 | * |
| 49 | * Valid data type configurations: |
| 50 | * |src0 |src1 |src2 |dst | |
| 51 | * |:--------------|:------------------|:------|:--------------| |
| 52 | * |F16 |F16 |F16 |F16 | |
| 53 | * |F32 |F32 |F32 |F32 | |
Freddie Liardet | f727ef4 | 2021-10-18 13:28:57 +0100 | [diff] [blame] | 54 | * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | |
| 55 | * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 56 | * |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 57 | * @param[in, out] src0 Input tensor info. |
| 58 | * @param[in] src1 Set of kernels to convolve the input volume. |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 59 | * The 2nd dimension must be the same as the input's volume 1st dimension. |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 60 | * @param[in] src2 Set of biases. Can be nullptr. |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 61 | * @param[out] dst Output tensor info. |
| 62 | * The 1st dimensions must be equal to the 1st dimension of the @p kernels tensor. |
| 63 | * @param[in] conv_info Contains padding, stride, acitvation information. |
| 64 | * |
| 65 | */ |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 66 | void configure(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 67 | /** Static function to check if given info will lead to a valid configuration |
| 68 | * |
| 69 | * Similar to CpuDirectConv3dKernel::configure() |
| 70 | * |
| 71 | * @return a status |
| 72 | */ |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 73 | static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 74 | |
| 75 | // Inherited methods overridden: |
| 76 | void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; |
| 77 | const char *name() const override; |
| 78 | |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 79 | struct DirectConv3dKernel |
| 80 | { |
| 81 | const char *name; |
| 82 | const DataTypeISASelectorPtr is_selected; |
| 83 | DirectConv3dKernelPtr ukernel; |
| 84 | }; |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 85 | |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 86 | static const std::vector<DirectConv3dKernel> &get_available_kernels(); |
| 87 | |
| 88 | private: |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame] | 89 | Conv3dInfo _conv_info{}; |
| 90 | DirectConv3dKernelPtr _run_method{ nullptr }; |
| 91 | std::string _name{}; |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 92 | }; |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 93 | |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 94 | } // namespace kernels |
| 95 | } // namespace cpu |
| 96 | } // namespace arm_compute |
| 97 | #endif /*ARM_COMPUTE_CPU_DIRECTCONV3D_KERNEL_H */ |