Adnan AlSinan | 171fc3d | 2022-03-15 18:46:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "src/cpu/kernels/CpuPool3dKernel.h" |
| 25 | |
| 26 | #include "arm_compute/core/TensorInfo.h" |
| 27 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
| 28 | #include "src/core/CPP/Validate.h" |
| 29 | #include "src/core/common/Registrars.h" |
| 30 | #include "src/core/helpers/AutoConfiguration.h" |
| 31 | #include "src/core/helpers/WindowHelpers.h" |
| 32 | #include "src/cpu/kernels/pool3d/list.h" |
| 33 | |
| 34 | namespace arm_compute |
| 35 | { |
| 36 | namespace cpu |
| 37 | { |
| 38 | namespace kernels |
| 39 | { |
| 40 | namespace |
| 41 | { |
| 42 | using namespace misc::shape_calculator; |
| 43 | |
| 44 | static const std::vector<CpuPool3dKernel::Pooling3dKernel> available_kernels = |
| 45 | { |
| 46 | { |
Adnan AlSinan | 9104cd5 | 2022-04-06 16:19:31 +0100 | [diff] [blame] | 47 | "neon_qu8_ndhwc_poolMxNxD", |
| 48 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8); }, |
| 49 | REGISTER_QASYMM8_NEON(arm_compute::cpu::neon_q8_pool3d) |
| 50 | }, |
| 51 | { |
| 52 | "neon_qs8_ndhwc_poolMxNxD", |
| 53 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8_SIGNED); }, |
| 54 | REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::neon_q8_signed_pool3d) |
| 55 | }, |
| 56 | { |
Adnan AlSinan | 171fc3d | 2022-03-15 18:46:42 +0000 | [diff] [blame] | 57 | "neon_fp16_ndhwc_poolMxNxD", |
| 58 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::F16 && data.isa.fp16); }, |
| 59 | REGISTER_FP16_NEON(arm_compute::cpu::neon_fp16_pool3d) |
| 60 | }, |
Adnan AlSinan | 171fc3d | 2022-03-15 18:46:42 +0000 | [diff] [blame] | 61 | { |
| 62 | "neon_fp32_ndhwc_poolMxNxD", |
| 63 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::F32); }, |
| 64 | REGISTER_FP32_NEON(arm_compute::cpu::neon_fp32_pool3d) |
| 65 | } |
| 66 | }; |
| 67 | |
| 68 | Status validate_arguments(const ITensorInfo *src, const ITensorInfo *dst, const Pooling3dLayerInfo &pool_info) |
| 69 | { |
| 70 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst); |
| 71 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src->data_layout() != DataLayout::NDHWC, "Only NDHWC layout supported"); |
| 72 | ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src); |
Adnan AlSinan | 9104cd5 | 2022-04-06 16:19:31 +0100 | [diff] [blame] | 73 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::F16, DataType::F32, DataType::QASYMM8, DataType::QASYMM8_SIGNED); |
| 74 | |
| 75 | ARM_COMPUTE_RETURN_ERROR_ON_MSG((!is_data_type_float(src->data_type())) && (!pool_info.exclude_padding |
| 76 | && (pool_info.pool_type == PoolingType::AVG)), |
| 77 | "Exclude padding is unsupported for non-float types for Avg op"); |
Adnan AlSinan | 171fc3d | 2022-03-15 18:46:42 +0000 | [diff] [blame] | 78 | |
| 79 | const auto data_layout = src->data_layout(); |
| 80 | const int idx_width = get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH); |
| 81 | const int idx_height = get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT); |
| 82 | const int idx_depth = get_data_layout_dimension_index(data_layout, DataLayoutDimension::DEPTH); |
| 83 | |
| 84 | const bool is_global_pooling = pool_info.is_global_pooling; |
| 85 | const unsigned int pool_size_x = is_global_pooling ? src->dimension(idx_width) : pool_info.pool_size.width; |
| 86 | const unsigned int pool_size_y = is_global_pooling ? src->dimension(idx_height) : pool_info.pool_size.height; |
| 87 | const unsigned int pool_size_z = is_global_pooling ? src->dimension(idx_depth) : pool_info.pool_size.depth; |
| 88 | |
| 89 | const unsigned int stride_x = pool_info.stride.x(); |
| 90 | const unsigned int stride_y = pool_info.stride.y(); |
| 91 | const unsigned int stride_z = pool_info.stride.z(); |
| 92 | |
| 93 | ARM_COMPUTE_RETURN_ERROR_ON((pool_size_x == 0) || (pool_size_y == 0) || (pool_size_z == 0)); |
| 94 | ARM_COMPUTE_RETURN_ERROR_ON((stride_x == 0) || (stride_y == 0) || (stride_z == 0)); |
| 95 | |
| 96 | int output_width = 0; |
| 97 | int output_height = 0; |
| 98 | int output_depth = 0; |
| 99 | |
Adnan AlSinan | facd9dd | 2022-05-04 11:31:45 +0100 | [diff] [blame] | 100 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(is_pool_3d_region_entirely_outside_input(pool_info), "Pooling region that is entirely outside input tensor is unsupported"); |
| 101 | |
Adnan AlSinan | 171fc3d | 2022-03-15 18:46:42 +0000 | [diff] [blame] | 102 | std::tie(output_width, output_height, output_depth) = scaled_3d_dimensions_signed(src->tensor_shape()[idx_width], src->tensor_shape()[idx_height], src->tensor_shape()[idx_depth], |
| 103 | pool_size_x, pool_size_y, pool_size_z, pool_info); |
| 104 | ARM_COMPUTE_RETURN_ERROR_ON_MSG((output_width < 1 || output_height < 1 || output_depth < 1), "Calculated output dimension size is invalid"); |
| 105 | |
| 106 | if(dst->total_size() != 0) |
| 107 | { |
| 108 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst); |
| 109 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src, dst); |
| 110 | TensorInfo out_info(TensorInfo(compute_pool3d_shape(src->tensor_shape(), pool_info), 1, dst->data_type(), DataLayout::NDHWC)); |
| 111 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_SHAPES(dst, &out_info); |
| 112 | } |
| 113 | |
| 114 | const auto *uk = CpuPool3dKernel::get_implementation(DataTypeISASelectorData{ src->data_type(), CPUInfo::get().get_isa() }); |
| 115 | ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr); |
| 116 | |
| 117 | return Status{}; |
| 118 | } |
| 119 | } //namespace |
| 120 | |
| 121 | void CpuPool3dKernel::configure(const ITensorInfo *src, ITensorInfo *dst, const Pooling3dLayerInfo &pool_info) |
| 122 | { |
| 123 | ARM_COMPUTE_ERROR_ON_NULLPTR(src, dst); |
| 124 | |
| 125 | // Perform validation step |
| 126 | ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src, dst, pool_info)); |
| 127 | |
| 128 | // dst auto inizialitation if not yet initialized |
| 129 | auto_init_if_empty(*dst, src->clone()->set_tensor_shape(compute_pool3d_shape(src->tensor_shape(), pool_info))); |
| 130 | |
| 131 | // Get data layout |
| 132 | const auto data_layout = src->data_layout(); |
| 133 | const int idx_width = get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH); |
| 134 | const int idx_height = get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT); |
| 135 | const int idx_depth = get_data_layout_dimension_index(data_layout, DataLayoutDimension::DEPTH); |
| 136 | |
| 137 | // Update pool size in case of global pooling |
| 138 | const bool is_global_pooling = pool_info.is_global_pooling; |
| 139 | const Size3D pool_size( |
| 140 | is_global_pooling ? src->dimension(idx_width) : pool_info.pool_size.width, |
| 141 | is_global_pooling ? src->dimension(idx_height) : pool_info.pool_size.height, |
| 142 | is_global_pooling ? src->dimension(idx_depth) : pool_info.pool_size.depth); |
| 143 | |
| 144 | const auto *uk = CpuPool3dKernel::get_implementation(DataTypeISASelectorData{ src->data_type(), CPUInfo::get().get_isa() }); |
| 145 | ARM_COMPUTE_ERROR_ON(uk == nullptr); |
| 146 | |
| 147 | // Set instance variables |
| 148 | _pool_info = pool_info; |
| 149 | _run_method = uk->ukernel; |
| 150 | _name = std::string("CpuPool3dKernel").append("/").append(uk->name); |
| 151 | |
| 152 | // Configure kernel window |
| 153 | Window win = calculate_max_window(*dst, Steps()); |
| 154 | ICpuKernel::configure(win); |
| 155 | } |
| 156 | |
| 157 | Status CpuPool3dKernel::validate(const ITensorInfo *src, const ITensorInfo *dst, const Pooling3dLayerInfo &pool_info) |
| 158 | { |
| 159 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src); |
| 160 | |
| 161 | ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src, dst, pool_info)); |
| 162 | |
| 163 | return Status{}; |
| 164 | } |
| 165 | |
| 166 | void CpuPool3dKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) |
| 167 | { |
| 168 | ARM_COMPUTE_UNUSED(info); |
| 169 | ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this); |
| 170 | ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window); |
| 171 | ARM_COMPUTE_ERROR_ON(_run_method == nullptr); |
| 172 | |
| 173 | const ITensor *src = tensors.get_const_tensor(TensorType::ACL_SRC_0); |
| 174 | ITensor *dst = tensors.get_tensor(TensorType::ACL_DST_0); |
| 175 | |
| 176 | _run_method(src, dst, _pool_info, window); |
| 177 | } |
| 178 | |
| 179 | const char *CpuPool3dKernel::name() const |
| 180 | { |
| 181 | return _name.c_str(); |
| 182 | } |
| 183 | |
| 184 | const std::vector<CpuPool3dKernel::Pooling3dKernel> &CpuPool3dKernel::get_available_kernels() |
| 185 | { |
| 186 | return available_kernels; |
| 187 | } |
| 188 | |
| 189 | } // namespace kernels |
| 190 | } // namespace cpu |
| 191 | } // namespace arm_compute |