Release 18.02
Change-Id: I41a89c149534a7c354a58e2c66a32cba572fc0c1
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+------ ArmNN for Android 18.02 Release Notes ------
+
+This release of ArmNN for Android supports use as a driver for the Android Neural Networks API. It implements the android.hardware.neuralnetworks@1.0 interface.
+
+For more information on the Android Neural Networks API, see https://developer.android.com/ndk/guides/neuralnetworks/index.html
+
+For integration and usage documentation, please see README.md.
+
+--- Support for Android Neural Networks HAL operations ---
+
+The following AndroidNN operations are currently supported.
+
+AndroidNN operator Tensor type supported
+ADD (FLOAT32)
+AVERAGE_POOL_2D (FLOAT32,QUANT8_ASYMM)
+CONCATENATION (FLOAT32)
+CONV_2D (FLOAT32,QUANT8_ASYMM**)
+DEPTHWISE_CONV_2D*** (FLOAT32,QUANT8_ASYMM)
+FLOOR (FLOAT32)
+FULLY_CONNECTED (FLOAT32)
+L2_NORMALIZATION (FLOAT32)
+L2_POOL_2D (FLOAT32)
+LOCAL_RESPONSE_NORMALIZATION (FLOAT32)
+LOGISTIC (FLOAT32,QUANT8_ASYMM)
+MAX_POOL_2D (FLOAT32,QUANT8_ASYMM)
+MUL* (FLOAT32)
+RELU (FLOAT32,QUANT8_ASYMM)
+RELU1 (FLOAT32,QUANT8_ASYMM)
+RELU6 (FLOAT32,QUANT8_ASYMM)
+RESHAPE (FLOAT32,QUANT8_ASYMM)
+RESIZE_BILINEAR (FLOAT32)
+SOFTMAX (FLOAT32,QUANT8_ASYMM)
+TANH (FLOAT32)
+
+* MUL currently does not support mixing of different tensor sizes.
+
+** QUANT8_ASYMM version does not support asymmetric padding. In addition, only the following configurations are supported:
+ 1) 1x1 convolution with strides of 1 or 2 or 3
+ 2) 3x3 convolution with strides of 1 or 2
+ 3) 5x5 convolution with strides of 1 or 2
+
+*** Depthwise convolution only supports a value of 1 for the depth multiplier. In addition, the QUANT8_ASYMM version only supports 3x3 kernels.
+
+
+--- Unsupported operators ---
+
+The following AndroidNN operations are currently not supported.
+
+DEPTH_TO_SPACE
+DEQUANTIZE
+EMBEDDING_LOOKUP
+HASHTABLE_LOOKUP
+LSH_PROJECTION
+LSTM
+RNN
+SPACE_TO_DEPTH
+SVDF
+
+Where operations are not supported by the ArmNN Android NN Driver, the driver indicates this to the framework appropriately and the framework implements those operations using a CPU implementation.