diff --git a/test/1.2/Capabilities.cpp b/test/1.2/Capabilities.cpp
index aa0c642..41d5ee5 100644
--- a/test/1.2/Capabilities.cpp
+++ b/test/1.2/Capabilities.cpp
@@ -1,39 +1,12 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
-#include "../../1.2/ArmnnDriverImpl.hpp"
-
+#include "../DriverTestHelpers.hpp"
 #include "Utils.h"
 
-#include <armnn/utility/Assert.hpp>
-
-// Un-define some of the macros as they clash in 'third-party/doctest/doctest.h'
-// and 'system/core/base/include/android-base/logging.h'
-// macro redefined error[-Werror,-Wmacro-redefined]
-#ifdef CHECK
-#undef CHECK
-#endif
-#ifdef CHECK_EQ
-#undef CHECK_EQ
-#endif
-#ifdef CHECK_NE
-#undef CHECK_NE
-#endif
-#ifdef CHECK_GT
-#undef CHECK_GT
-#endif
-#ifdef CHECK_LT
-#undef CHECK_LT
-#endif
-#ifdef CHECK_GE
-#undef CHECK_GE
-#endif
-#ifdef CHECK_LE
-#undef CHECK_LE
-#endif
-#include <doctest/doctest.h>
+#include <1.2/ArmnnDriverImpl.hpp>
 
 #include <sys/system_properties.h>
 
@@ -86,15 +59,14 @@
 {
     using namespace armnn_driver::hal_1_2;
     V1_0::PerformanceInfo perfInfo = android::nn::lookup(capabilities.operandPerformance, type);
-    ARMNN_ASSERT(perfInfo.execTime == execTime);
-    ARMNN_ASSERT(perfInfo.powerUsage == powerUsage);
+    DOCTEST_CHECK(perfInfo.execTime == execTime);
+    DOCTEST_CHECK(perfInfo.powerUsage == powerUsage);
 }
 
-TEST_SUITE("CapabilitiesTests")
+DOCTEST_TEST_SUITE("CapabilitiesTests")
 {
-TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesWithRuntime")
+DOCTEST_TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesWithRuntime")
 {
-    using namespace armnn_driver::hal_1_2;
     using namespace android::nn;
 
     auto getCapabilitiesFn = [&](V1_0::ErrorStatus error, const V1_2::Capabilities& capabilities)
@@ -118,7 +90,8 @@
             CheckOperandType(capabilities, V1_2::OperandType::OEM, FLT_MAX, FLT_MAX);
             CheckOperandType(capabilities, V1_2::OperandType::TENSOR_OEM_BYTE, FLT_MAX, FLT_MAX);
 
-            ARMNN_ASSERT(error == V1_0::ErrorStatus::NONE);
+            bool result = (error == V1_0::ErrorStatus::NONE);
+            DOCTEST_CHECK(result);
         };
 
     __system_property_set("Armnn.operandTypeTensorFloat32Performance.execTime", "2.0f");
@@ -145,12 +118,11 @@
     armnn::IRuntime::CreationOptions options;
     armnn::IRuntimePtr runtime(armnn::IRuntime::Create(options));
 
-    ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn);
+    armnn_driver::hal_1_2::ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn);
 }
 
-TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesUndefined")
+DOCTEST_TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesUndefined")
 {
-    using namespace armnn_driver::hal_1_2;
     using namespace android::nn;
 
     float defaultValue = .1f;
@@ -179,13 +151,14 @@
             CheckOperandType(capabilities, V1_2::OperandType::OEM, FLT_MAX, FLT_MAX);
             CheckOperandType(capabilities, V1_2::OperandType::TENSOR_OEM_BYTE, FLT_MAX, FLT_MAX);
 
-            ARMNN_ASSERT(error == V1_0::ErrorStatus::NONE);
+            bool result = (error == V1_0::ErrorStatus::NONE);
+            DOCTEST_CHECK(result);
         };
 
     armnn::IRuntime::CreationOptions options;
     armnn::IRuntimePtr runtime(armnn::IRuntime::Create(options));
 
-    ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn);
+    armnn_driver::hal_1_2::ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn);
 }
 
 }
\ No newline at end of file
diff --git a/test/1.2/Dilation.cpp b/test/1.2/Dilation.cpp
index e1cde9f..c9182a7 100644
--- a/test/1.2/Dilation.cpp
+++ b/test/1.2/Dilation.cpp
@@ -1,17 +1,16 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
 #include "../Dilation.hpp"
 
-#include "../../1.2/HalPolicy.hpp"
+#include <1.2/HalPolicy.hpp>
 
-#include <doctest/doctest.h>
-
-TEST_SUITE("DilationTests")
+DOCTEST_TEST_SUITE("DilationTests")
 {
-TEST_CASE("ConvolutionExplicitPaddingNoDilation")
+
+DOCTEST_TEST_CASE("ConvolutionExplicitPaddingNoDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = false;
@@ -21,7 +20,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("ConvolutionExplicitPaddingDilation")
+DOCTEST_TEST_CASE("ConvolutionExplicitPaddingDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = false;
@@ -31,7 +30,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("ConvolutionImplicitPaddingNoDilation")
+DOCTEST_TEST_CASE("ConvolutionImplicitPaddingNoDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = false;
@@ -41,7 +40,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("ConvolutionImplicitPaddingDilation")
+DOCTEST_TEST_CASE("ConvolutionImplicitPaddingDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = false;
@@ -51,7 +50,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("DepthwiseConvolutionExplicitPaddingNoDilation")
+DOCTEST_TEST_CASE("DepthwiseConvolutionExplicitPaddingNoDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = true;
@@ -61,7 +60,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("DepthwiseConvolutionExplicitPaddingDilation")
+DOCTEST_TEST_CASE("DepthwiseConvolutionExplicitPaddingDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = true;
@@ -71,7 +70,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("DepthwiseConvolutionImplicitPaddingNoDilation")
+DOCTEST_TEST_CASE("DepthwiseConvolutionImplicitPaddingNoDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = true;
@@ -81,7 +80,7 @@
     DilationTestImpl<hal_1_2::HalPolicy>(options);
 }
 
-TEST_CASE("DepthwiseConvolutionImplicitPaddingDilation")
+DOCTEST_TEST_CASE("DepthwiseConvolutionImplicitPaddingDilation")
 {
     DilationTestOptions options;
     options.m_IsDepthwiseConvolution = true;
diff --git a/test/1.2/Lstm.cpp b/test/1.2/Lstm.cpp
index 70fbf70..59d5d38 100644
--- a/test/1.2/Lstm.cpp
+++ b/test/1.2/Lstm.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -7,52 +7,64 @@
 
 using namespace armnn_driver;
 
-TEST_SUITE("LstmTests_1.2_CpuRef")
+DOCTEST_TEST_SUITE("LstmTests_1.2_CpuRef")
 {
-    TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_armnn::Compute::CpuRef")
+
+    DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_armnn::Compute::CpuRef")
     {
         LstmNoCifgNoPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_CpuRef")
     {
         LstmCifgPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_CpuRef")
     {
         LstmNoCifgPeepholeProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_CpuRef")
     {
         LstmCifgPeepholeNoProjectionBatch2<hal_1_2::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("QuantizedLstmTest_1.2_CpuRef")
+
+    DOCTEST_TEST_CASE("QuantizedLstmTest_1.2_CpuRef")
     {
         QuantizedLstm<hal_1_2::HalPolicy>(armnn::Compute::CpuRef);
     }
+
 }
 
 #if defined(ARMCOMPUTECL_ENABLED)
-TEST_SUITE("LstmTests_1.2_GpuAcc")
+DOCTEST_TEST_SUITE("LstmTests_1.2_GpuAcc")
 {
-    TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_GpuAcc")
     {
         LstmNoCifgNoPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_GpuAcc")
     {
         LstmCifgPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_GpuAcc")
     {
         LstmNoCifgPeepholeProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_GpuAcc")
     {
         LstmCifgPeepholeNoProjectionBatch2<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc);
     }
-        TEST_CASE("QuantizedLstmTest_1.2_GpuAcc")
+
+    DOCTEST_TEST_CASE("QuantizedLstmTest_1.2_GpuAcc")
     {
         QuantizedLstm<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc);
     }
+
 }
 #endif