IVGCVSW-8260 Update Doxgen Docu for 24.05
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: If4bc983bf2793a27ded8e26ac2b29523fc1e4711
diff --git a/latest/_cl_batch_mat_mul_workload_8cpp_source.html b/latest/_cl_batch_mat_mul_workload_8cpp_source.html
index 3b11664..84da963 100644
--- a/latest/_cl_batch_mat_mul_workload_8cpp_source.html
+++ b/latest/_cl_batch_mat_mul_workload_8cpp_source.html
@@ -36,7 +36,7 @@
<img alt="ArmNN" src="Arm_NN_horizontal_blue.png" style="max-width: 15rem; margin-top: .5rem; margin-left 13px"/>
<td id="projectalign" style="padding-left: 0.9em;">
<div id="projectname">
-  <span id="projectnumber">24.02</span>
+  <span id="projectnumber">24.05</span>
</div>
</td>
</tr>
@@ -217,7 +217,7 @@
<div class="ttc" id="astructarmnn_1_1_batch_mat_mul_descriptor_html_acb441bb8db19bcce78d15cdd8ceb5ea0"><div class="ttname"><a href="structarmnn_1_1_batch_mat_mul_descriptor.html#acb441bb8db19bcce78d15cdd8ceb5ea0">armnn::BatchMatMulDescriptor::m_TransposeX</a></div><div class="ttdeci">bool m_TransposeX</div><div class="ttdoc">Transpose the slices of each input tensor Transpose and Adjoint can not both be set to true for the s...</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01612">Descriptors.hpp:1612</a></div></div>
<div class="ttc" id="astructarmnn_1_1_batch_mat_mul_descriptor_html_a0cf8306be7d301de0f095fff9901a525"><div class="ttname"><a href="structarmnn_1_1_batch_mat_mul_descriptor.html#a0cf8306be7d301de0f095fff9901a525">armnn::BatchMatMulDescriptor::m_AdjointX</a></div><div class="ttdeci">bool m_AdjointX</div><div class="ttdoc">Adjoint the slices of each input tensor Transpose and Adjoint can not both be set to true for the sam...</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01617">Descriptors.hpp:1617</a></div></div>
<div class="ttc" id="a_workload_utils_8hpp_html"><div class="ttname"><a href="_workload_utils_8hpp.html">WorkloadUtils.hpp</a></div></div>
-<div class="ttc" id="astructarmnn_1_1_queue_descriptor_html_a765d2cee4ccce5b9467e0c2b6d25b84a"><div class="ttname"><a href="structarmnn_1_1_queue_descriptor.html#a765d2cee4ccce5b9467e0c2b6d25b84a">armnn::QueueDescriptor::ValidateInputsOutputs</a></div><div class="ttdeci">void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const</div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8cpp_source.html#l00446">WorkloadData.cpp:446</a></div></div>
+<div class="ttc" id="astructarmnn_1_1_queue_descriptor_html_a765d2cee4ccce5b9467e0c2b6d25b84a"><div class="ttname"><a href="structarmnn_1_1_queue_descriptor.html#a765d2cee4ccce5b9467e0c2b6d25b84a">armnn::QueueDescriptor::ValidateInputsOutputs</a></div><div class="ttdeci">void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const</div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8cpp_source.html#l00447">WorkloadData.cpp:447</a></div></div>
<div class="ttc" id="anamespacearmnn_html_abfb0841058a8190d30851f07eca3991f"><div class="ttname"><a href="namespacearmnn.html#abfb0841058a8190d30851f07eca3991f">armnn::ConvertAdditionalInfoToAclActivationLayerInfo</a></div><div class="ttdeci">arm_compute::ActivationLayerInfo ConvertAdditionalInfoToAclActivationLayerInfo(const QueueDescriptor &queueDescriptor)</div><div class="ttdef"><b>Definition:</b> <a href="_arm_compute_utils_8hpp_source.html#l00105">ArmComputeUtils.hpp:105</a></div></div>
<div class="ttc" id="astructarmnn_1_1_batch_mat_mul_descriptor_html_aedca000a005e091c23191e82d7e81b1d"><div class="ttname"><a href="structarmnn_1_1_batch_mat_mul_descriptor.html#aedca000a005e091c23191e82d7e81b1d">armnn::BatchMatMulDescriptor::m_DataLayoutX</a></div><div class="ttdeci">DataLayout m_DataLayoutX</div><div class="ttdoc">Data layout of each input tensor, such as NHWC/NDHWC (leave as default for arbitrary layout)</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01621">Descriptors.hpp:1621</a></div></div>
<div class="ttc" id="aclassarmnn_1_1_tensor_info_html"><div class="ttname"><a href="classarmnn_1_1_tensor_info.html">armnn::TensorInfo</a></div><div class="ttdef"><b>Definition:</b> <a href="_tensor_8hpp_source.html#l00152">Tensor.hpp:152</a></div></div>
@@ -246,7 +246,7 @@
<div class="ttc" id="anamespacearmnn_html_a67a0db04d321a74b7e7fcfd3f1a3f70b"><div class="ttname"><a href="namespacearmnn.html#a67a0db04d321a74b7e7fcfd3f1a3f70b">armnn::Status</a></div><div class="ttdeci">Status</div><div class="ttdef"><b>Definition:</b> <a href="_types_8hpp_source.html#l00042">Types.hpp:42</a></div></div>
<div class="ttc" id="a_cl_tensor_handle_8hpp_html"><div class="ttname"><a href="_cl_tensor_handle_8hpp.html">ClTensorHandle.hpp</a></div></div>
<div class="ttc" id="aclassarmnn_1_1_base_workload_html_afb8d2c8817c75de9d01a4c0e0d5c160b"><div class="ttname"><a href="classarmnn_1_1_base_workload.html#afb8d2c8817c75de9d01a4c0e0d5c160b">armnn::BaseWorkload< BatchMatMulQueueDescriptor >::m_Data</a></div><div class="ttdeci">BatchMatMulQueueDescriptor m_Data</div><div class="ttdef"><b>Definition:</b> <a href="_workload_8hpp_source.html#l00089">Workload.hpp:89</a></div></div>
-<div class="ttc" id="anamespacearmnn_html_a52c299ca6a3884c609583a5a0663db80"><div class="ttname"><a href="namespacearmnn.html#a52c299ca6a3884c609583a5a0663db80">armnn::RunClFunction</a></div><div class="ttdeci">void RunClFunction(arm_compute::IFunction &function, const CheckLocation &location)</div><div class="ttdef"><b>Definition:</b> <a href="_cl_workload_utils_8hpp_source.html#l00168">ClWorkloadUtils.hpp:168</a></div></div>
+<div class="ttc" id="anamespacearmnn_html_a52c299ca6a3884c609583a5a0663db80"><div class="ttname"><a href="namespacearmnn.html#a52c299ca6a3884c609583a5a0663db80">armnn::RunClFunction</a></div><div class="ttdeci">void RunClFunction(arm_compute::IFunction &function, const CheckLocation &location)</div><div class="ttdef"><b>Definition:</b> <a href="_cl_workload_utils_8hpp_source.html#l00167">ClWorkloadUtils.hpp:167</a></div></div>
<div class="ttc" id="astructarmnn_1_1_workload_info_html_ac97905bfa0daab357b91df1347600309"><div class="ttname"><a href="structarmnn_1_1_workload_info.html#ac97905bfa0daab357b91df1347600309">armnn::WorkloadInfo::m_InputTensorInfos</a></div><div class="ttdeci">std::vector< TensorInfo > m_InputTensorInfos</div><div class="ttdef"><b>Definition:</b> <a href="_workload_info_8hpp_source.html#l00018">WorkloadInfo.hpp:18</a></div></div>
<div class="ttc" id="a_cl_batch_mat_mul_workload_8hpp_html"><div class="ttname"><a href="_cl_batch_mat_mul_workload_8hpp.html">ClBatchMatMulWorkload.hpp</a></div></div>
<div class="ttc" id="anamespacearmnn_html"><div class="ttname"><a href="namespacearmnn.html">armnn</a></div><div class="ttdoc">Copyright (c) 2021 ARM Limited and Contributors.</div><div class="ttdef"><b>Definition:</b> <a href="01__00__quick__start_8dox_source.html#l00006">01_00_quick_start.dox:6</a></div></div>
@@ -257,7 +257,7 @@
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<li class="navelem"><a class="el" href="dir_68267d1309a1af8e8297ef4c3efbcdba.html">src</a></li><li class="navelem"><a class="el" href="dir_0f3cdec46afbc61a1ded8e1687c9c9a0.html">backends</a></li><li class="navelem"><a class="el" href="dir_1ad86c6d39ab715a831555571b9e98a5.html">cl</a></li><li class="navelem"><a class="el" href="dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.html">workloads</a></li><li class="navelem"><a class="el" href="_cl_batch_mat_mul_workload_8cpp.html">ClBatchMatMulWorkload.cpp</a></li>
- <li class="footer">Generated on Wed Feb 14 2024 16:36:15 for Arm NN by
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