commit 1dc83febfb76d6a770bdf3ba16c4034a970c2320
author Nikhil Raj <nikhil.raj@arm.com> Thu May 16 09:47:51 2024 +0100
committer Nikhil Raj <nikhil.raj@arm.com> Thu May 16 09:47:51 2024 +0100
tree 66d27e5587e9010f3db26a23a348df844c88f8e6
parent 38b600d8abb2c5f7a44511b5deddf441f975d51d

IVGCVSW-8260 Update Doxgen Docu for 24.05

Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: If4bc983bf2793a27ded8e26ac2b29523fc1e4711

latest/_gpu_fsa_batch_mat_mul_8cpp_source.html

diff --git a/latest/_gpu_fsa_batch_mat_mul_8cpp_source.html b/latest/_gpu_fsa_batch_mat_mul_8cpp_source.html
index d29d6af..62da790 100644
--- a/latest/_gpu_fsa_batch_mat_mul_8cpp_source.html
+++ b/latest/_gpu_fsa_batch_mat_mul_8cpp_source.html
@@ -36,7 +36,7 @@
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-   &#160;<span id="projectnumber">24.02</span>
+   &#160;<span id="projectnumber">24.05</span>
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@@ -208,7 +208,7 @@
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 <div class="ttc" id="aclassarmnn_1_1_tensor_info_html"><div class="ttname"><a href="classarmnn_1_1_tensor_info.html">armnn::TensorInfo</a></div><div class="ttdef"><b>Definition:</b> <a href="_tensor_8hpp_source.html#l00152">Tensor.hpp:152</a></div></div>
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-<div class="ttc" id="aclassarmnn_1_1_tensor_info_html_a945263e85c27f3216a8323cfc16d8919"><div class="ttname"><a href="classarmnn_1_1_tensor_info.html#a945263e85c27f3216a8323cfc16d8919">armnn::TensorInfo::IsConstant</a></div><div class="ttdeci">bool IsConstant() const</div><div class="ttdef"><b>Definition:</b> <a href="_tensor_8cpp_source.html#l00509">Tensor.cpp:509</a></div></div>
+<div class="ttc" id="aclassarmnn_1_1_tensor_info_html_a945263e85c27f3216a8323cfc16d8919"><div class="ttname"><a href="classarmnn_1_1_tensor_info.html#a945263e85c27f3216a8323cfc16d8919">armnn::TensorInfo::IsConstant</a></div><div class="ttdeci">bool IsConstant() const</div><div class="ttdef"><b>Definition:</b> <a href="_tensor_8cpp_source.html#l00513">Tensor.cpp:513</a></div></div>
 <div class="ttc" id="astructarmnn_1_1_gpu_fsa_pre_compiled_blob_html_a479b90f0b24c427502d94b716117e034"><div class="ttname"><a href="structarmnn_1_1_gpu_fsa_pre_compiled_blob.html#a479b90f0b24c427502d94b716117e034">armnn::GpuFsaPreCompiledBlob::inputTensorInfos</a></div><div class="ttdeci">std::unique_ptr&lt; std::vector&lt; arm_compute::ITensorInfo * &gt; &gt; inputTensorInfos</div><div class="ttdef"><b>Definition:</b> <a href="_gpu_fsa_backend_8hpp_source.html#l00037">GpuFsaBackend.hpp:37</a></div></div>
 <div class="ttc" id="astructarmnn_1_1_batch_mat_mul_descriptor_html_a112b466e5d2ab9d1887178adbe3afa1c"><div class="ttname"><a href="structarmnn_1_1_batch_mat_mul_descriptor.html#a112b466e5d2ab9d1887178adbe3afa1c">armnn::BatchMatMulDescriptor::m_TransposeY</a></div><div class="ttdeci">bool m_TransposeY</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01613">Descriptors.hpp:1613</a></div></div>
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@@ -227,7 +227,7 @@
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-    <li class="footer">Generated on Wed Feb 14 2024 16:36:16 for Arm NN by
+    <li class="footer">Generated on Thu May 16 2024 09:31:47 for Arm NN by
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