commit 1dc83febfb76d6a770bdf3ba16c4034a970c2320
author Nikhil Raj <nikhil.raj@arm.com> Thu May 16 09:47:51 2024 +0100
committer Nikhil Raj <nikhil.raj@arm.com> Thu May 16 09:47:51 2024 +0100
tree 66d27e5587e9010f3db26a23a348df844c88f8e6
parent 38b600d8abb2c5f7a44511b5deddf441f975d51d

IVGCVSW-8260 Update Doxgen Docu for 24.05

Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: If4bc983bf2793a27ded8e26ac2b29523fc1e4711

latest/dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.js

diff --git a/latest/dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.js b/latest/dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.js
index da03249..475a21c 100644
--- a/latest/dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.js
+++ b/latest/dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.js
@@ -116,6 +116,8 @@
     [ "ClReverseV2Workload.hpp", "_cl_reverse_v2_workload_8hpp.html", "_cl_reverse_v2_workload_8hpp" ],
     [ "ClRsqrtWorkload.cpp", "_cl_rsqrt_workload_8cpp.html", "_cl_rsqrt_workload_8cpp" ],
     [ "ClRsqrtWorkload.hpp", "_cl_rsqrt_workload_8hpp.html", "_cl_rsqrt_workload_8hpp" ],
+    [ "ClScatterNdWorkload.cpp", "_cl_scatter_nd_workload_8cpp.html", "_cl_scatter_nd_workload_8cpp" ],
+    [ "ClScatterNdWorkload.hpp", "_cl_scatter_nd_workload_8hpp.html", "_cl_scatter_nd_workload_8hpp" ],
     [ "ClSinWorkload.cpp", "_cl_sin_workload_8cpp.html", "_cl_sin_workload_8cpp" ],
     [ "ClSinWorkload.hpp", "_cl_sin_workload_8hpp.html", "_cl_sin_workload_8hpp" ],
     [ "ClSliceWorkload.cpp", "_cl_slice_workload_8cpp.html", "_cl_slice_workload_8cpp" ],