IVGCVSW-7094 Add LOG and SIN support to tflite parser
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I979a6f43c0d6ec49effb9a87339dbcd07678d2bd
diff --git a/docs/05_01_parsers.dox b/docs/05_01_parsers.dox
index 99178ac..39fe536 100644
--- a/docs/05_01_parsers.dox
+++ b/docs/05_01_parsers.dox
@@ -144,6 +144,7 @@
- LEAKY_RELU
- LESS
- LESS_EQUAL
+- LOG
- LOGICAL_NOT
- LOGISTIC
- LOG_SOFTMAX
@@ -171,6 +172,7 @@
- RESIZE_NEAREST_NEIGHBOR
- RSQRT
- SHAPE
+- SIN
- SLICE
- SOFTMAX
- SPACE_TO_BATCH
diff --git a/src/armnnTfLiteParser/TfLiteParser.cpp b/src/armnnTfLiteParser/TfLiteParser.cpp
index 5dbb5ee..91420ab 100644
--- a/src/armnnTfLiteParser/TfLiteParser.cpp
+++ b/src/armnnTfLiteParser/TfLiteParser.cpp
@@ -708,6 +708,7 @@
m_ParserFunctions[tflite::BuiltinOperator_LESS_EQUAL] = &TfLiteParserImpl::ParseLessOrEqual;
m_ParserFunctions[tflite::BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION]
= &TfLiteParserImpl::ParseLocalResponseNormalization;
+ m_ParserFunctions[tflite::BuiltinOperator_LOG] = &TfLiteParserImpl::ParseLog;
m_ParserFunctions[tflite::BuiltinOperator_LOGICAL_NOT] = &TfLiteParserImpl::ParseLogicalNot;
m_ParserFunctions[tflite::BuiltinOperator_LOGISTIC] = &TfLiteParserImpl::ParseLogistic;
m_ParserFunctions[tflite::BuiltinOperator_LOG_SOFTMAX] = &TfLiteParserImpl::ParseLogSoftmax;
@@ -736,6 +737,7 @@
m_ParserFunctions[tflite::BuiltinOperator_RSQRT] = &TfLiteParserImpl::ParseRsqrt;
m_ParserFunctions[tflite::BuiltinOperator_SQRT] = &TfLiteParserImpl::ParseSqrt;
m_ParserFunctions[tflite::BuiltinOperator_SHAPE] = &TfLiteParserImpl::ParseShape;
+ m_ParserFunctions[tflite::BuiltinOperator_SIN] = &TfLiteParserImpl::ParseSin;
m_ParserFunctions[tflite::BuiltinOperator_SLICE] = &TfLiteParserImpl::ParseSlice;
m_ParserFunctions[tflite::BuiltinOperator_SOFTMAX] = &TfLiteParserImpl::ParseSoftmax;
m_ParserFunctions[tflite::BuiltinOperator_SPACE_TO_BATCH_ND] = &TfLiteParserImpl::ParseSpaceToBatchND;
@@ -4160,16 +4162,6 @@
RegisterOutputSlots(subgraphIndex, operatorIndex, layer, outputTensorIndexes);
}
-void TfLiteParserImpl::ParseAbs(size_t subgraphIndex, size_t operatorIndex)
-{
- ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Abs);
-}
-
-void TfLiteParserImpl::ParseExp(size_t subgraphIndex, size_t operatorIndex)
-{
- ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Exp);
-}
-
void TfLiteParserImpl::ParseLocalResponseNormalization(size_t subgraphIndex, size_t operatorIndex)
{
CHECK_MODEL(m_Model, subgraphIndex, operatorIndex);
@@ -4214,6 +4206,21 @@
RegisterOutputSlots(subgraphIndex, operatorIndex, layer, {outputTensorIndexes[0]});
}
+void TfLiteParserImpl::ParseAbs(size_t subgraphIndex, size_t operatorIndex)
+{
+ ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Abs);
+}
+
+void TfLiteParserImpl::ParseExp(size_t subgraphIndex, size_t operatorIndex)
+{
+ ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Exp);
+}
+
+void TfLiteParserImpl::ParseLog(size_t subgraphIndex, size_t operatorIndex)
+{
+ ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Log);
+}
+
void TfLiteParserImpl::ParseLogicalNot(size_t subgraphIndex, size_t operatorIndex)
{
ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::LogicalNot);
@@ -4229,6 +4236,11 @@
ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Rsqrt);
}
+void TfLiteParserImpl::ParseSin(size_t subgraphIndex, size_t operatorIndex)
+{
+ ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Sin);
+}
+
void TfLiteParserImpl::ParseSqrt(size_t subgraphIndex, size_t operatorIndex)
{
ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Sqrt);
diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp
index 43c5466..e742d30 100644
--- a/src/armnnTfLiteParser/TfLiteParser.hpp
+++ b/src/armnnTfLiteParser/TfLiteParser.hpp
@@ -143,6 +143,7 @@
void ParseLeakyRelu(size_t subgraphIndex, size_t operatorIndex);
void ParseLess(size_t subgraphIndex, size_t operatorIndex);
void ParseLessOrEqual(size_t subgraphIndex, size_t operatorIndex);
+ void ParseLog(size_t subgraphIndex, size_t operatorIndex);
void ParseLocalResponseNormalization(size_t subgraphIndex, size_t operatorIndex);
void ParseLogicalNot(size_t subgraphIndex, size_t operatorIndex);
void ParseLogistic(size_t subgraphIndex, size_t operatorIndex);
@@ -173,6 +174,7 @@
void ParseResizeNearestNeighbor(size_t subgraphIndex, size_t operatorIndex);
void ParseRsqrt(size_t subgraphIndex, size_t operatorIndex);
void ParseShape(size_t subgraphIndex, size_t operatorIndex);
+ void ParseSin(size_t subgraphIndex, size_t operatorIndex);
void ParseSlice(size_t subgraphIndex, size_t operatorIndex);
void ParseSoftmax(size_t subgraphIndex, size_t operatorIndex);
void ParseSqrt(size_t subgraphIndex, size_t operatorIndex);
diff --git a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
index bab9a05..67c2080 100644
--- a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
+++ b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -104,6 +104,19 @@
20.0855185f, 54.5980834f, 148.4129329f} } });
}
+struct SimpleLogFixture : public ElementWiseUnaryFixture
+{
+ SimpleLogFixture() : ElementWiseUnaryFixture("LOG", "FLOAT32", "[ 1, 2, 3, 1 ]", "[ 1, 2, 3, 1 ]") {}
+};
+
+TEST_CASE_FIXTURE(SimpleLogFixture, "ParseLog")
+{
+ RunTest<4, armnn::DataType::Float32>(0, {{ "inputTensor", { 1.0f, 1.0f, 2.0f,
+ 3.0f, 4.0f, 2.71828f} }},
+ {{ "outputTensor",{ 0.f, 0.f, 0.69314718056f,
+ 1.09861228867f, 1.38629436112f, 0.99999932734f} } });
+}
+
struct SimpleLogicalNotFixture : public ElementWiseUnaryFixture
{
SimpleLogicalNotFixture() : ElementWiseUnaryFixture("LOGICAL_NOT", "BOOL", "[ 1, 1, 1, 4 ]", "[ 1, 1, 1, 4 ]") {}
@@ -154,4 +167,17 @@
5.0f, 6.0f, 7.0f} }});
}
+struct SimpleSinFixture : public ElementWiseUnaryFixture
+{
+ SimpleSinFixture() : ElementWiseUnaryFixture("SIN", "FLOAT32", "[ 1, 2, 3, 1 ]", "[ 1, 2, 3, 1 ]") {}
+};
+
+TEST_CASE_FIXTURE(SimpleSinFixture, "ParseSin")
+{
+ RunTest<4, armnn::DataType::Float32>(0, {{ "inputTensor", { 0.0f, 1.0f, 16.0f,
+ 0.5f, 36.0f, -1.f } }},
+ {{ "outputTensor",{ 0.0f, 0.8414709848f, -0.28790331666f,
+ 0.4794255386f, -0.99177885344f, -0.8414709848f} }});
+}
+
}