IVGCVSW-6620 Update the async api to use ExecutionData
* ExecutionData holds a void* which can be assigned to data required
for execution in a backend. WorkingMemDescriptors are used in the Ref
backend which hold TensorHandles for inputs and outputs.
* Updated ExecuteAsync functions to take ExecutionData.
* Added CreateExecutionData and UpdateExectutionData to IBackendInternal.
* Streamlined experimental IWorkingMemHandle API by removing map related
function and unused m_workingMemDescriptorMap from WorkingMemHandle.
Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com>
Change-Id: I54b0aab12872011743a141eb42dae200227769af
diff --git a/src/armnn/ExecutionData.hpp b/src/armnn/ExecutionData.hpp
new file mode 100644
index 0000000..69c8f3f
--- /dev/null
+++ b/src/armnn/ExecutionData.hpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+namespace armnn
+{
+
+namespace experimental
+{
+
+struct ExecutionData
+{
+ void* m_Data;
+};
+
+} // end experimental namespace
+
+} // end armnn namespace
diff --git a/src/armnn/LoadedNetwork.cpp b/src/armnn/LoadedNetwork.cpp
index 8e664e6..5dd7b6c 100644
--- a/src/armnn/LoadedNetwork.cpp
+++ b/src/armnn/LoadedNetwork.cpp
@@ -9,12 +9,14 @@
#include "Profiling.hpp"
#include "HeapProfiling.hpp"
#include "WorkingMemHandle.hpp"
+#include "ExecutionData.hpp"
#include <armnn/BackendHelper.hpp>
#include <armnn/BackendRegistry.hpp>
#include <armnn/Logging.hpp>
#include <armnn/backends/TensorHandle.hpp>
+#include <armnn/backends/IBackendInternal.hpp>
#include <armnn/backends/IMemoryManager.hpp>
#include <armnn/backends/MemCopyWorkload.hpp>
@@ -642,9 +644,13 @@
m_ConstantTensorHandles[layer->GetGuid()] = tensorHandle;
tensorHandle->Allocate();
+ auto& backend = m_Backends.at(layer->GetBackendId());
+
WorkingMemDescriptor memDesc;
memDesc.m_Outputs.push_back(tensorHandle);
- m_ConstantWorkloads[layer->GetGuid()]->ExecuteAsync(memDesc);
+
+ ExecutionData executionData = backend->CreateExecutionData(memDesc);
+ m_ConstantWorkloads[layer->GetGuid()]->ExecuteAsync(executionData);
}
}
}
@@ -1717,15 +1723,15 @@
throw InvalidArgumentException(fmt::format("ClearImportedOutputs::Unknown ImportedOutputId: {}", id));
}
- auto& importedTensorHandle = m_PreImportedOutputHandles[id].m_TensorHandle;
- if (!importedTensorHandle)
- {
- throw InvalidArgumentException(
- fmt::format("ClearImportedOutputs::ImportedOutput with id: {} has already been deleted", id));
- }
- // Call Unimport then destroy the tensorHandle
- importedTensorHandle->Unimport();
- importedTensorHandle = {};
+ auto& importedTensorHandle = m_PreImportedOutputHandles[id].m_TensorHandle;
+ if (!importedTensorHandle)
+ {
+ throw InvalidArgumentException(
+ fmt::format("ClearImportedOutputs::ImportedOutput with id: {} has already been deleted", id));
+ }
+ // Call Unimport then destroy the tensorHandle
+ importedTensorHandle->Unimport();
+ importedTensorHandle = {};
}
}
@@ -1882,7 +1888,6 @@
const auto& preimportedHandle = importedOutputPin.m_TensorHandle;
auto outputConnections = workingMemHandle.GetOutputConnection(layerBindingId);
-
for (auto it : outputConnections)
{
*it = preimportedHandle.get();
@@ -1895,7 +1900,7 @@
ARMNN_LOG(error) << "An error occurred attempting to execute a workload: " << error.what();
executionSucceeded = false;
};
- ProfilingDynamicGuid workloadInferenceID(0);
+ ProfilingDynamicGuid workloadInferenceID(0);
try
{
@@ -1907,7 +1912,8 @@
workloadInferenceID = timelineUtils->RecordWorkloadInferenceAndStartOfLifeEvent(workload->GetGuid(),
inferenceGuid);
}
- workload->ExecuteAsync(workingMemHandle.GetWorkingMemDescriptorAt(i));
+
+ workload->ExecuteAsync(workingMemHandle.GetExecutionDataAt(i).second);
if (timelineUtils)
{
@@ -1961,7 +1967,7 @@
std::vector<std::unique_ptr<ITensorHandle>> unmanagedTensorHandles;
std::vector<WorkingMemDescriptor> workingMemDescriptors;
- std::unordered_map<LayerGuid, WorkingMemDescriptor> workingMemDescriptorMap;
+ std::vector<std::pair<BackendId, ExecutionData>> executionDataVec;
auto GetTensorHandle = [&](Layer* layer, const OutputSlot& outputSlot)
{
@@ -2142,13 +2148,19 @@
handleInfo.m_InputMemDescriptorCoords.m_InputSlotCoords.emplace_back(connectionLocation);
}
}
- workingMemDescriptorMap.insert({layer->GetGuid(), workingMemDescriptor});
// Input/Output layers/workloads will not be executed, so the descriptor is not added to workingMemDescriptors
// However we will still need to manage the tensorHandle
if (!isInputLayer)
{
+ // Simply auto initialise ExecutionData here, so it's added only for the layer that require execution.
+ // The memory and data will be allocated/assigned for the void* in WorkingMemHandle::Allocate.
+ std::pair<BackendId, ExecutionData> dataPair;
+ dataPair.first = layer->GetBackendId();
+
+ executionDataVec.push_back(dataPair);
workingMemDescriptors.push_back(workingMemDescriptor);
+
layerIndex++;
}
}
@@ -2185,11 +2197,12 @@
inputConnectionsInfo,
outputConnectionsInfo,
workingMemDescriptors,
- workingMemDescriptorMap,
std::move(externalMemoryManager),
std::move(tensorMemory),
std::move(managedTensorHandles),
- std::move(unmanagedTensorHandles));
+ std::move(unmanagedTensorHandles),
+ executionDataVec,
+ &m_Backends);
}
void LoadedNetwork::RegisterDebugCallback(const DebugCallbackFunction& func)
diff --git a/src/armnn/WorkingMemHandle.cpp b/src/armnn/WorkingMemHandle.cpp
index 70bdd59..e800c42 100644
--- a/src/armnn/WorkingMemHandle.cpp
+++ b/src/armnn/WorkingMemHandle.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,20 +19,22 @@
std::vector<InputMemDescriptorCoords> inputLayerInfo,
std::vector<OutputMemDescriptorCoords> outputLayerInfo,
std::vector<WorkingMemDescriptor> workingMemDescriptors,
- std::unordered_map<LayerGuid, WorkingMemDescriptor> workingMemDescriptorMap,
std::unique_ptr<MemoryManager> memoryManager,
std::vector<std::pair<std::shared_ptr<TensorMemory>, MemorySource>> tensorMemory,
std::vector<std::unique_ptr<ITensorHandle>> managedTensorHandles,
- std::vector<std::unique_ptr<ITensorHandle>> unmanagedTensorHandles)
+ std::vector<std::unique_ptr<ITensorHandle>> unmanagedTensorHandles,
+ std::vector<std::pair<BackendId, ExecutionData>> executionDataVec,
+ BackendPtrMap* backends)
: m_NetworkId(networkId)
, m_WorkingMemDescriptors(workingMemDescriptors)
- , m_WorkingMemDescriptorMap(workingMemDescriptorMap)
, m_MemoryManager(std::move(memoryManager))
, m_TensorMemory(std::move(tensorMemory))
, m_ManagedTensorHandles(std::move(managedTensorHandles))
, m_UnmanagedTensorHandles(std::move(unmanagedTensorHandles))
, m_InputSize(numeric_cast<DifferenceType>(inputLayerInfo.size()))
, m_IsAllocated(false)
+ , m_ExecutionDataVec(executionDataVec)
+ , m_Backends(backends)
{
for (const auto& inputInfo : inputLayerInfo)
{
@@ -109,6 +111,15 @@
{
m_ManagedTensorHandles[i]->Import(m_TensorMemory[i].first->m_Data, m_TensorMemory[i].second);
}
+
+ // Assign previously allocated ExecutionData. Needs to be assigned after allocation so the void* are allocated.
+ for (unsigned int i = 0; i < m_ExecutionDataVec.size(); ++i)
+ {
+ auto& backend = m_Backends->at(m_ExecutionDataVec[i].first);
+
+ ExecutionData executionData = backend->CreateExecutionData(GetWorkingMemDescriptorAt(i));
+ m_ExecutionDataVec[i].second = executionData;
+ }
}
void WorkingMemHandle::Free()
diff --git a/src/armnn/WorkingMemHandle.hpp b/src/armnn/WorkingMemHandle.hpp
index bca1d2d..dc62b9a 100644
--- a/src/armnn/WorkingMemHandle.hpp
+++ b/src/armnn/WorkingMemHandle.hpp
@@ -1,16 +1,18 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
+#include "ExecutionData.hpp"
#include "Layer.hpp"
#include "Network.hpp"
#include "WorkingMemDescriptor.hpp"
#include <armnn/IWorkingMemHandle.hpp>
#include <armnn/Tensor.hpp>
+#include <armnn/backends/IBackendInternal.hpp>
#include <unordered_map>
#include <mutex>
@@ -22,6 +24,7 @@
namespace experimental
{
+using BackendPtrMap = std::unordered_map<BackendId, IBackendInternalUniquePtr>;
class WorkingMemHandle final : public IWorkingMemHandle
{
@@ -48,11 +51,12 @@
std::vector<InputMemDescriptorCoords> inputLayerInfo,
std::vector<OutputMemDescriptorCoords> outputLayerInfo,
std::vector<WorkingMemDescriptor> workingMemDescriptors,
- std::unordered_map<LayerGuid, WorkingMemDescriptor> workingMemDescriptorMap,
std::unique_ptr<MemoryManager> memoryManager,
std::vector<std::pair<std::shared_ptr<TensorMemory>, MemorySource>> tensorMemory,
std::vector<std::unique_ptr<ITensorHandle>> managedTensorHandles,
- std::vector<std::unique_ptr<ITensorHandle>> unmanagedTensorHandles);
+ std::vector<std::unique_ptr<ITensorHandle>> unmanagedTensorHandles,
+ std::vector<std::pair<BackendId, ExecutionData>> executionDataVec,
+ BackendPtrMap* backends);
~WorkingMemHandle()
{ Free(); }
@@ -75,14 +79,6 @@
return m_IsAllocated;
}
- /// Get the WorkingMemDescriptor for a Layer.
- WorkingMemDescriptor& GetWorkingMemDescriptor(LayerGuid id) override
- {
- auto result = m_WorkingMemDescriptorMap.find(id);
- ARMNN_ASSERT(result != m_WorkingMemDescriptorMap.end());
- return result->second;
- }
-
/// Get the WorkingMemDescriptor at an index. The WorkingMemDescriptors are stored in the same order as
/// the Workloads in a topologically sorted graph.
WorkingMemDescriptor& GetWorkingMemDescriptorAt(unsigned int id) override
@@ -90,6 +86,14 @@
return m_WorkingMemDescriptors[id];
}
+ /// Get the ExecutionData at an index.
+ /// The ExecutionData is paired with a BackendId to be able to call backend specific functions upon it.
+ /// The ExecutionData are stored in the same order as the Workloads in a topologically sorted graph.
+ std::pair<BackendId, ExecutionData>& GetExecutionDataAt(unsigned int id) override
+ {
+ return m_ExecutionDataVec[id];
+ }
+
ITensorHandle* GetInputHandle(LayerBindingId layerBindingId) const
{
return m_InputHandleMap.at(layerBindingId);
@@ -129,14 +133,12 @@
std::unordered_map<LayerBindingId, std::vector<std::vector<ITensorHandle*>::iterator>> m_OutputConnectionMap;
std::vector<WorkingMemDescriptor> m_WorkingMemDescriptors;
- std::unordered_map<LayerGuid, WorkingMemDescriptor> m_WorkingMemDescriptorMap;
std::unique_ptr<MemoryManager> m_MemoryManager;
// Memory to be imported into the tensorHandles after allocation
std::vector<std::pair<std::shared_ptr<TensorMemory>, MemorySource>> m_TensorMemory;
-
// Tensors that will need to be allocated internally within armnn
std::vector<std::unique_ptr<ITensorHandle>> m_ManagedTensorHandles;
@@ -151,6 +153,10 @@
DifferenceType m_InputSize;
bool m_IsAllocated;
+
+ std::vector<std::pair<BackendId, ExecutionData>> m_ExecutionDataVec;
+
+ BackendPtrMap* m_Backends;
};
} // end experimental namespace
diff --git a/src/backends/backendsCommon/MemCopyWorkload.cpp b/src/backends/backendsCommon/MemCopyWorkload.cpp
index 09d0e6c..3e0782a 100644
--- a/src/backends/backendsCommon/MemCopyWorkload.cpp
+++ b/src/backends/backendsCommon/MemCopyWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -63,11 +63,14 @@
}
}
-void CopyMemGenericWorkload::ExecuteAsync(WorkingMemDescriptor& descriptor)
+void CopyMemGenericWorkload::ExecuteAsync(ExecutionData& executionData)
{
ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "CopyMemGeneric_Execute_WorkingMemDescriptor");
+
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
std::vector<TensorHandlePair> tensorHandlePairs;
- GatherTensorHandlePairs(descriptor, tensorHandlePairs);
+
+ GatherTensorHandlePairs(*workingMemDescriptor, tensorHandlePairs);
auto copyFunc = [](void* dst, const void* src, size_t size)
{
diff --git a/src/backends/backendsCommon/MemSyncWorkload.cpp b/src/backends/backendsCommon/MemSyncWorkload.cpp
index af68306..79df2d2 100644
--- a/src/backends/backendsCommon/MemSyncWorkload.cpp
+++ b/src/backends/backendsCommon/MemSyncWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -27,11 +27,13 @@
m_TensorHandle->Unmap();
}
-void SyncMemGenericWorkload::ExecuteAsync(WorkingMemDescriptor& descriptor)
+void SyncMemGenericWorkload::ExecuteAsync(ExecutionData& executionData)
{
ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "SyncMemGeneric_Execute_WorkingMemDescriptor");
- descriptor.m_Inputs[0]->Map(true);
- descriptor.m_Inputs[0]->Unmap();
+
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ workingMemDescriptor->m_Inputs[0]->Map(true);
+ workingMemDescriptor->m_Inputs[0]->Unmap();
}
} //namespace armnn
diff --git a/src/backends/backendsCommon/MemSyncWorkload.hpp b/src/backends/backendsCommon/MemSyncWorkload.hpp
index eb26517..df54a65 100644
--- a/src/backends/backendsCommon/MemSyncWorkload.hpp
+++ b/src/backends/backendsCommon/MemSyncWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
@@ -19,7 +19,7 @@
public:
SyncMemGenericWorkload(const MemSyncQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& descriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
ITensorHandle* m_TensorHandle;
diff --git a/src/backends/backendsCommon/test/DefaultAsyncExecuteTest.cpp b/src/backends/backendsCommon/test/DefaultAsyncExecuteTest.cpp
index b1ee89a..0863ee4 100644
--- a/src/backends/backendsCommon/test/DefaultAsyncExecuteTest.cpp
+++ b/src/backends/backendsCommon/test/DefaultAsyncExecuteTest.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -46,13 +46,14 @@
}
}
- void ExecuteAsync(WorkingMemDescriptor& desc)
+ void ExecuteAsync(ExecutionData& executionData)
{
- int* inVals = static_cast<int*>(desc.m_Inputs[0][0].Map());
- int* outVals = static_cast<int*>(desc.m_Outputs[0][0].Map());
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ int* inVals = static_cast<int*>(workingMemDescriptor->m_Inputs[0][0].Map());
+ int* outVals = static_cast<int*>(workingMemDescriptor->m_Outputs[0][0].Map());
for (unsigned int i = 0;
- i < desc.m_Inputs[0][0].GetShape().GetNumElements();
+ i < workingMemDescriptor->m_Inputs[0][0].GetShape().GetNumElements();
++i)
{
outVals[i] = inVals[i] + outVals[i];
@@ -147,7 +148,10 @@
workingMemDescriptor0.m_Inputs = std::vector<ITensorHandle*>{&asyncInput0};
workingMemDescriptor0.m_Outputs = std::vector<ITensorHandle*>{&asyncOutput0};
- workload0.get()->ExecuteAsync(workingMemDescriptor0);
+ ExecutionData executionData;
+ executionData.m_Data = &workingMemDescriptor0;
+
+ workload0.get()->ExecuteAsync(executionData);
// Inputs are also changed by the execute/executeAsync calls to make sure there is no interference with them
ValidateTensor(workingMemDescriptor0.m_Outputs[0], expectedExecuteAsyncval);
@@ -183,7 +187,10 @@
workingMemDescriptor.m_Inputs = std::vector<ITensorHandle*>{&asyncInput};
workingMemDescriptor.m_Outputs = std::vector<ITensorHandle*>{&asyncOutput};
- workload1.get()->ExecuteAsync(workingMemDescriptor);
+ ExecutionData executionData;
+ executionData.m_Data = &workingMemDescriptor;
+
+ workload1.get()->ExecuteAsync(executionData);
// workload1 has no AsyncExecute implementation and so should use the default workload AsyncExecute
// implementation which will call workload1.Execute() in a thread safe manner
@@ -225,6 +232,8 @@
workingMemDescriptor1.m_Inputs = std::vector<ITensorHandle*>{&asyncInput1};
workingMemDescriptor1.m_Outputs = std::vector<ITensorHandle*>{&asyncOutput1};
+ ExecutionData executionData1;
+ executionData1.m_Data = &workingMemDescriptor1;
ScopedTensorHandle asyncInput2(constInputTensor2);
ScopedTensorHandle asyncOutput2(constOutputTensor2);
@@ -233,16 +242,19 @@
workingMemDescriptor2.m_Inputs = std::vector<ITensorHandle*>{&asyncInput2};
workingMemDescriptor2.m_Outputs = std::vector<ITensorHandle*>{&asyncOutput2};
+ ExecutionData executionData2;
+ executionData2.m_Data = &workingMemDescriptor2;
+
std::thread thread1 = std::thread([&]()
{
- workload.get()->ExecuteAsync(workingMemDescriptor1);
- workload.get()->ExecuteAsync(workingMemDescriptor1);
+ workload.get()->ExecuteAsync(executionData1);
+ workload.get()->ExecuteAsync(executionData1);
});
std::thread thread2 = std::thread([&]()
{
- workload.get()->ExecuteAsync(workingMemDescriptor2);
- workload.get()->ExecuteAsync(workingMemDescriptor2);
+ workload.get()->ExecuteAsync(executionData2);
+ workload.get()->ExecuteAsync(executionData2);
});
thread1.join();
diff --git a/src/backends/reference/RefBackend.cpp b/src/backends/reference/RefBackend.cpp
index c38d6b6..a33a775 100644
--- a/src/backends/reference/RefBackend.cpp
+++ b/src/backends/reference/RefBackend.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -103,4 +103,16 @@
return std::make_unique<DefaultAllocator>();
}
+ExecutionData RefBackend::CreateExecutionData(WorkingMemDescriptor& workingMemDescriptor) const
+{
+ ExecutionData executionData;
+ executionData.m_Data = &workingMemDescriptor;
+ return executionData;
+}
+
+void RefBackend::UpdateExecutionData(ExecutionData& executionData, WorkingMemDescriptor& workingMemDescriptor) const
+{
+ executionData.m_Data = &workingMemDescriptor;
+}
+
} // namespace armnn
diff --git a/src/backends/reference/RefBackend.hpp b/src/backends/reference/RefBackend.hpp
index da04f22..9828d09 100644
--- a/src/backends/reference/RefBackend.hpp
+++ b/src/backends/reference/RefBackend.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
@@ -62,6 +62,10 @@
};
std::unique_ptr<ICustomAllocator> GetDefaultAllocator() const override;
+
+ ExecutionData CreateExecutionData(WorkingMemDescriptor& workingMemDescriptor) const override;
+
+ void UpdateExecutionData(ExecutionData& executionData, WorkingMemDescriptor& workingMemDescriptor) const override;
};
} // namespace armnn
diff --git a/src/backends/reference/workloads/RefActivationWorkload.cpp b/src/backends/reference/workloads/RefActivationWorkload.cpp
index 7795867..bdc637a 100644
--- a/src/backends/reference/workloads/RefActivationWorkload.cpp
+++ b/src/backends/reference/workloads/RefActivationWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,9 +20,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefActivationWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefActivationWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefActivationWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefActivationWorkload.hpp b/src/backends/reference/workloads/RefActivationWorkload.hpp
index 8dc2d52..f09c928 100644
--- a/src/backends/reference/workloads/RefActivationWorkload.hpp
+++ b/src/backends/reference/workloads/RefActivationWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<ActivationQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp b/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp
index d724273..910ea73 100644
--- a/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp
+++ b/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -24,9 +24,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefArgMinMaxWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefArgMinMaxWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefArgMinMaxWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp b/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp
index 97c4b45..000513b 100644
--- a/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp
+++ b/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefBatchNormalizationWorkload.cpp b/src/backends/reference/workloads/RefBatchNormalizationWorkload.cpp
index a6bd986..ed99c63 100644
--- a/src/backends/reference/workloads/RefBatchNormalizationWorkload.cpp
+++ b/src/backends/reference/workloads/RefBatchNormalizationWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -27,9 +27,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefBatchNormalizationWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefBatchNormalizationWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefBatchNormalizationWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefBatchNormalizationWorkload.hpp b/src/backends/reference/workloads/RefBatchNormalizationWorkload.hpp
index 60dd2a9..88f0e34 100644
--- a/src/backends/reference/workloads/RefBatchNormalizationWorkload.hpp
+++ b/src/backends/reference/workloads/RefBatchNormalizationWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
explicit RefBatchNormalizationWorkload(const BatchNormalizationQueueDescriptor& descriptor,
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp
index 441d2ba..72c7a76 100644
--- a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp
+++ b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,9 +16,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefBatchToSpaceNdWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefBatchToSpaceNdWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefBatchToSpaceNdWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp
index d7ee6fc..ac6aad3 100644
--- a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp
+++ b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
using RefBaseWorkload<BatchToSpaceNdQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefCastWorkload.cpp b/src/backends/reference/workloads/RefCastWorkload.cpp
index 8f2a725..5dce5d9 100644
--- a/src/backends/reference/workloads/RefCastWorkload.cpp
+++ b/src/backends/reference/workloads/RefCastWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -31,9 +31,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefCastWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefCastWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefCastWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefCastWorkload.hpp b/src/backends/reference/workloads/RefCastWorkload.hpp
index 6f7e56a..39963c6 100644
--- a/src/backends/reference/workloads/RefCastWorkload.hpp
+++ b/src/backends/reference/workloads/RefCastWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,7 +18,7 @@
public:
using RefBaseWorkload<CastQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefChannelShuffleWorkload.cpp b/src/backends/reference/workloads/RefChannelShuffleWorkload.cpp
index 9f8514d..8d317ba 100644
--- a/src/backends/reference/workloads/RefChannelShuffleWorkload.cpp
+++ b/src/backends/reference/workloads/RefChannelShuffleWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefChannelShuffleWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefChannelShuffleWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
// Reference implementation for channel shuffle taken from
diff --git a/src/backends/reference/workloads/RefChannelShuffleWorkload.hpp b/src/backends/reference/workloads/RefChannelShuffleWorkload.hpp
index b459b87..c70361a 100644
--- a/src/backends/reference/workloads/RefChannelShuffleWorkload.hpp
+++ b/src/backends/reference/workloads/RefChannelShuffleWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<ChannelShuffleQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefComparisonWorkload.cpp b/src/backends/reference/workloads/RefComparisonWorkload.cpp
index 433e3e8..0ce83a9 100644
--- a/src/backends/reference/workloads/RefComparisonWorkload.cpp
+++ b/src/backends/reference/workloads/RefComparisonWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -47,11 +47,12 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefComparisonWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefComparisonWorkload::ExecuteAsync(ExecutionData& executionData)
{
- PostAllocationConfigure(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ PostAllocationConfigure(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefComparisonWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefComparisonWorkload.hpp b/src/backends/reference/workloads/RefComparisonWorkload.hpp
index 93cfd1f..325509e 100644
--- a/src/backends/reference/workloads/RefComparisonWorkload.hpp
+++ b/src/backends/reference/workloads/RefComparisonWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -21,7 +21,7 @@
RefComparisonWorkload(const ComparisonQueueDescriptor& descriptor, const WorkloadInfo& info);
void PostAllocationConfigure() override;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void PostAllocationConfigure(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs);
diff --git a/src/backends/reference/workloads/RefConcatWorkload.cpp b/src/backends/reference/workloads/RefConcatWorkload.cpp
index c04c053..5aa8f03 100644
--- a/src/backends/reference/workloads/RefConcatWorkload.cpp
+++ b/src/backends/reference/workloads/RefConcatWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,9 +17,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConcatWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConcatWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConcatWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefConcatWorkload.hpp b/src/backends/reference/workloads/RefConcatWorkload.hpp
index 11d6d01..5175438 100644
--- a/src/backends/reference/workloads/RefConcatWorkload.hpp
+++ b/src/backends/reference/workloads/RefConcatWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<ConcatQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConstantWorkload.cpp b/src/backends/reference/workloads/RefConstantWorkload.cpp
index 571dbb2..937e517 100644
--- a/src/backends/reference/workloads/RefConstantWorkload.cpp
+++ b/src/backends/reference/workloads/RefConstantWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -25,9 +25,10 @@
Execute(m_Data.m_Outputs);
}
-void RefConstantWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConstantWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Outputs);
}
void RefConstantWorkload::Execute(std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefConstantWorkload.hpp b/src/backends/reference/workloads/RefConstantWorkload.hpp
index 181d79d..e2f701a 100644
--- a/src/backends/reference/workloads/RefConstantWorkload.hpp
+++ b/src/backends/reference/workloads/RefConstantWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
RefConstantWorkload(const ConstantQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.cpp b/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.cpp
index 70e377d..2fe2eaf 100644
--- a/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.cpp
+++ b/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvertBf16ToFp32Workload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConvertBf16ToFp32Workload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvertBf16ToFp32Workload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.hpp b/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.hpp
index 8b5c6d5..24dcb0f 100644
--- a/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.hpp
+++ b/src/backends/reference/workloads/RefConvertBf16ToFp32Workload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using BFloat16ToFloat32Workload<ConvertBf16ToFp32QueueDescriptor>::BFloat16ToFloat32Workload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.cpp b/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.cpp
index 347132d..fa811e1 100644
--- a/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.cpp
+++ b/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvertFp16ToFp32Workload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConvertFp16ToFp32Workload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvertFp16ToFp32Workload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.hpp b/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.hpp
index feb442e..b850866 100644
--- a/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.hpp
+++ b/src/backends/reference/workloads/RefConvertFp16ToFp32Workload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using Float16ToFloat32Workload<ConvertFp16ToFp32QueueDescriptor>::Float16ToFloat32Workload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.cpp b/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.cpp
index 7fe302a..71ee95b 100644
--- a/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.cpp
+++ b/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvertFp32ToBf16Workload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConvertFp32ToBf16Workload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvertFp32ToBf16Workload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.hpp b/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.hpp
index cd3cfa4..c1e57ec 100644
--- a/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.hpp
+++ b/src/backends/reference/workloads/RefConvertFp32ToBf16Workload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using Float32ToBFloat16Workload<ConvertFp32ToBf16QueueDescriptor>::Float32ToBFloat16Workload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.cpp b/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.cpp
index be13458..4992e9c 100644
--- a/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.cpp
+++ b/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,9 +19,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvertFp32ToFp16Workload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefConvertFp32ToFp16Workload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvertFp32ToFp16Workload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.hpp b/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.hpp
index fe137ed..7950c6b 100644
--- a/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.hpp
+++ b/src/backends/reference/workloads/RefConvertFp32ToFp16Workload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using Float32ToFloat16Workload<ConvertFp32ToFp16QueueDescriptor>::Float32ToFloat16Workload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefConvolution2dWorkload.cpp b/src/backends/reference/workloads/RefConvolution2dWorkload.cpp
index 3ddbdce..355d526 100644
--- a/src/backends/reference/workloads/RefConvolution2dWorkload.cpp
+++ b/src/backends/reference/workloads/RefConvolution2dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -35,9 +35,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvolution2dWorkload::ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor)
+void RefConvolution2dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvolution2dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefConvolution2dWorkload.hpp b/src/backends/reference/workloads/RefConvolution2dWorkload.hpp
index f0d7037..61c1eb6 100644
--- a/src/backends/reference/workloads/RefConvolution2dWorkload.hpp
+++ b/src/backends/reference/workloads/RefConvolution2dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefConvolution3dWorkload.cpp b/src/backends/reference/workloads/RefConvolution3dWorkload.cpp
index f6a0ee2..3ac7cd7 100644
--- a/src/backends/reference/workloads/RefConvolution3dWorkload.cpp
+++ b/src/backends/reference/workloads/RefConvolution3dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -37,9 +37,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefConvolution3dWorkload::ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor)
+void RefConvolution3dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefConvolution3dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefConvolution3dWorkload.hpp b/src/backends/reference/workloads/RefConvolution3dWorkload.hpp
index b53f3a5..82236b9 100644
--- a/src/backends/reference/workloads/RefConvolution3dWorkload.hpp
+++ b/src/backends/reference/workloads/RefConvolution3dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefDebugWorkload.cpp b/src/backends/reference/workloads/RefDebugWorkload.cpp
index b0e19c5..48b519f 100644
--- a/src/backends/reference/workloads/RefDebugWorkload.cpp
+++ b/src/backends/reference/workloads/RefDebugWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -21,9 +21,10 @@
}
template<armnn::DataType DataType>
-void RefDebugWorkload<DataType>::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefDebugWorkload<DataType>::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs);
}
template<armnn::DataType DataType>
diff --git a/src/backends/reference/workloads/RefDebugWorkload.hpp b/src/backends/reference/workloads/RefDebugWorkload.hpp
index a157959..91bc322 100644
--- a/src/backends/reference/workloads/RefDebugWorkload.hpp
+++ b/src/backends/reference/workloads/RefDebugWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -30,7 +30,7 @@
using TypedWorkload<DebugQueueDescriptor, DataType>::TypedWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
void RegisterDebugCallback(const DebugCallbackFunction& func) override;
diff --git a/src/backends/reference/workloads/RefDepthToSpaceWorkload.cpp b/src/backends/reference/workloads/RefDepthToSpaceWorkload.cpp
index 22e35f0..cb11378 100644
--- a/src/backends/reference/workloads/RefDepthToSpaceWorkload.cpp
+++ b/src/backends/reference/workloads/RefDepthToSpaceWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,9 +16,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefDepthToSpaceWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefDepthToSpaceWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefDepthToSpaceWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefDepthToSpaceWorkload.hpp b/src/backends/reference/workloads/RefDepthToSpaceWorkload.hpp
index bd179d3..e19d07d 100644
--- a/src/backends/reference/workloads/RefDepthToSpaceWorkload.hpp
+++ b/src/backends/reference/workloads/RefDepthToSpaceWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -15,7 +15,7 @@
public:
using RefBaseWorkload<DepthToSpaceQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.cpp b/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.cpp
index fd11ad1..c0677c9 100644
--- a/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.cpp
+++ b/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -41,9 +41,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefDepthwiseConvolution2dWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefDepthwiseConvolution2dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefDepthwiseConvolution2dWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.hpp b/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.hpp
index 30ee6d8..f138000 100644
--- a/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.hpp
+++ b/src/backends/reference/workloads/RefDepthwiseConvolution2dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#include "RefBaseWorkload.hpp"
@@ -17,7 +17,7 @@
explicit RefDepthwiseConvolution2dWorkload(const DepthwiseConvolution2dQueueDescriptor &descriptor,
const WorkloadInfo &info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefDequantizeWorkload.cpp b/src/backends/reference/workloads/RefDequantizeWorkload.cpp
index f9d8007..aa5ff62 100644
--- a/src/backends/reference/workloads/RefDequantizeWorkload.cpp
+++ b/src/backends/reference/workloads/RefDequantizeWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,9 +17,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefDequantizeWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefDequantizeWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefDequantizeWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefDequantizeWorkload.hpp b/src/backends/reference/workloads/RefDequantizeWorkload.hpp
index 8fa8951..97cd996 100644
--- a/src/backends/reference/workloads/RefDequantizeWorkload.hpp
+++ b/src/backends/reference/workloads/RefDequantizeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
using RefBaseWorkload<DequantizeQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefDetectionPostProcessWorkload.cpp b/src/backends/reference/workloads/RefDetectionPostProcessWorkload.cpp
index 5f01db3..ba7933b 100644
--- a/src/backends/reference/workloads/RefDetectionPostProcessWorkload.cpp
+++ b/src/backends/reference/workloads/RefDetectionPostProcessWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefDetectionPostProcessWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefDetectionPostProcessWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefDetectionPostProcessWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefDetectionPostProcessWorkload.hpp b/src/backends/reference/workloads/RefDetectionPostProcessWorkload.hpp
index 53b2971..87faa31 100644
--- a/src/backends/reference/workloads/RefDetectionPostProcessWorkload.hpp
+++ b/src/backends/reference/workloads/RefDetectionPostProcessWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
explicit RefDetectionPostProcessWorkload(const DetectionPostProcessQueueDescriptor& descriptor,
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp
index 3ea51b9..4bd5a51 100644
--- a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp
+++ b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -35,10 +35,11 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefElementwiseUnaryWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefElementwiseUnaryWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefElementwiseUnaryWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.hpp b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.hpp
index 91229b3..471c6ed 100644
--- a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.hpp
+++ b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
RefElementwiseUnaryWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefElementwiseWorkload.cpp b/src/backends/reference/workloads/RefElementwiseWorkload.cpp
index d14ce07..344ca34 100644
--- a/src/backends/reference/workloads/RefElementwiseWorkload.cpp
+++ b/src/backends/reference/workloads/RefElementwiseWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -33,9 +33,10 @@
template <typename Functor, typename ParentDescriptor, typename armnn::StringMapping::Id DebugString>
void RefElementwiseWorkload<Functor, ParentDescriptor, DebugString>::ExecuteAsync(
- WorkingMemDescriptor &workingMemDescriptor)
+ ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
template <typename Functor, typename ParentDescriptor, typename armnn::StringMapping::Id DebugString>
diff --git a/src/backends/reference/workloads/RefElementwiseWorkload.hpp b/src/backends/reference/workloads/RefElementwiseWorkload.hpp
index 579e5de..458b524 100644
--- a/src/backends/reference/workloads/RefElementwiseWorkload.hpp
+++ b/src/backends/reference/workloads/RefElementwiseWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,7 +23,7 @@
public:
RefElementwiseWorkload(const ParentDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
using InType = typename ElementwiseBinaryFunction<Functor>::InType;
diff --git a/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.cpp b/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.cpp
index b30811b..828204f 100644
--- a/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.cpp
+++ b/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -31,9 +31,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefFakeQuantizationFloat32Workload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefFakeQuantizationFloat32Workload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefFakeQuantizationFloat32Workload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.hpp b/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.hpp
index 85dc6af..9683c87 100644
--- a/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.hpp
+++ b/src/backends/reference/workloads/RefFakeQuantizationFloat32Workload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using Float32Workload<FakeQuantizationQueueDescriptor>::Float32Workload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefFillWorkload.cpp b/src/backends/reference/workloads/RefFillWorkload.cpp
index ea1ca87..a0f0c6b 100644
--- a/src/backends/reference/workloads/RefFillWorkload.cpp
+++ b/src/backends/reference/workloads/RefFillWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,9 +19,10 @@
Execute(m_Data.m_Outputs);
}
-void RefFillWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefFillWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Outputs);
}
void RefFillWorkload::Execute(std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefFillWorkload.hpp b/src/backends/reference/workloads/RefFillWorkload.hpp
index d1e0058..5b0dcf7 100644
--- a/src/backends/reference/workloads/RefFillWorkload.hpp
+++ b/src/backends/reference/workloads/RefFillWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<FillQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefFloorWorkload.cpp b/src/backends/reference/workloads/RefFloorWorkload.cpp
index e7bd50d..d02e529 100644
--- a/src/backends/reference/workloads/RefFloorWorkload.cpp
+++ b/src/backends/reference/workloads/RefFloorWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefFloorWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefFloorWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefFloorWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefFloorWorkload.hpp b/src/backends/reference/workloads/RefFloorWorkload.hpp
index 6237ff0..5f8298d 100644
--- a/src/backends/reference/workloads/RefFloorWorkload.hpp
+++ b/src/backends/reference/workloads/RefFloorWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<FloorQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefFullyConnectedWorkload.cpp b/src/backends/reference/workloads/RefFullyConnectedWorkload.cpp
index 087fc9d..734d7f3 100644
--- a/src/backends/reference/workloads/RefFullyConnectedWorkload.cpp
+++ b/src/backends/reference/workloads/RefFullyConnectedWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -39,9 +39,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefFullyConnectedWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefFullyConnectedWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefFullyConnectedWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefFullyConnectedWorkload.hpp b/src/backends/reference/workloads/RefFullyConnectedWorkload.hpp
index 3bdfb86..7f9438c 100644
--- a/src/backends/reference/workloads/RefFullyConnectedWorkload.hpp
+++ b/src/backends/reference/workloads/RefFullyConnectedWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,7 +22,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefGatherNdWorkload.cpp b/src/backends/reference/workloads/RefGatherNdWorkload.cpp
index 4c6b559..9a9478c 100644
--- a/src/backends/reference/workloads/RefGatherNdWorkload.cpp
+++ b/src/backends/reference/workloads/RefGatherNdWorkload.cpp
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefGatherNdWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefGatherNdWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefGatherNdWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefGatherNdWorkload.hpp b/src/backends/reference/workloads/RefGatherNdWorkload.hpp
index a0d9158..0be02bd 100644
--- a/src/backends/reference/workloads/RefGatherNdWorkload.hpp
+++ b/src/backends/reference/workloads/RefGatherNdWorkload.hpp
@@ -15,7 +15,7 @@
public:
using RefBaseWorkload<GatherNdQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefGatherWorkload.cpp b/src/backends/reference/workloads/RefGatherWorkload.cpp
index 8ad36e4..55a4c09 100644
--- a/src/backends/reference/workloads/RefGatherWorkload.cpp
+++ b/src/backends/reference/workloads/RefGatherWorkload.cpp
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefGatherWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefGatherWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefGatherWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefGatherWorkload.hpp b/src/backends/reference/workloads/RefGatherWorkload.hpp
index ec880a5..ff38a1d 100644
--- a/src/backends/reference/workloads/RefGatherWorkload.hpp
+++ b/src/backends/reference/workloads/RefGatherWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -21,7 +21,7 @@
public:
using RefBaseWorkload<GatherQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefInstanceNormalizationWorkload.cpp b/src/backends/reference/workloads/RefInstanceNormalizationWorkload.cpp
index c103a6b..dd4fbf3 100644
--- a/src/backends/reference/workloads/RefInstanceNormalizationWorkload.cpp
+++ b/src/backends/reference/workloads/RefInstanceNormalizationWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefInstanceNormalizationWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefInstanceNormalizationWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefInstanceNormalizationWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefInstanceNormalizationWorkload.hpp b/src/backends/reference/workloads/RefInstanceNormalizationWorkload.hpp
index a4b2dd3..3ae03754 100644
--- a/src/backends/reference/workloads/RefInstanceNormalizationWorkload.hpp
+++ b/src/backends/reference/workloads/RefInstanceNormalizationWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
explicit RefInstanceNormalizationWorkload(const InstanceNormalizationQueueDescriptor& descriptor,
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefL2NormalizationWorkload.cpp b/src/backends/reference/workloads/RefL2NormalizationWorkload.cpp
index f6fcff3..bce8f24 100644
--- a/src/backends/reference/workloads/RefL2NormalizationWorkload.cpp
+++ b/src/backends/reference/workloads/RefL2NormalizationWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -29,9 +29,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefL2NormalizationWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefL2NormalizationWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefL2NormalizationWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefL2NormalizationWorkload.hpp b/src/backends/reference/workloads/RefL2NormalizationWorkload.hpp
index c64e2ea..4a56a04 100644
--- a/src/backends/reference/workloads/RefL2NormalizationWorkload.hpp
+++ b/src/backends/reference/workloads/RefL2NormalizationWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,7 +18,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefLogSoftmaxWorkload.cpp b/src/backends/reference/workloads/RefLogSoftmaxWorkload.cpp
index ebe1b1e..a21eb45 100644
--- a/src/backends/reference/workloads/RefLogSoftmaxWorkload.cpp
+++ b/src/backends/reference/workloads/RefLogSoftmaxWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,9 +22,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefLogSoftmaxWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefLogSoftmaxWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefLogSoftmaxWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefLogSoftmaxWorkload.hpp b/src/backends/reference/workloads/RefLogSoftmaxWorkload.hpp
index 91ad5f6..098a9ee 100644
--- a/src/backends/reference/workloads/RefLogSoftmaxWorkload.hpp
+++ b/src/backends/reference/workloads/RefLogSoftmaxWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<LogSoftmaxQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefLogicalBinaryWorkload.cpp b/src/backends/reference/workloads/RefLogicalBinaryWorkload.cpp
index f0cb846..b132061 100644
--- a/src/backends/reference/workloads/RefLogicalBinaryWorkload.cpp
+++ b/src/backends/reference/workloads/RefLogicalBinaryWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -27,9 +27,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefLogicalBinaryWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefLogicalBinaryWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefLogicalBinaryWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp b/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp
index 797d937..498f80a 100644
--- a/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp
+++ b/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
RefLogicalBinaryWorkload(const LogicalBinaryQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefLogicalUnaryWorkload.cpp b/src/backends/reference/workloads/RefLogicalUnaryWorkload.cpp
index ec0aa0e..a84af44 100644
--- a/src/backends/reference/workloads/RefLogicalUnaryWorkload.cpp
+++ b/src/backends/reference/workloads/RefLogicalUnaryWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -27,9 +27,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefLogicalUnaryWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefLogicalUnaryWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefLogicalUnaryWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefLogicalUnaryWorkload.hpp b/src/backends/reference/workloads/RefLogicalUnaryWorkload.hpp
index ebd5826..e901359 100644
--- a/src/backends/reference/workloads/RefLogicalUnaryWorkload.hpp
+++ b/src/backends/reference/workloads/RefLogicalUnaryWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,7 +20,7 @@
RefLogicalUnaryWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefLstmWorkload.cpp b/src/backends/reference/workloads/RefLstmWorkload.cpp
index 8609811..3879051 100644
--- a/src/backends/reference/workloads/RefLstmWorkload.cpp
+++ b/src/backends/reference/workloads/RefLstmWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -44,9 +44,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefLstmWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefLstmWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefLstmWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefLstmWorkload.hpp b/src/backends/reference/workloads/RefLstmWorkload.hpp
index 57526c9..ad94e26 100644
--- a/src/backends/reference/workloads/RefLstmWorkload.hpp
+++ b/src/backends/reference/workloads/RefLstmWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,7 +19,7 @@
explicit RefLstmWorkload(const LstmQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefMeanWorkload.cpp b/src/backends/reference/workloads/RefMeanWorkload.cpp
index 23abaf8..5d73a43 100644
--- a/src/backends/reference/workloads/RefMeanWorkload.cpp
+++ b/src/backends/reference/workloads/RefMeanWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefMeanWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefMeanWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefMeanWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefMeanWorkload.hpp b/src/backends/reference/workloads/RefMeanWorkload.hpp
index c4c6a12..6c09f4b 100644
--- a/src/backends/reference/workloads/RefMeanWorkload.hpp
+++ b/src/backends/reference/workloads/RefMeanWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,7 +19,7 @@
public:
explicit RefMeanWorkload (const MeanQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefNormalizationWorkload.cpp b/src/backends/reference/workloads/RefNormalizationWorkload.cpp
index 613868d..40c9a6f 100644
--- a/src/backends/reference/workloads/RefNormalizationWorkload.cpp
+++ b/src/backends/reference/workloads/RefNormalizationWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -166,9 +166,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefNormalizationWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefNormalizationWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefNormalizationWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefNormalizationWorkload.hpp b/src/backends/reference/workloads/RefNormalizationWorkload.hpp
index 5218e1e..f06563c 100644
--- a/src/backends/reference/workloads/RefNormalizationWorkload.hpp
+++ b/src/backends/reference/workloads/RefNormalizationWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,7 +18,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefPadWorkload.cpp b/src/backends/reference/workloads/RefPadWorkload.cpp
index fd0728c..9bc4efa 100644
--- a/src/backends/reference/workloads/RefPadWorkload.cpp
+++ b/src/backends/reference/workloads/RefPadWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefPadWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefPadWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefPadWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefPadWorkload.hpp b/src/backends/reference/workloads/RefPadWorkload.hpp
index c587105..539ac4a 100644
--- a/src/backends/reference/workloads/RefPadWorkload.hpp
+++ b/src/backends/reference/workloads/RefPadWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<PadQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefPermuteWorkload.cpp b/src/backends/reference/workloads/RefPermuteWorkload.cpp
index f6af208..e0e3b4f 100644
--- a/src/backends/reference/workloads/RefPermuteWorkload.cpp
+++ b/src/backends/reference/workloads/RefPermuteWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,9 +20,10 @@
}
template <armnn::DataType DataType>
-void RefPermuteWorkload<DataType>::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefPermuteWorkload<DataType>::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
template <armnn::DataType DataType>
diff --git a/src/backends/reference/workloads/RefPermuteWorkload.hpp b/src/backends/reference/workloads/RefPermuteWorkload.hpp
index d1e4452..c6b8e3b 100644
--- a/src/backends/reference/workloads/RefPermuteWorkload.hpp
+++ b/src/backends/reference/workloads/RefPermuteWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -25,7 +25,7 @@
using TypedWorkload<PermuteQueueDescriptor, DataType>::m_Data;
using TypedWorkload<PermuteQueueDescriptor, DataType>::TypedWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefPooling2dWorkload.cpp b/src/backends/reference/workloads/RefPooling2dWorkload.cpp
index d337278..9dc9a35 100644
--- a/src/backends/reference/workloads/RefPooling2dWorkload.cpp
+++ b/src/backends/reference/workloads/RefPooling2dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefPooling2dWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefPooling2dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefPooling2dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefPooling2dWorkload.hpp b/src/backends/reference/workloads/RefPooling2dWorkload.hpp
index a073e39..8da8e87 100644
--- a/src/backends/reference/workloads/RefPooling2dWorkload.hpp
+++ b/src/backends/reference/workloads/RefPooling2dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,7 +19,7 @@
using RefBaseWorkload<Pooling2dQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefPooling3dWorkload.cpp b/src/backends/reference/workloads/RefPooling3dWorkload.cpp
index d1e00aa..5f1eda2 100644
--- a/src/backends/reference/workloads/RefPooling3dWorkload.cpp
+++ b/src/backends/reference/workloads/RefPooling3dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefPooling3dWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefPooling3dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefPooling3dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefPooling3dWorkload.hpp b/src/backends/reference/workloads/RefPooling3dWorkload.hpp
index 92bc476..6aa32ae 100644
--- a/src/backends/reference/workloads/RefPooling3dWorkload.hpp
+++ b/src/backends/reference/workloads/RefPooling3dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,7 +19,7 @@
using RefBaseWorkload<Pooling3dQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefPreluWorkload.cpp b/src/backends/reference/workloads/RefPreluWorkload.cpp
index 94eeea1..efe7a4c 100644
--- a/src/backends/reference/workloads/RefPreluWorkload.cpp
+++ b/src/backends/reference/workloads/RefPreluWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefPreluWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefPreluWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefPreluWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefPreluWorkload.hpp b/src/backends/reference/workloads/RefPreluWorkload.hpp
index 51ba2c1..b309dcf 100644
--- a/src/backends/reference/workloads/RefPreluWorkload.hpp
+++ b/src/backends/reference/workloads/RefPreluWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
explicit RefPreluWorkload(const PreluQueueDescriptor& descriptor,
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefQLstmWorkload.cpp b/src/backends/reference/workloads/RefQLstmWorkload.cpp
index 74f5f1e..398faa9 100644
--- a/src/backends/reference/workloads/RefQLstmWorkload.cpp
+++ b/src/backends/reference/workloads/RefQLstmWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -48,9 +48,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefQLstmWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefQLstmWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefQLstmWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefQLstmWorkload.hpp b/src/backends/reference/workloads/RefQLstmWorkload.hpp
index 0e64a38..2c56d9c3 100644
--- a/src/backends/reference/workloads/RefQLstmWorkload.hpp
+++ b/src/backends/reference/workloads/RefQLstmWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -19,7 +19,7 @@
explicit RefQLstmWorkload(const QLstmQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefQuantizeWorkload.cpp b/src/backends/reference/workloads/RefQuantizeWorkload.cpp
index 10ef0e5..e54ab45 100644
--- a/src/backends/reference/workloads/RefQuantizeWorkload.cpp
+++ b/src/backends/reference/workloads/RefQuantizeWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -39,9 +39,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefQuantizeWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefQuantizeWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefQuantizeWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefQuantizeWorkload.hpp b/src/backends/reference/workloads/RefQuantizeWorkload.hpp
index e382410..1aba32c 100644
--- a/src/backends/reference/workloads/RefQuantizeWorkload.hpp
+++ b/src/backends/reference/workloads/RefQuantizeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
public:
RefQuantizeWorkload(const QuantizeQueueDescriptor& descriptor, const WorkloadInfo &info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefRankWorkload.hpp b/src/backends/reference/workloads/RefRankWorkload.hpp
index 000828f..4810952 100644
--- a/src/backends/reference/workloads/RefRankWorkload.hpp
+++ b/src/backends/reference/workloads/RefRankWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,9 +22,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override
+ void ExecuteAsync(ExecutionData& executionData) override
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
private:
diff --git a/src/backends/reference/workloads/RefReduceWorkload.cpp b/src/backends/reference/workloads/RefReduceWorkload.cpp
index 62881da..e7d05ca 100644
--- a/src/backends/reference/workloads/RefReduceWorkload.cpp
+++ b/src/backends/reference/workloads/RefReduceWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Samsung Electronics Co Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefReduceWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefReduceWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefReduceWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefReduceWorkload.hpp b/src/backends/reference/workloads/RefReduceWorkload.hpp
index d759bc2..2611932 100644
--- a/src/backends/reference/workloads/RefReduceWorkload.hpp
+++ b/src/backends/reference/workloads/RefReduceWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Samsung Electronics Co Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,7 +18,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefReshapeWorkload.cpp b/src/backends/reference/workloads/RefReshapeWorkload.cpp
index 960d591..a93645e 100644
--- a/src/backends/reference/workloads/RefReshapeWorkload.cpp
+++ b/src/backends/reference/workloads/RefReshapeWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,9 +17,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefReshapeWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefReshapeWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefReshapeWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefReshapeWorkload.hpp b/src/backends/reference/workloads/RefReshapeWorkload.hpp
index 7596685..94fb3a1 100644
--- a/src/backends/reference/workloads/RefReshapeWorkload.hpp
+++ b/src/backends/reference/workloads/RefReshapeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<ReshapeQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefResizeWorkload.cpp b/src/backends/reference/workloads/RefResizeWorkload.cpp
index d7a82b8..39a2a29 100644
--- a/src/backends/reference/workloads/RefResizeWorkload.cpp
+++ b/src/backends/reference/workloads/RefResizeWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,9 +22,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefResizeWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefResizeWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefResizeWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefResizeWorkload.hpp b/src/backends/reference/workloads/RefResizeWorkload.hpp
index f774719..27ae48c 100644
--- a/src/backends/reference/workloads/RefResizeWorkload.hpp
+++ b/src/backends/reference/workloads/RefResizeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<ResizeQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefShapeWorkload.hpp b/src/backends/reference/workloads/RefShapeWorkload.hpp
index b7ed761..bc4d50a 100644
--- a/src/backends/reference/workloads/RefShapeWorkload.hpp
+++ b/src/backends/reference/workloads/RefShapeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -21,9 +21,10 @@
{
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override
+ void ExecuteAsync(ExecutionData& executionData) override
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
private:
diff --git a/src/backends/reference/workloads/RefSliceWorkload.cpp b/src/backends/reference/workloads/RefSliceWorkload.cpp
index f94a83e..60c3950 100644
--- a/src/backends/reference/workloads/RefSliceWorkload.cpp
+++ b/src/backends/reference/workloads/RefSliceWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,9 +18,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefSliceWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefSliceWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefSliceWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefSliceWorkload.hpp b/src/backends/reference/workloads/RefSliceWorkload.hpp
index b9dca86..8b99bc4 100644
--- a/src/backends/reference/workloads/RefSliceWorkload.hpp
+++ b/src/backends/reference/workloads/RefSliceWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2019 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
using RefBaseWorkload<SliceQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefSoftmaxWorkload.cpp b/src/backends/reference/workloads/RefSoftmaxWorkload.cpp
index 9733cbc..f2579ce 100644
--- a/src/backends/reference/workloads/RefSoftmaxWorkload.cpp
+++ b/src/backends/reference/workloads/RefSoftmaxWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,9 +22,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefSoftmaxWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefSoftmaxWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefSoftmaxWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefSoftmaxWorkload.hpp b/src/backends/reference/workloads/RefSoftmaxWorkload.hpp
index cac102a..89d2c9e 100644
--- a/src/backends/reference/workloads/RefSoftmaxWorkload.hpp
+++ b/src/backends/reference/workloads/RefSoftmaxWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<SoftmaxQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp
index e35632d..6aa422a 100644
--- a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp
+++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,9 +17,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefSpaceToBatchNdWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefSpaceToBatchNdWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefSpaceToBatchNdWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp
index eb2d93f..f2c8768 100644
--- a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp
+++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<SpaceToBatchNdQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefSpaceToDepthWorkload.cpp b/src/backends/reference/workloads/RefSpaceToDepthWorkload.cpp
index 88faf7a..e8dd052 100644
--- a/src/backends/reference/workloads/RefSpaceToDepthWorkload.cpp
+++ b/src/backends/reference/workloads/RefSpaceToDepthWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,9 +17,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefSpaceToDepthWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefSpaceToDepthWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefSpaceToDepthWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefSpaceToDepthWorkload.hpp b/src/backends/reference/workloads/RefSpaceToDepthWorkload.hpp
index 17f8d2f..79e888d 100644
--- a/src/backends/reference/workloads/RefSpaceToDepthWorkload.hpp
+++ b/src/backends/reference/workloads/RefSpaceToDepthWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
@@ -16,7 +16,7 @@
public:
using RefBaseWorkload<SpaceToDepthQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefSplitterWorkload.cpp b/src/backends/reference/workloads/RefSplitterWorkload.cpp
index 076aefe..93b393b 100644
--- a/src/backends/reference/workloads/RefSplitterWorkload.cpp
+++ b/src/backends/reference/workloads/RefSplitterWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -16,9 +16,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefSplitterWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefSplitterWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefSplitterWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefSplitterWorkload.hpp b/src/backends/reference/workloads/RefSplitterWorkload.hpp
index 0b72bb9..0beaaf9 100644
--- a/src/backends/reference/workloads/RefSplitterWorkload.hpp
+++ b/src/backends/reference/workloads/RefSplitterWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -18,7 +18,7 @@
public:
using RefBaseWorkload<SplitterQueueDescriptor>::RefBaseWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefStackWorkload.cpp b/src/backends/reference/workloads/RefStackWorkload.cpp
index f57e6e0..e35c2d5 100644
--- a/src/backends/reference/workloads/RefStackWorkload.cpp
+++ b/src/backends/reference/workloads/RefStackWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,9 +23,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefStackWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefStackWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefStackWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefStackWorkload.hpp b/src/backends/reference/workloads/RefStackWorkload.hpp
index 19f4a7b..d413c7d 100644
--- a/src/backends/reference/workloads/RefStackWorkload.hpp
+++ b/src/backends/reference/workloads/RefStackWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,7 +17,7 @@
explicit RefStackWorkload(const StackQueueDescriptor& descriptor,
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefStridedSliceWorkload.cpp b/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
index 41fe4c3..f5ca0c1 100644
--- a/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
+++ b/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,9 +20,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefStridedSliceWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefStridedSliceWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefStridedSliceWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
diff --git a/src/backends/reference/workloads/RefStridedSliceWorkload.hpp b/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
index ea443cf..f8a8f8d 100644
--- a/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
+++ b/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -15,7 +15,7 @@
public:
RefStridedSliceWorkload(const StridedSliceQueueDescriptor& descriptor, const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.cpp b/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.cpp
index 64a2d4c..1269b3f 100644
--- a/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.cpp
+++ b/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -38,9 +38,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefTransposeConvolution2dWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefTransposeConvolution2dWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefTransposeConvolution2dWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.hpp b/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.hpp
index 6bcee9a..1d66698 100644
--- a/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.hpp
+++ b/src/backends/reference/workloads/RefTransposeConvolution2dWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -22,7 +22,7 @@
~RefTransposeConvolution2dWorkload() = default;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
diff --git a/src/backends/reference/workloads/RefTransposeWorkload.cpp b/src/backends/reference/workloads/RefTransposeWorkload.cpp
index 828badd..6c94e7d 100644
--- a/src/backends/reference/workloads/RefTransposeWorkload.cpp
+++ b/src/backends/reference/workloads/RefTransposeWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -20,9 +20,10 @@
}
template <armnn::DataType DataType>
-void RefTransposeWorkload<DataType>::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
+void RefTransposeWorkload<DataType>::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
template <armnn::DataType DataType>
diff --git a/src/backends/reference/workloads/RefTransposeWorkload.hpp b/src/backends/reference/workloads/RefTransposeWorkload.hpp
index b8c3649..db4f683 100644
--- a/src/backends/reference/workloads/RefTransposeWorkload.hpp
+++ b/src/backends/reference/workloads/RefTransposeWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2020 Arm Ltd. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -25,7 +25,7 @@
using TypedWorkload<TransposeQueueDescriptor, DataType>::m_Data;
using TypedWorkload<TransposeQueueDescriptor, DataType>::TypedWorkload;
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private:
void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
};
diff --git a/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.cpp b/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.cpp
index c4345d4..23022d0 100644
--- a/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.cpp
+++ b/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -48,9 +48,10 @@
Execute(m_Data.m_Inputs, m_Data.m_Outputs);
}
-void RefUnidirectionalSequenceLstmWorkload::ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor)
+void RefUnidirectionalSequenceLstmWorkload::ExecuteAsync(ExecutionData& executionData)
{
- Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
+ WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+ Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
}
void RefUnidirectionalSequenceLstmWorkload::Execute(std::vector<ITensorHandle*> inputs,
diff --git a/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.hpp b/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.hpp
index 7a91cee..ad2b862 100644
--- a/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.hpp
+++ b/src/backends/reference/workloads/RefUnidirectionalSequenceLstmWorkload.hpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -23,7 +23,7 @@
const WorkloadInfo& info);
void Execute() const override;
- void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor) override;
+ void ExecuteAsync(ExecutionData& executionData) override;
private: