IVGCVSW-7785 3D tensors in BATCH_TO_SPACE and SPACE_TO_BATCH in CpuAcc & GpuAcc
* Add Reshape layers before and after to extend support for 3D tensors, as ACL only supports 4D tensors for those layers
* Add Unit Tests
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I4431185ce3a3b2f595d2a79bdda7095212d1c52d
diff --git a/src/backends/aclCommon/ArmComputeTensorUtils.hpp b/src/backends/aclCommon/ArmComputeTensorUtils.hpp
index fab643e..f5ae770 100644
--- a/src/backends/aclCommon/ArmComputeTensorUtils.hpp
+++ b/src/backends/aclCommon/ArmComputeTensorUtils.hpp
@@ -123,10 +123,22 @@
/// Utility function used to setup an arm_compute::CropInfo object from an ArmNN layer descriptor.
template <typename Descriptor>
-arm_compute::CropInfo BuildArmComputeCropInfo(const Descriptor& descriptor)
+arm_compute::CropInfo BuildArmComputeCropInfo(const Descriptor& descriptor, const unsigned int rank = 4)
{
- return arm_compute::CropInfo(descriptor.m_Crops[1].first, descriptor.m_Crops[1].second,
- descriptor.m_Crops[0].first, descriptor.m_Crops[0].second);
+ if (rank == 3)
+ {
+ return arm_compute::CropInfo(0, 0,
+ descriptor.m_Crops[0].first, descriptor.m_Crops[0].second);
+ }
+ else if (rank == 4)
+ {
+ return arm_compute::CropInfo(descriptor.m_Crops[1].first, descriptor.m_Crops[1].second,
+ descriptor.m_Crops[0].first, descriptor.m_Crops[0].second);
+ }
+ else
+ {
+ throw InvalidArgumentException("Tensor rank must be either 3 or 4", CHECK_LOCATION());
+ }
}
/// Sets up the given ArmCompute tensor's dimensions based on the given ArmNN tensor.
diff --git a/src/backends/cl/test/ClLayerTests.cpp b/src/backends/cl/test/ClLayerTests.cpp
index 03a4d6f..93ad653 100644
--- a/src/backends/cl/test/ClLayerTests.cpp
+++ b/src/backends/cl/test/ClLayerTests.cpp
@@ -145,6 +145,9 @@
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat327,
ClContextControlFixture,
BatchToSpaceNdNhwcTest7<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat32_3D,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest8<DataType::Float32>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat321,
ClContextControlFixture,
@@ -189,6 +192,9 @@
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt7,
ClContextControlFixture,
BatchToSpaceNdNhwcTest7<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt_3D,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest8<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt1,
ClContextControlFixture,
@@ -233,6 +239,9 @@
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint7,
ClContextControlFixture,
BatchToSpaceNdNhwcTest7<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint_3D,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest8<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint1,
ClContextControlFixture,
diff --git a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
index ad3a602..f6d9604 100644
--- a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
+++ b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
@@ -1,43 +1,88 @@
//
-// Copyright © 2017, 2023 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2017, 2019-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#include "ClBatchToSpaceNdWorkload.hpp"
+#include <armnn/utility/PolymorphicDowncast.hpp>
+
#include <cl/ClTensorHandle.hpp>
-#include <armnn/backends/TensorHandle.hpp>
-#include <aclCommon/ArmComputeTensorUtils.hpp>
-
-#include <armnn/utility/NumericCast.hpp>
-
-#include "ClWorkloadUtils.hpp"
namespace armnn
{
+
using namespace armcomputetensorutils;
arm_compute::Status ClBatchToSpaceNdWorkloadValidate(const TensorInfo& input,
const TensorInfo& output,
const BatchToSpaceNdDescriptor& descriptor)
{
- DataLayout dataLayout = descriptor.m_DataLayout;
- const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, dataLayout);
+ arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
- // ArmNN blockShape is [H, W] Cl asks for W, H
+ arm_compute::Status statusBatchToSpace = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeInput = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeOutput = arm_compute::Status(arm_compute::ErrorCode::OK);
+
+ arm_compute::TensorInfo aclReshapeInputInfo = aclInputInfo;
+ arm_compute::TensorInfo aclReshapeOutputInfo = aclOutputInfo;
+
+ // When a spacial dimension is missing (rank=3) set W to 1
+ const unsigned int rank = input.GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = aclInputInfo.tensor_shape();
+ const arm_compute::TensorShape outputShape = aclOutputInfo.tensor_shape();
+
+ if (descriptor.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (descriptor.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ statusReshapeInput = arm_compute::CLReshapeLayer::validate(&aclInputInfo, &aclReshapeInputInfo);
+ statusReshapeOutput = arm_compute::CLReshapeLayer::validate(&aclReshapeOutputInfo, &aclOutputInfo);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
- const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, dataLayout);
+ const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor, rank);
- const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor);
+ statusBatchToSpace = arm_compute::CLBatchToSpaceLayer::validate(rank == 3 ? &aclReshapeInputInfo : &aclInputInfo,
+ blockWidth,
+ blockHeight,
+ rank == 3 ? &aclReshapeOutputInfo : &aclOutputInfo,
+ cropInfo);
- const arm_compute::Status aclStatus = arm_compute::CLBatchToSpaceLayer::validate(&aclInputInfo,
- blockWidth,
- blockHeight,
- &aclOutputInfo,
- cropInfo);
- return aclStatus;
+ if (statusReshapeInput.error_code() == arm_compute::ErrorCode::OK &&
+ statusReshapeOutput.error_code() == arm_compute::ErrorCode::OK &&
+ statusBatchToSpace.error_code() == arm_compute::ErrorCode::OK)
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::OK,
+ "All BatchToSpace layers validate status OK.");
+ }
+ else
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::RUNTIME_ERROR,
+ "BatchToSpace layer validate status failed."
+ + statusBatchToSpace.error_description()
+ + statusReshapeInput.error_description()
+ + statusReshapeOutput.error_description());
+ }
}
ClBatchToSpaceNdWorkload::ClBatchToSpaceNdWorkload(const BatchToSpaceNdQueueDescriptor& descriptor,
@@ -53,30 +98,84 @@
m_Data.ValidateInputsOutputs("ClBatchToSpaceNdWorkload", 1, 1);
- arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
-
arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
- input.info()->set_data_layout(aclDataLayout);
-
- // ArmNN blockShape is [H, W] Cl asks for W, H
- int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
-
arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+ arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
+ input.info()->set_data_layout(aclDataLayout);
output.info()->set_data_layout(aclDataLayout);
+ arm_compute::TensorInfo aclReshapeInputInfo = BuildArmComputeTensorInfo(info.m_InputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+ arm_compute::TensorInfo aclReshapeOutputInfo = BuildArmComputeTensorInfo(info.m_OutputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+
+ const unsigned int rank = info.m_InputTensorInfos[0].GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = input.info()->tensor_shape();
+ const arm_compute::TensorShape outputShape = output.info()->tensor_shape();
+
+ // When a spacial dimension is missing set W to 1
+ if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ m_ReshapeInputTensor.allocator()->init(aclReshapeInputInfo);
+ m_ReshapeOutputTensor.allocator()->init(aclReshapeOutputInfo);
+
+ InitialiseArmComputeTensorEmpty(m_ReshapeInputTensor);
+ InitialiseArmComputeTensorEmpty(m_ReshapeOutputTensor);
+
+ m_LayerReshapeInput.reset(new arm_compute::CLReshapeLayer());
+ m_LayerReshapeOutput.reset(new arm_compute::CLReshapeLayer());
+
+ m_LayerReshapeInput->configure(clCompileContext, &input, &m_ReshapeInputTensor);
+ m_LayerReshapeOutput->configure(clCompileContext, &m_ReshapeOutputTensor, &output);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
+ int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[0]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
+
const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor.m_Parameters);
{
ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "ClBatchToSpaceNdWorkload_configure");
- m_Layer.configure(clCompileContext, &input, blockWidth, blockHeight, &output, cropInfo);
+ m_Layer.configure(clCompileContext,
+ (rank == 3) ? &m_ReshapeInputTensor : &input,
+ blockWidth,
+ blockHeight,
+ (rank == 3) ? &m_ReshapeOutputTensor : &output,
+ cropInfo);
}
}
void ClBatchToSpaceNdWorkload::Execute() const
{
ARMNN_SCOPED_PROFILING_EVENT_CL_GUID("ClBatchToSpaceNdWorkload_Execute", this->GetGuid());
+ if (m_LayerReshapeInput)
+ {
+ m_LayerReshapeInput->run();
+ }
RunClFunction(m_Layer, CHECK_LOCATION());
+ if (m_LayerReshapeOutput)
+ {
+ m_LayerReshapeOutput->run();
+ }
}
} //namespace armnn
diff --git a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.hpp b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.hpp
index 5026dc3..b23c416 100644
--- a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.hpp
+++ b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.hpp
@@ -1,12 +1,15 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2017-2018,2020-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
#include "ClBaseWorkload.hpp"
+#include "ClWorkloadUtils.hpp"
+
#include <arm_compute/runtime/CL/functions/CLBatchToSpaceLayer.h>
+#include <arm_compute/runtime/CL/functions/CLReshapeLayer.h>
namespace armnn
{
@@ -22,11 +25,14 @@
const WorkloadInfo& info,
const arm_compute::CLCompileContext& clCompileContext);
- void Execute() const override;
+ virtual void Execute() const override;
private:
-
mutable arm_compute::CLBatchToSpaceLayer m_Layer;
+ mutable std::unique_ptr<arm_compute::CLReshapeLayer> m_LayerReshapeInput;
+ mutable std::unique_ptr<arm_compute::CLReshapeLayer> m_LayerReshapeOutput;
+ arm_compute::CLTensor m_ReshapeInputTensor;
+ arm_compute::CLTensor m_ReshapeOutputTensor;
};
} //namespace armnn
diff --git a/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.cpp b/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.cpp
index 220d2d1..fd90adb 100644
--- a/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.cpp
+++ b/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.cpp
@@ -1,20 +1,13 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2017-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#include "ClSpaceToBatchNdWorkload.hpp"
-#include "ClWorkloadUtils.hpp"
-
-#include <aclCommon/ArmComputeUtils.hpp>
-#include <aclCommon/ArmComputeTensorUtils.hpp>
-#include <armnn/utility/NumericCast.hpp>
#include <armnn/utility/PolymorphicDowncast.hpp>
-#include <armnn/backends/TensorHandle.hpp>
-#include <cl/ClLayerSupport.hpp>
+
#include <cl/ClTensorHandle.hpp>
-#include <cl/ClLayerSupport.hpp>
namespace armnn
{
@@ -24,30 +17,82 @@
const TensorInfo& output,
const SpaceToBatchNdDescriptor& descriptor)
{
- const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
- const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
- // ArmNN blockShape is [H, W] Cl asks for W, H
+ arm_compute::Status statusSpaceToBatch = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeInput = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeOutput = arm_compute::Status(arm_compute::ErrorCode::OK);
+
+ arm_compute::TensorInfo aclReshapeInputInfo = aclInputInfo;
+ arm_compute::TensorInfo aclReshapeOutputInfo = aclOutputInfo;
+
+ // When a spacial dimension is missing (rank=3) set W to 1
+ const unsigned int rank = input.GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = aclInputInfo.tensor_shape();
+ const arm_compute::TensorShape outputShape = aclOutputInfo.tensor_shape();
+
+ if (descriptor.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (descriptor.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ statusReshapeInput = arm_compute::CLReshapeLayer::validate(&aclInputInfo, &aclReshapeInputInfo);
+ statusReshapeOutput = arm_compute::CLReshapeLayer::validate(&aclReshapeOutputInfo, &aclOutputInfo);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
- arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(
- descriptor.m_PadList[1].first, descriptor.m_PadList[0].first);
- arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(
- descriptor.m_PadList[1].second, descriptor.m_PadList[0].second);
+ unsigned int padLeft = (rank == 3) ? 0 : descriptor.m_PadList[1].first;
+ unsigned int padRight = (rank == 3) ? 0 : descriptor.m_PadList[1].second;
+ arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(padLeft,
+ descriptor.m_PadList[0].first);
+ arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(padRight,
+ descriptor.m_PadList[0].second);
- return arm_compute::CLSpaceToBatchLayer::validate(&aclInputInfo,
- blockWidth,
- blockHeight,
- paddingLeftTop,
- paddingRightBottom,
- &aclOutputInfo);
+ const arm_compute::Status aclStatus = arm_compute::CLSpaceToBatchLayer::validate(&aclInputInfo,
+ blockWidth,
+ blockHeight,
+ paddingLeftTop,
+ paddingRightBottom,
+ &aclOutputInfo);
+
+ if (statusReshapeInput.error_code() == arm_compute::ErrorCode::OK &&
+ statusReshapeOutput.error_code() == arm_compute::ErrorCode::OK &&
+ statusSpaceToBatch.error_code() == arm_compute::ErrorCode::OK)
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::OK,
+ "All SpaceToBatch layers validate status OK.");
+ }
+ else
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::RUNTIME_ERROR,
+ "SpaceToBatch layer validate status failed."
+ + statusSpaceToBatch.error_description()
+ + statusReshapeInput.error_description()
+ + statusReshapeOutput.error_description());
+ }
}
-ClSpaceToBatchNdWorkload::ClSpaceToBatchNdWorkload(
- const SpaceToBatchNdQueueDescriptor& descriptor,
- const WorkloadInfo& info,
- const arm_compute::CLCompileContext& clCompileContext)
+ClSpaceToBatchNdWorkload::ClSpaceToBatchNdWorkload(const SpaceToBatchNdQueueDescriptor& descriptor,
+ const WorkloadInfo& info,
+ const arm_compute::CLCompileContext& clCompileContext)
: ClBaseWorkload<SpaceToBatchNdQueueDescriptor>(descriptor, info)
{
// Report Profiling Details
@@ -58,40 +103,90 @@
m_Data.ValidateInputsOutputs("ClSpaceToBatchNdWorkload", 1, 1);
- arm_compute::ICLTensor& input =
- armnn::PolymorphicPointerDowncast<IClTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
- arm_compute::ICLTensor& output =
- armnn::PolymorphicPointerDowncast<IClTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
-
- // ArmNN blockShape is [H, W] Cl asks for W, H
- int32_t blockHeight = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[1]);
-
- arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(
- m_Data.m_Parameters.m_PadList[1].first, m_Data.m_Parameters.m_PadList[0].first);
- arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(
- m_Data.m_Parameters.m_PadList[1].second, m_Data.m_Parameters.m_PadList[0].second);
+ arm_compute::ICLTensor& input = PolymorphicPointerDowncast<IClTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ICLTensor& output = PolymorphicPointerDowncast<IClTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
input.info()->set_data_layout(aclDataLayout);
output.info()->set_data_layout(aclDataLayout);
+ arm_compute::TensorInfo aclReshapeInputInfo = BuildArmComputeTensorInfo(info.m_InputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+ arm_compute::TensorInfo aclReshapeOutputInfo = BuildArmComputeTensorInfo(info.m_OutputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+
+ const unsigned int rank = info.m_InputTensorInfos[0].GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = input.info()->tensor_shape();
+ const arm_compute::TensorShape outputShape = output.info()->tensor_shape();
+
+ // When a spacial dimension is missing set W to 1
+ if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ m_ReshapeInputTensor.allocator()->init(aclReshapeInputInfo);
+ m_ReshapeOutputTensor.allocator()->init(aclReshapeOutputInfo);
+
+ InitialiseArmComputeTensorEmpty(m_ReshapeInputTensor);
+ InitialiseArmComputeTensorEmpty(m_ReshapeOutputTensor);
+
+ m_LayerReshapeInput.reset(new arm_compute::CLReshapeLayer());
+ m_LayerReshapeOutput.reset(new arm_compute::CLReshapeLayer());
+
+ m_LayerReshapeInput->configure(clCompileContext, &input, &m_ReshapeInputTensor);
+ m_LayerReshapeOutput->configure(clCompileContext, &m_ReshapeOutputTensor, &output);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
+ int32_t blockHeight = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]);
+ int32_t blockWidth = (rank == 3) ? 1: armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
+
+ unsigned int padLeft = (rank == 3) ? 0 : descriptor.m_Parameters.m_PadList[1].first;
+ unsigned int padRight = (rank == 3) ? 0 : descriptor.m_Parameters.m_PadList[1].second;
+ arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(padLeft,
+ descriptor.m_Parameters.m_PadList[0].first);
+ arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(padRight,
+ descriptor.m_Parameters.m_PadList[0].second);
+
{
ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "ClSpaceToBatchNdWorkload_configure");
- m_SpaceToBatchLayer.configure(clCompileContext,
- &input,
- blockWidth,
- blockHeight,
- paddingLeftTop,
- paddingRightBottom,
- &output);
+ m_Layer.configure(clCompileContext,
+ rank == 3 ? &m_ReshapeInputTensor : &input,
+ blockWidth,
+ blockHeight,
+ paddingLeftTop,
+ paddingRightBottom,
+ rank == 3 ? &m_ReshapeOutputTensor : &output);
}
}
void ClSpaceToBatchNdWorkload::Execute() const
{
ARMNN_SCOPED_PROFILING_EVENT_CL_GUID("ClSpaceToBatchNdWorkload_Execute", this->GetGuid());
- RunClFunction(m_SpaceToBatchLayer, CHECK_LOCATION());
+ if (m_LayerReshapeInput)
+ {
+ m_LayerReshapeInput->run();
+ }
+ RunClFunction(m_Layer, CHECK_LOCATION());
+ if (m_LayerReshapeOutput)
+ {
+ m_LayerReshapeOutput->run();
+ }
}
} //namespace armnn
diff --git a/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.hpp b/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.hpp
index 948d13b..a577c06 100644
--- a/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.hpp
+++ b/src/backends/cl/workloads/ClSpaceToBatchNdWorkload.hpp
@@ -1,16 +1,15 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2017, 2020-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
-#include <armnn/Tensor.hpp>
-#include <armnn/Descriptors.hpp>
-
#include "ClBaseWorkload.hpp"
+#include "ClWorkloadUtils.hpp"
#include <arm_compute/runtime/CL/functions/CLSpaceToBatchLayer.h>
+#include <arm_compute/runtime/CL/functions/CLReshapeLayer.h>
namespace armnn
{
@@ -25,10 +24,14 @@
ClSpaceToBatchNdWorkload(const SpaceToBatchNdQueueDescriptor& descriptor,
const WorkloadInfo& info,
const arm_compute::CLCompileContext& clCompileContext);
- void Execute() const override;
+ virtual void Execute() const override;
private:
- mutable arm_compute::CLSpaceToBatchLayer m_SpaceToBatchLayer;
+ mutable arm_compute::CLSpaceToBatchLayer m_Layer;
+ mutable std::unique_ptr<arm_compute::CLReshapeLayer> m_LayerReshapeInput;
+ mutable std::unique_ptr<arm_compute::CLReshapeLayer> m_LayerReshapeOutput;
+ arm_compute::CLTensor m_ReshapeInputTensor;
+ arm_compute::CLTensor m_ReshapeOutputTensor;
};
} //namespace armnn
diff --git a/src/backends/neon/test/NeonLayerTests.cpp b/src/backends/neon/test/NeonLayerTests.cpp
index c0b995b..c5b710a 100644
--- a/src/backends/neon/test/NeonLayerTests.cpp
+++ b/src/backends/neon/test/NeonLayerTests.cpp
@@ -33,6 +33,7 @@
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat325, BatchToSpaceNdNhwcTest5<DataType::Float32>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat326, BatchToSpaceNdNhwcTest6<DataType::Float32>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat327, BatchToSpaceNdNhwcTest7<DataType::Float32>)
+ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_3D, BatchToSpaceNdNhwcTest8<DataType::Float32>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwFloat321, BatchToSpaceNdNchwTest1<DataType::Float32>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwFloat322, BatchToSpaceNdNchwTest2<DataType::Float32>)
@@ -49,6 +50,7 @@
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt5, BatchToSpaceNdNhwcTest5<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt6, BatchToSpaceNdNhwcTest6<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt7, BatchToSpaceNdNhwcTest7<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt_3D, BatchToSpaceNdNhwcTest8<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwInt1, BatchToSpaceNdNchwTest1<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwInt2, BatchToSpaceNdNchwTest2<DataType::QAsymmS8>)
@@ -65,6 +67,7 @@
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint5, BatchToSpaceNdNhwcTest5<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint6, BatchToSpaceNdNhwcTest6<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint7, BatchToSpaceNdNhwcTest7<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint_3D, BatchToSpaceNdNhwcTest8<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwUint1, BatchToSpaceNdNchwTest1<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwUint2, BatchToSpaceNdNchwTest2<DataType::QAsymmU8>)
diff --git a/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.cpp b/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.cpp
index 05b5899..f66849a 100644
--- a/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.cpp
+++ b/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.cpp
@@ -1,17 +1,12 @@
//
-// Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#include "NeonBatchToSpaceNdWorkload.hpp"
-#include "NeonWorkloadUtils.hpp"
-
-#include <armnn/utility/NumericCast.hpp>
#include <armnn/utility/PolymorphicDowncast.hpp>
-#include <ResolveType.hpp>
-
namespace armnn
{
@@ -21,21 +16,71 @@
const TensorInfo& output,
const BatchToSpaceNdDescriptor& descriptor)
{
- const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
- const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
- // ArmNN blockShape is [H, W] Cl asks for W, H
+ arm_compute::Status statusBatchToSpace = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeInput = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeOutput = arm_compute::Status(arm_compute::ErrorCode::OK);
+
+ arm_compute::TensorInfo aclReshapeInputInfo = aclInputInfo;
+ arm_compute::TensorInfo aclReshapeOutputInfo = aclOutputInfo;
+
+ // When a spacial dimension is missing (rank=3) set W to 1
+ const unsigned int rank = input.GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = aclInputInfo.tensor_shape();
+ const arm_compute::TensorShape outputShape = aclOutputInfo.tensor_shape();
+
+ if (descriptor.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (descriptor.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ statusReshapeInput = arm_compute::NEReshapeLayer::validate(&aclInputInfo, &aclReshapeInputInfo);
+ statusReshapeOutput = arm_compute::NEReshapeLayer::validate(&aclReshapeOutputInfo, &aclOutputInfo);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
- const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor);
+ const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor, rank);
- const arm_compute::Status aclStatus = arm_compute::NEBatchToSpaceLayer::validate(&aclInputInfo,
- blockWidth,
- blockHeight,
- &aclOutputInfo,
- cropInfo);
- return aclStatus;
+ statusBatchToSpace = arm_compute::NEBatchToSpaceLayer::validate(rank == 3 ? &aclReshapeInputInfo : &aclInputInfo,
+ blockWidth,
+ blockHeight,
+ rank == 3 ? &aclReshapeOutputInfo : &aclOutputInfo,
+ cropInfo);
+
+ if (statusReshapeInput.error_code() == arm_compute::ErrorCode::OK &&
+ statusReshapeOutput.error_code() == arm_compute::ErrorCode::OK &&
+ statusBatchToSpace.error_code() == arm_compute::ErrorCode::OK)
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::OK,
+ "All BatchToSpace layers validate status OK.");
+ }
+ else
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::RUNTIME_ERROR,
+ "BatchToSpace layer validate status failed."
+ + statusBatchToSpace.error_description()
+ + statusReshapeInput.error_description()
+ + statusReshapeOutput.error_description());
+ }
}
NeonBatchToSpaceNdWorkload::NeonBatchToSpaceNdWorkload(const BatchToSpaceNdQueueDescriptor& descriptor,
@@ -50,33 +95,85 @@
m_Data.ValidateInputsOutputs("NeonBatchToSpaceNdWorkload", 1, 1);
- arm_compute::ITensor& input =
- armnn::PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
- arm_compute::ITensor& output =
- armnn::PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
+ arm_compute::ITensor& input = PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ITensor& output = PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
input.info()->set_data_layout(aclDataLayout);
output.info()->set_data_layout(aclDataLayout);
- // ArmNN blockShape is [H, W] Cl asks for W, H
- int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
+ arm_compute::TensorInfo aclReshapeInputInfo = BuildArmComputeTensorInfo(info.m_InputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+ arm_compute::TensorInfo aclReshapeOutputInfo = BuildArmComputeTensorInfo(info.m_OutputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
- const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor.m_Parameters);
+ const unsigned int rank = info.m_InputTensorInfos[0].GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = input.info()->tensor_shape();
+ const arm_compute::TensorShape outputShape = output.info()->tensor_shape();
+
+ // When a spacial dimension is missing set W to 1
+ if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ m_ReshapeInputTensor.allocator()->init(aclReshapeInputInfo);
+ m_ReshapeOutputTensor.allocator()->init(aclReshapeOutputInfo);
+
+ InitialiseArmComputeTensorEmpty(m_ReshapeInputTensor);
+ InitialiseArmComputeTensorEmpty(m_ReshapeOutputTensor);
+
+ m_LayerReshapeInput.reset(new arm_compute::NEReshapeLayer());
+ m_LayerReshapeOutput.reset(new arm_compute::NEReshapeLayer());
+
+ m_LayerReshapeInput->configure(&input, &m_ReshapeInputTensor);
+ m_LayerReshapeOutput->configure(&m_ReshapeOutputTensor, &output);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
+ int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[0]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
+
+ const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor.m_Parameters, rank);
m_Layer.reset(new arm_compute::NEBatchToSpaceLayer());
- m_Layer->configure(&input, blockWidth, blockHeight, &output, cropInfo);
+ m_Layer->configure(rank == 3 ? &m_ReshapeInputTensor : &input,
+ blockWidth,
+ blockHeight,
+ rank == 3 ? &m_ReshapeOutputTensor : &output,
+ cropInfo);
m_Layer->prepare();
}
void NeonBatchToSpaceNdWorkload::Execute() const
{
+ ARMNN_SCOPED_PROFILING_EVENT_NEON_GUID("NeonBatchToSpaceNdWorkload_Execute", this->GetGuid());
+ if (m_LayerReshapeInput)
+ {
+ m_LayerReshapeInput->run();
+ }
if (m_Layer)
{
- ARMNN_SCOPED_PROFILING_EVENT_NEON_GUID("NeonSpaceToBatchNdWorkload_Execute", this->GetGuid());
m_Layer->run();
}
+ if (m_LayerReshapeOutput)
+ {
+ m_LayerReshapeOutput->run();
+ }
}
} //namespace armnn
diff --git a/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.hpp b/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.hpp
index 55f773e..ef5bd13 100644
--- a/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.hpp
+++ b/src/backends/neon/workloads/NeonBatchToSpaceNdWorkload.hpp
@@ -1,16 +1,15 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
-#include <armnn/Tensor.hpp>
-#include <armnn/Descriptors.hpp>
-
#include "NeonBaseWorkload.hpp"
+#include "NeonWorkloadUtils.hpp"
#include <arm_compute/runtime/NEON/functions/NEBatchToSpaceLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEReshapeLayer.h>
namespace armnn
{
@@ -30,6 +29,10 @@
private:
mutable std::unique_ptr<arm_compute::NEBatchToSpaceLayer> m_Layer;
+ mutable std::unique_ptr<arm_compute::NEReshapeLayer> m_LayerReshapeInput;
+ mutable std::unique_ptr<arm_compute::NEReshapeLayer> m_LayerReshapeOutput;
+ arm_compute::Tensor m_ReshapeInputTensor;
+ arm_compute::Tensor m_ReshapeOutputTensor;
};
}
diff --git a/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.cpp b/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.cpp
index e0adc62..291fa81 100644
--- a/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.cpp
+++ b/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.cpp
@@ -5,13 +5,8 @@
#include "NeonSpaceToBatchNdWorkload.hpp"
-#include "NeonWorkloadUtils.hpp"
-
-#include <armnn/utility/NumericCast.hpp>
#include <armnn/utility/PolymorphicDowncast.hpp>
-#include <ResolveType.hpp>
-
namespace armnn
{
@@ -21,24 +16,77 @@
const TensorInfo& output,
const SpaceToBatchNdDescriptor& descriptor)
{
- const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
- const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+ arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
- // ArmNN blockShape is [H, W] Cl asks for W, H
+ arm_compute::Status statusSpaceToBatch = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeInput = arm_compute::Status(arm_compute::ErrorCode::OK);
+ arm_compute::Status statusReshapeOutput = arm_compute::Status(arm_compute::ErrorCode::OK);
+
+ arm_compute::TensorInfo aclReshapeInputInfo = aclInputInfo;
+ arm_compute::TensorInfo aclReshapeOutputInfo = aclOutputInfo;
+
+ // When a spacial dimension is missing (rank=3) set W to 1
+ const unsigned int rank = input.GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = aclInputInfo.tensor_shape();
+ const arm_compute::TensorShape outputShape = aclOutputInfo.tensor_shape();
+
+ if (descriptor.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (descriptor.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ statusReshapeInput = arm_compute::NEReshapeLayer::validate(&aclInputInfo, &aclReshapeInputInfo);
+ statusReshapeOutput = arm_compute::NEReshapeLayer::validate(&aclReshapeOutputInfo, &aclOutputInfo);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
+ int32_t blockWidth = (rank == 3) ? 1 : armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
- arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(
- descriptor.m_PadList[1].first, descriptor.m_PadList[0].first);
- arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(
- descriptor.m_PadList[1].second, descriptor.m_PadList[0].second);
+ unsigned int padLeft = (rank == 3) ? 0 : descriptor.m_PadList[1].first;
+ unsigned int padRight = (rank == 3) ? 0 : descriptor.m_PadList[1].second;
+ arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(padLeft,
+ descriptor.m_PadList[0].first);
+ arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(padRight,
+ descriptor.m_PadList[0].second);
- return arm_compute::NESpaceToBatchLayer::validate(&aclInputInfo,
- blockWidth,
- blockHeight,
- paddingLeftTop,
- paddingRightBottom,
- &aclOutputInfo);
+ statusSpaceToBatch = arm_compute::NESpaceToBatchLayer::validate(rank == 3 ? &aclReshapeInputInfo : &aclInputInfo,
+ blockWidth,
+ blockHeight,
+ paddingLeftTop,
+ paddingRightBottom,
+ rank == 3 ? &aclReshapeOutputInfo : &aclOutputInfo);
+
+ if (statusReshapeInput.error_code() == arm_compute::ErrorCode::OK &&
+ statusReshapeOutput.error_code() == arm_compute::ErrorCode::OK &&
+ statusSpaceToBatch.error_code() == arm_compute::ErrorCode::OK)
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::OK,
+ "All SpaceToBatch layers validate status OK.");
+ }
+ else
+ {
+ return arm_compute::Status(arm_compute::ErrorCode::RUNTIME_ERROR,
+ "SpaceToBatch layer validate status failed."
+ + statusSpaceToBatch.error_description()
+ + statusReshapeInput.error_description()
+ + statusReshapeOutput.error_description());
+ }
}
NeonSpaceToBatchNdWorkload::NeonSpaceToBatchNdWorkload(const SpaceToBatchNdQueueDescriptor& descriptor,
@@ -53,41 +101,91 @@
m_Data.ValidateInputsOutputs("NESpaceToBatchNdWorkload", 1, 1);
- arm_compute::ITensor& input =
- PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
- arm_compute::ITensor& output =
- PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
-
- // ArmNN blockShape is [H, W] Cl asks for W, H
- int32_t blockHeight = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[1]);
-
- arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(
- m_Data.m_Parameters.m_PadList[1].first, m_Data.m_Parameters.m_PadList[0].first);
- arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(
- m_Data.m_Parameters.m_PadList[1].second, m_Data.m_Parameters.m_PadList[0].second);
+ arm_compute::ITensor& input = PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ITensor& output = PolymorphicPointerDowncast<IAclTensorHandle>(m_Data.m_Outputs[0])->GetTensor();
arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
input.info()->set_data_layout(aclDataLayout);
output.info()->set_data_layout(aclDataLayout);
+ arm_compute::TensorInfo aclReshapeInputInfo = BuildArmComputeTensorInfo(info.m_InputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+ arm_compute::TensorInfo aclReshapeOutputInfo = BuildArmComputeTensorInfo(info.m_OutputTensorInfos[0],
+ m_Data.m_Parameters.m_DataLayout);
+
+ const unsigned int rank = info.m_InputTensorInfos[0].GetNumDimensions();
+ if (rank == 3)
+ {
+ const arm_compute::TensorShape inputShape = input.info()->tensor_shape();
+ const arm_compute::TensorShape outputShape = output.info()->tensor_shape();
+
+ // When a spacial dimension is missing set W to 1
+ if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NHWC)
+ {
+ // In ACL dimensions are right to left: C, W, H, N
+ aclReshapeInputInfo.set_tensor_shape({inputShape.x(), 1, inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({outputShape.x(), 1, outputShape.y(), outputShape.z()});
+ }
+ else if (m_Data.m_Parameters.m_DataLayout == armnn::DataLayout::NCHW)
+ {
+ // In ACL dimensions are right to left: W, H, C, N
+ aclReshapeInputInfo.set_tensor_shape({1, inputShape.x(), inputShape.y(), inputShape.z()});
+ aclReshapeOutputInfo.set_tensor_shape({1, outputShape.x(), outputShape.y(), outputShape.z()});
+ }
+ else
+ {
+ throw InvalidArgumentException("Unsupported or unknown DataLayout", CHECK_LOCATION());
+ }
+
+ m_ReshapeInputTensor.allocator()->init(aclReshapeInputInfo);
+ m_ReshapeOutputTensor.allocator()->init(aclReshapeOutputInfo);
+
+ InitialiseArmComputeTensorEmpty(m_ReshapeInputTensor);
+ InitialiseArmComputeTensorEmpty(m_ReshapeOutputTensor);
+
+ m_LayerReshapeInput.reset(new arm_compute::NEReshapeLayer());
+ m_LayerReshapeOutput.reset(new arm_compute::NEReshapeLayer());
+
+ m_LayerReshapeInput->configure(&input, &m_ReshapeInputTensor);
+ m_LayerReshapeOutput->configure(&m_ReshapeOutputTensor, &output);
+ }
+
+ // ArmNN blockShape is [H, W] ACl asks for W, H
+ int32_t blockHeight = armnn::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]);
+ int32_t blockWidth = (rank == 3) ? 1: armnn::numeric_cast<int32_t>(descriptor.m_Parameters.m_BlockShape[1]);
+
+ unsigned int padLeft = (rank == 3) ? 0 : descriptor.m_Parameters.m_PadList[1].first;
+ unsigned int padRight = (rank == 3) ? 0 : descriptor.m_Parameters.m_PadList[1].second;
+ arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D(padLeft,
+ descriptor.m_Parameters.m_PadList[0].first);
+ arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D(padRight,
+ descriptor.m_Parameters.m_PadList[0].second);
+
m_Layer.reset(new arm_compute::NESpaceToBatchLayer());
- m_Layer->configure(&input,
+ m_Layer->configure((rank == 3) ? &m_ReshapeInputTensor : &input,
blockWidth,
blockHeight,
paddingLeftTop,
paddingRightBottom,
- &output);
+ (rank == 3) ? &m_ReshapeOutputTensor : &output);
m_Layer->prepare();
}
void NeonSpaceToBatchNdWorkload::Execute() const
{
+ ARMNN_SCOPED_PROFILING_EVENT_NEON_GUID("NeonSpaceToBatchNdWorkload_Execute", this->GetGuid());
+ if (m_LayerReshapeInput)
+ {
+ m_LayerReshapeInput->run();
+ }
if (m_Layer)
{
- ARMNN_SCOPED_PROFILING_EVENT_NEON_GUID("NeonSpaceToBatchNdWorkload_Execute", this->GetGuid());
m_Layer->run();
}
+ if (m_LayerReshapeOutput)
+ {
+ m_LayerReshapeOutput->run();
+ }
}
} //namespace armnn
\ No newline at end of file
diff --git a/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.hpp b/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.hpp
index 4bd7d2d..35d70d3 100644
--- a/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.hpp
+++ b/src/backends/neon/workloads/NeonSpaceToBatchNdWorkload.hpp
@@ -1,16 +1,15 @@
//
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
-#include <armnn/Tensor.hpp>
-#include <armnn/Descriptors.hpp>
-
#include "NeonBaseWorkload.hpp"
+#include "NeonWorkloadUtils.hpp"
#include <arm_compute/runtime/NEON/functions/NESpaceToBatchLayer.h>
+#include <arm_compute/runtime/NEON/functions/NEReshapeLayer.h>
namespace armnn
{
@@ -30,6 +29,10 @@
private:
mutable std::unique_ptr<arm_compute::NESpaceToBatchLayer> m_Layer;
+ mutable std::unique_ptr<arm_compute::NEReshapeLayer> m_LayerReshapeInput;
+ mutable std::unique_ptr<arm_compute::NEReshapeLayer> m_LayerReshapeOutput;
+ arm_compute::Tensor m_ReshapeInputTensor;
+ arm_compute::Tensor m_ReshapeOutputTensor;
};
} //namespace armnn
\ No newline at end of file