IVGCVSW-5543 Fix delegate Pooling2d failures on CpuAcc/GpuAcc
* Added tolerance when comparing data
* Removed unsupported int16 tests
Signed-off-by: Jan Eilers <jan.eilers@arm.com>
Change-Id: I10f3ac26b894bb1da3af61bfe2d2a41c2f5d2bb1
diff --git a/delegate/CMakeLists.txt b/delegate/CMakeLists.txt
index d53af88..5b64587 100644
--- a/delegate/CMakeLists.txt
+++ b/delegate/CMakeLists.txt
@@ -129,6 +129,7 @@
src/test/SoftmaxTest.cpp
src/test/SoftmaxTestHelper.hpp
src/test/TestUtils.hpp
+ src/test/TestUtils.cpp
src/test/TransposeTest.cpp
src/test/TransposeTestHelper.hpp)
diff --git a/delegate/src/test/Pooling2dTest.cpp b/delegate/src/test/Pooling2dTest.cpp
index bc7bf38..fd52aee 100644
--- a/delegate/src/test/Pooling2dTest.cpp
+++ b/delegate/src/test/Pooling2dTest.cpp
@@ -864,18 +864,6 @@
MaxPool2dUint8ReluTest(backends);
}
-TEST_CASE ("MaxPooling2d_Int16_PaddingSame_GpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
- MaxPool2dInt16PaddingSameTest(backends);
-}
-
-TEST_CASE ("MaxPooling2d_Int16_Relu_GpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
- MaxPool2dInt16ReluTest(backends);
-}
-
TEST_CASE ("AveragePooling2d_FP32_PaddingValid_GpuAcc_Test")
{
std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
@@ -936,18 +924,6 @@
AveragePool2dUint8ReluTest(backends);
}
-TEST_CASE ("AveragePooling2d_Int16_PaddingSame_GpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
- AveragePool2dInt16PaddingSameTest(backends);
-}
-
-TEST_CASE ("AveragePooling2d_Int16_Relu_GpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
- AveragePool2dInt16ReluTest(backends);
-}
-
TEST_CASE ("L2Pooling2d_FP32_PaddingValid_GpuAcc_Test")
{
std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc };
@@ -1037,18 +1013,6 @@
MaxPool2dUint8ReluTest(backends);
}
-TEST_CASE ("MaxPooling2d_Int16_PaddingSame_CpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
- MaxPool2dInt16PaddingSameTest(backends);
-}
-
-TEST_CASE ("MaxPooling2d_Int16_Relu_CpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
- MaxPool2dInt16ReluTest(backends);
-}
-
TEST_CASE ("AveragePooling2d_FP32_PaddingValid_CpuAcc_Test")
{
std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
@@ -1109,18 +1073,6 @@
AveragePool2dUint8ReluTest(backends);
}
-TEST_CASE ("AveragePooling2d_Int16_PaddingSame_CpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
- AveragePool2dInt16PaddingSameTest(backends);
-}
-
-TEST_CASE ("AveragePooling2d_Int16_Relu_CpuAcc_Test")
-{
- std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
- AveragePool2dInt16ReluTest(backends);
-}
-
TEST_CASE ("L2Pooling2d_FP32_PaddingValid_CpuAcc_Test")
{
std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc };
diff --git a/delegate/src/test/Pooling2dTestHelper.hpp b/delegate/src/test/Pooling2dTestHelper.hpp
index f107d94..c2c7be7 100644
--- a/delegate/src/test/Pooling2dTestHelper.hpp
+++ b/delegate/src/test/Pooling2dTestHelper.hpp
@@ -5,6 +5,8 @@
#pragma once
+#include "TestUtils.hpp"
+
#include <armnn_delegate.hpp>
#include <flatbuffers/flatbuffers.h>
@@ -183,26 +185,8 @@
// Run EnqueueWorkload
CHECK(tfLiteInterpreter->Invoke() == kTfLiteOk);
CHECK(armnnDelegateInterpreter->Invoke() == kTfLiteOk);
- // Compare output data
- auto tfLiteDelegateOutputId = tfLiteInterpreter->outputs()[0];
- auto tfLiteDelegateOutputData = tfLiteInterpreter->typed_tensor<T>(tfLiteDelegateOutputId);
- auto tfLiteDelegateOutputTensor = tfLiteInterpreter->tensor(tfLiteDelegateOutputId);
- auto armnnDelegateOutputId = armnnDelegateInterpreter->outputs()[0];
- auto armnnDelegateOutputData = armnnDelegateInterpreter->typed_tensor<T>(armnnDelegateOutputId);
- auto armnnDelegateOutputTensor = armnnDelegateInterpreter->tensor(armnnDelegateOutputId);
- for (size_t i = 0; i < static_cast<size_t>(tfLiteDelegateOutputTensor->dims->size); i++)
- {
- CHECK(outputShape[i] == armnnDelegateOutputTensor->dims->data[i]);
- CHECK(tfLiteDelegateOutputTensor->dims->data[i] == armnnDelegateOutputTensor->dims->data[i]);
- }
-
- for (size_t i = 0; i < expectedOutputValues.size(); i++)
- {
- CHECK(expectedOutputValues[i] == armnnDelegateOutputData[i]);
- CHECK(tfLiteDelegateOutputData[i] == expectedOutputValues[i]);
- CHECK(tfLiteDelegateOutputData[i] == armnnDelegateOutputData[i]);
- }
+ armnnDelegate::CompareOutputData(tfLiteInterpreter, armnnDelegateInterpreter, outputShape, expectedOutputValues);
}
} // anonymous namespace
diff --git a/delegate/src/test/TestUtils.cpp b/delegate/src/test/TestUtils.cpp
new file mode 100644
index 0000000..cf3e1fe
--- /dev/null
+++ b/delegate/src/test/TestUtils.cpp
@@ -0,0 +1,46 @@
+//
+// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "TestUtils.hpp"
+
+namespace armnnDelegate
+{
+
+void CompareData(float tensor1[], float tensor2[], size_t tensorSize)
+{
+ for (size_t i = 0; i < tensorSize; i++)
+ {
+ CHECK(tensor1[i] == doctest::Approx( tensor2[i] ));
+ }
+}
+
+void CompareData(uint8_t tensor1[], uint8_t tensor2[], size_t tensorSize)
+{
+ uint8_t tolerance = 1;
+ for (size_t i = 0; i < tensorSize; i++)
+ {
+ CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance);
+ }
+}
+
+void CompareData(int16_t tensor1[], int16_t tensor2[], size_t tensorSize)
+{
+ int16_t tolerance = 1;
+ for (size_t i = 0; i < tensorSize; i++)
+ {
+ CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance);
+ }
+}
+
+void CompareData(int8_t tensor1[], int8_t tensor2[], size_t tensorSize)
+{
+ int8_t tolerance = 1;
+ for (size_t i = 0; i < tensorSize; i++)
+ {
+ CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance);
+ }
+}
+
+} // namespace armnnDelegate
\ No newline at end of file
diff --git a/delegate/src/test/TestUtils.hpp b/delegate/src/test/TestUtils.hpp
index 9bbab8f..d805f70 100644
--- a/delegate/src/test/TestUtils.hpp
+++ b/delegate/src/test/TestUtils.hpp
@@ -25,6 +25,13 @@
}
}
+// Can be used to compare data with a tolerance depending on their data type
+void CompareData(float tensor1[], float tensor2[], size_t tensorSize);
+void CompareData(int8_t tensor1[], int8_t tensor2[], size_t tensorSize);
+void CompareData(uint8_t tensor1[], uint8_t tensor2[], size_t tensorSize);
+void CompareData(int16_t tensor1[], int16_t tensor2[], size_t tensorSize);
+
+
// Can be used to compare the output tensor shape and values
// from armnnDelegateInterpreter and tfLiteInterpreter.
// Example usage can be found in ControlTestHelper.hpp
@@ -36,7 +43,7 @@
{
auto tfLiteDelegateOutputId = tfLiteInterpreter->outputs()[0];
auto tfLiteDelegateOutputTensor = tfLiteInterpreter->tensor(tfLiteDelegateOutputId);
- auto tfLiteDelageOutputData = tfLiteInterpreter->typed_tensor<T>(tfLiteDelegateOutputId);
+ auto tfLiteDelegateOutputData = tfLiteInterpreter->typed_tensor<T>(tfLiteDelegateOutputId);
auto armnnDelegateOutputId = armnnDelegateInterpreter->outputs()[0];
auto armnnDelegateOutputTensor = armnnDelegateInterpreter->tensor(armnnDelegateOutputId);
auto armnnDelegateOutputData = armnnDelegateInterpreter->typed_tensor<T>(armnnDelegateOutputId);
@@ -48,12 +55,9 @@
CHECK(tfLiteDelegateOutputTensor->dims->data[i] == armnnDelegateOutputTensor->dims->data[i]);
}
- for (size_t i = 0; i < expectedOutputValues.size(); i++)
- {
- CHECK(expectedOutputValues[i] == armnnDelegateOutputData[i]);
- CHECK(tfLiteDelageOutputData[i] == expectedOutputValues[i]);
- CHECK(tfLiteDelageOutputData[i] == armnnDelegateOutputData[i]);
- }
+ armnnDelegate::CompareData(expectedOutputValues.data(), armnnDelegateOutputData , expectedOutputValues.size());
+ armnnDelegate::CompareData(tfLiteDelegateOutputData , expectedOutputValues.data(), expectedOutputValues.size());
+ armnnDelegate::CompareData(tfLiteDelegateOutputData , armnnDelegateOutputData , expectedOutputValues.size());
}
} // namespace armnnDelegate