commit 69b67d89c018981e1d4654ba7adfa6d4d64a813c
author Teresa Charlin <teresa.charlinreyes@arm.com> Thu Jan 05 17:24:34 2023 +0000
committer TeresaARM <teresa.charlinreyes@arm.com> Thu Jan 05 17:42:43 2023 +0000
tree 4f4a14c4822ad619e7b4c3b0b945ecc6fc5e2e35
parent 7000d679b5e5ea1df64a25fbe8e97ec23b95aff6

Add backend name to delegate test names that did not have it.

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: If9531f74d0b503c36f1b72ef51eee7e9f65559f2

delegate/src/test/ControlTest.cpp

diff --git a/delegate/src/test/ControlTest.cpp b/delegate/src/test/ControlTest.cpp
index 43491be..18bbc5a 100644
--- a/delegate/src/test/ControlTest.cpp
+++ b/delegate/src/test/ControlTest.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020,2023 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -286,7 +286,7 @@
     ConcatThreeInputsTest(backends);
 }
 
-TEST_CASE ("Concatenation_Axis_CpuRef_Test")
+TEST_CASE ("Concatenation_Axis_GpuAcc_Test")
 {
     std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     ConcatAxisTest(backends);

delegate/src/test/Convolution2dTest.cpp

diff --git a/delegate/src/test/Convolution2dTest.cpp b/delegate/src/test/Convolution2dTest.cpp
index b2e5fad..1051079 100644
--- a/delegate/src/test/Convolution2dTest.cpp
+++ b/delegate/src/test/Convolution2dTest.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020,2023 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -438,13 +438,13 @@
 TEST_SUITE("TransposeConv_CpuRef_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_CpuRef_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuRef};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_CpuRef_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuRef};
     TransposeConvInt8Test(backends);
@@ -455,13 +455,13 @@
 TEST_SUITE("TransposeConv_CpuAcc_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_CpuAcc_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuAcc};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_CpuAcc_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuAcc};
     TransposeConvInt8Test(backends);
@@ -472,13 +472,13 @@
 TEST_SUITE("TransposeConv_GpuAcc_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_GpuAcc_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_GpuAcc_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     TransposeConvInt8Test(backends);