commit 6f92c8e9f8bb38dcf5dccf8deeff5112ecd8e37c
author Nikhil Raj <nikhil.raj@arm.com> Wed Nov 22 11:41:15 2023 +0000
committer Nikhil Raj <nikhil.raj@arm.com> Wed Nov 22 11:41:15 2023 +0000
tree 0c076149c03ac45c2617f5e02a77b79287ff5a0f
parent 03c7ff3f6188240baaeaeb405a357a0c58195fec

Update Doxygen for 23.11

Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849

latest/_cl_slice_workload_8hpp_source.html

diff --git a/latest/_cl_slice_workload_8hpp_source.html b/latest/_cl_slice_workload_8hpp_source.html
index 5677903..150fb9a 100644
--- a/latest/_cl_slice_workload_8hpp_source.html
+++ b/latest/_cl_slice_workload_8hpp_source.html
@@ -36,7 +36,7 @@
   <img alt="ArmNN" src="Arm_NN_horizontal_blue.png" style="max-width: 15rem; margin-top: .5rem; margin-left 13px"/>
   <td id="projectalign" style="padding-left: 0.9em;">
    <div id="projectname">
-   &#160;<span id="projectnumber">23.08</span>
+   &#160;<span id="projectnumber">23.11</span>
    </div>
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  </tr>
@@ -140,12 +140,12 @@
 <div class="ttc" id="aclassarmnn_1_1_cl_slice_workload_html_adcc9a2099f0e6438775aecce5690fd9e"><div class="ttname"><a href="classarmnn_1_1_cl_slice_workload.html#adcc9a2099f0e6438775aecce5690fd9e">armnn::ClSliceWorkload::ClSliceWorkload</a></div><div class="ttdeci">ClSliceWorkload(const SliceQueueDescriptor &amp;descriptor, const WorkloadInfo &amp;info, const arm_compute::CLCompileContext &amp;clCompileContext)</div><div class="ttdef"><b>Definition:</b> <a href="_cl_slice_workload_8cpp_source.html#l00033">ClSliceWorkload.cpp:33</a></div></div>
 <div class="ttc" id="anamespacearmnn_html"><div class="ttname"><a href="namespacearmnn.html">armnn</a></div><div class="ttdoc">Copyright (c) 2021 ARM Limited and Contributors.</div><div class="ttdef"><b>Definition:</b> <a href="01__00__quick__start_8dox_source.html#l00006">01_00_quick_start.dox:6</a></div></div>
 <div class="ttc" id="a_cl_base_workload_8hpp_html"><div class="ttname"><a href="_cl_base_workload_8hpp.html">ClBaseWorkload.hpp</a></div></div>
-<div class="ttc" id="astructarmnn_1_1_slice_queue_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_slice_queue_descriptor.html">armnn::SliceQueueDescriptor</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00651">WorkloadData.hpp:651</a></div></div>
+<div class="ttc" id="astructarmnn_1_1_slice_queue_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_slice_queue_descriptor.html">armnn::SliceQueueDescriptor</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00656">WorkloadData.hpp:656</a></div></div>
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     <li class="navelem"><a class="el" href="dir_68267d1309a1af8e8297ef4c3efbcdba.html">src</a></li><li class="navelem"><a class="el" href="dir_0f3cdec46afbc61a1ded8e1687c9c9a0.html">backends</a></li><li class="navelem"><a class="el" href="dir_1ad86c6d39ab715a831555571b9e98a5.html">cl</a></li><li class="navelem"><a class="el" href="dir_2d9c087bc7f49a1d7a25fdc615d2f0c9.html">workloads</a></li><li class="navelem"><a class="el" href="_cl_slice_workload_8hpp.html">ClSliceWorkload.hpp</a></li>
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