IVGCVSW-2371 Add Rsqrt Ref implementation
*Added Unit Tests
Change-Id: I6cceb8e6dcda35ce08415f8e5ca86019a64d26e3
diff --git a/src/backends/reference/RefLayerSupport.cpp b/src/backends/reference/RefLayerSupport.cpp
index a64339e..56d2e4c 100644
--- a/src/backends/reference/RefLayerSupport.cpp
+++ b/src/backends/reference/RefLayerSupport.cpp
@@ -495,6 +495,17 @@
&TrueFunc<>);
}
+bool RefLayerSupport::IsRsqrtSupported(const TensorInfo& input,
+ const TensorInfo& output,
+ Optional<std::string&> reasonIfUnsupported) const
+{
+ ignore_unused(output);
+ return IsSupportedForDataTypeRef(reasonIfUnsupported,
+ input.GetDataType(),
+ &TrueFunc<>,
+ &FalseFuncU8<>);
+}
+
bool RefLayerSupport::IsSoftmaxSupported(const TensorInfo& input,
const TensorInfo& output,
const SoftmaxDescriptor& descriptor,
diff --git a/src/backends/reference/RefLayerSupport.hpp b/src/backends/reference/RefLayerSupport.hpp
index 3941f4b..188faa8 100644
--- a/src/backends/reference/RefLayerSupport.hpp
+++ b/src/backends/reference/RefLayerSupport.hpp
@@ -185,6 +185,10 @@
bool IsResizeBilinearSupported(const TensorInfo& input,
Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
+ bool IsRsqrtSupported(const TensorInfo& input,
+ const TensorInfo& output,
+ Optional<std::string&> reasonIfUnsupported = EmptyOptional()) const override;
+
bool IsSoftmaxSupported(const TensorInfo& input,
const TensorInfo& output,
const SoftmaxDescriptor& descriptor,
diff --git a/src/backends/reference/RefWorkloadFactory.cpp b/src/backends/reference/RefWorkloadFactory.cpp
index eb8807e..7929363 100644
--- a/src/backends/reference/RefWorkloadFactory.cpp
+++ b/src/backends/reference/RefWorkloadFactory.cpp
@@ -312,4 +312,10 @@
return MakeWorkload<RefDebugFloat32Workload, RefDebugUint8Workload>(descriptor, info);
}
-} // namespace armnn
+std::unique_ptr<IWorkload> RefWorkloadFactory::CreateRsqrt(const RsqrtQueueDescriptor& descriptor,
+ const WorkloadInfo& info) const
+{
+ return MakeWorkload<RefRsqrtFloat32Workload, NullWorkload>(descriptor, info);
+}
+
+} // namespace armnn
\ No newline at end of file
diff --git a/src/backends/reference/RefWorkloadFactory.hpp b/src/backends/reference/RefWorkloadFactory.hpp
index f4401cc..f6707f5 100644
--- a/src/backends/reference/RefWorkloadFactory.hpp
+++ b/src/backends/reference/RefWorkloadFactory.hpp
@@ -164,6 +164,9 @@
virtual std::unique_ptr<IWorkload> CreateDebug(const DebugQueueDescriptor& descriptor,
const WorkloadInfo& info) const override;
+
+ virtual std::unique_ptr<IWorkload> CreateRsqrt(const RsqrtQueueDescriptor& descriptor,
+ const WorkloadInfo& info) const override;
private:
template <typename F32Workload, typename U8Workload, typename QueueDescriptorType>
diff --git a/src/backends/reference/backend.mk b/src/backends/reference/backend.mk
index b23c752..84f15c9 100644
--- a/src/backends/reference/backend.mk
+++ b/src/backends/reference/backend.mk
@@ -57,6 +57,7 @@
workloads/RefReshapeUint8Workload.cpp \
workloads/RefResizeBilinearFloat32Workload.cpp \
workloads/RefResizeBilinearUint8Workload.cpp \
+ workloads/RefRsqrtFloat32Workload.cpp \
workloads/RefSoftmaxFloat32Workload.cpp \
workloads/RefSoftmaxUint8Workload.cpp \
workloads/RefSpaceToBatchNdWorkload.cpp \
@@ -64,6 +65,7 @@
workloads/RefSplitterFloat32Workload.cpp \
workloads/RefSplitterUint8Workload.cpp \
workloads/ResizeBilinear.cpp \
+ workloads/Rsqrt.cpp \
workloads/SpaceToBatchNd.cpp \
workloads/StridedSlice.cpp \
workloads/StringMapping.cpp \
diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp
index 7223f04..50c47ae 100644
--- a/src/backends/reference/test/RefLayerTests.cpp
+++ b/src/backends/reference/test/RefLayerTests.cpp
@@ -380,6 +380,12 @@
ARMNN_AUTO_TEST_CASE(SimpleReshapeFloat32, SimpleReshapeFloat32Test)
ARMNN_AUTO_TEST_CASE(SimpleReshapeUint8, SimpleReshapeUint8Test)
+// Rsqrt
+ARMNN_AUTO_TEST_CASE(Rsqrt2d, Rsqrt2dTest)
+ARMNN_AUTO_TEST_CASE(Rsqrt3d, Rsqrt3dTest)
+ARMNN_AUTO_TEST_CASE(RsqrtZero, RsqrtZeroTest)
+ARMNN_AUTO_TEST_CASE(RsqrtNegative, RsqrtNegativeTest)
+
// Permute
ARMNN_AUTO_TEST_CASE(SimplePermuteFloat32, SimplePermuteFloat32Test)
ARMNN_AUTO_TEST_CASE(SimplePermuteUint8, SimplePermuteUint8Test)
diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt
index d71e6ea..d15f77d 100644
--- a/src/backends/reference/workloads/CMakeLists.txt
+++ b/src/backends/reference/workloads/CMakeLists.txt
@@ -94,6 +94,8 @@
RefResizeBilinearFloat32Workload.hpp
RefResizeBilinearUint8Workload.cpp
RefResizeBilinearUint8Workload.hpp
+ RefRsqrtFloat32Workload.cpp
+ RefRsqrtFloat32Workload.hpp
RefSoftmaxFloat32Workload.cpp
RefSoftmaxFloat32Workload.hpp
RefSoftmaxUint8Workload.cpp
@@ -110,6 +112,8 @@
RefWorkloadUtils.hpp
ResizeBilinear.cpp
ResizeBilinear.hpp
+ Rsqrt.cpp
+ Rsqrt.hpp
Softmax.cpp
Softmax.hpp
SpaceToBatchNd.hpp
diff --git a/src/backends/reference/workloads/RefRsqrtFloat32Workload.cpp b/src/backends/reference/workloads/RefRsqrtFloat32Workload.cpp
new file mode 100644
index 0000000..c08dbf0
--- /dev/null
+++ b/src/backends/reference/workloads/RefRsqrtFloat32Workload.cpp
@@ -0,0 +1,25 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "RefRsqrtFloat32Workload.hpp"
+
+#include "RefWorkloadUtils.hpp"
+#include "Rsqrt.hpp"
+
+#include <Profiling.hpp>
+
+namespace armnn
+{
+
+void RefRsqrtFloat32Workload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefRsqrtFloat32Workload_Execute");
+
+ Rsqrt(GetInputTensorDataFloat(0, m_Data),
+ GetOutputTensorDataFloat(0, m_Data),
+ GetTensorInfo(m_Data.m_Inputs[0]));
+}
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefRsqrtFloat32Workload.hpp b/src/backends/reference/workloads/RefRsqrtFloat32Workload.hpp
new file mode 100644
index 0000000..9d1b450
--- /dev/null
+++ b/src/backends/reference/workloads/RefRsqrtFloat32Workload.hpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+
+class RefRsqrtFloat32Workload : public Float32Workload<RsqrtQueueDescriptor>
+{
+public:
+ using Float32Workload<RsqrtQueueDescriptor>::Float32Workload;
+ virtual void Execute() const override;
+};
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp
index ddce68e..8beb03f 100644
--- a/src/backends/reference/workloads/RefWorkloads.hpp
+++ b/src/backends/reference/workloads/RefWorkloads.hpp
@@ -59,3 +59,4 @@
#include "RefBatchToSpaceNdUint8Workload.hpp"
#include "RefBatchToSpaceNdFloat32Workload.hpp"
#include "RefDebugWorkload.hpp"
+#include "RefRsqrtFloat32Workload.hpp"
diff --git a/src/backends/reference/workloads/Rsqrt.cpp b/src/backends/reference/workloads/Rsqrt.cpp
new file mode 100644
index 0000000..cee38fc
--- /dev/null
+++ b/src/backends/reference/workloads/Rsqrt.cpp
@@ -0,0 +1,23 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "Rsqrt.hpp"
+
+#include <cmath>
+
+namespace armnn
+{
+
+void Rsqrt(const float* in,
+ float* out,
+ const TensorInfo& tensorInfo)
+{
+ for (size_t i = 0; i < tensorInfo.GetNumElements(); i++)
+ {
+ out[i] = 1.f / sqrtf(in[i]);
+ }
+}
+
+} //namespace armnn
\ No newline at end of file
diff --git a/src/backends/reference/workloads/Rsqrt.hpp b/src/backends/reference/workloads/Rsqrt.hpp
new file mode 100644
index 0000000..35caced
--- /dev/null
+++ b/src/backends/reference/workloads/Rsqrt.hpp
@@ -0,0 +1,18 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include <armnn/Tensor.hpp>
+#include <armnn/Types.hpp>
+
+namespace armnn
+{
+
+/// Performs the reciprocal squareroot function elementwise
+/// on the inputs to give the outputs.
+void Rsqrt(const float* in,
+ float* out,
+ const TensorInfo& tensorInfo);
+
+} //namespace armnn