IVGCVSW-6469 Add MirrorPad TfLiteParser and TfLiteDelegate Support
Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com>
Change-Id: Ia1c97adb401c5381341408ec1e4da287ef2d48fe
diff --git a/src/armnnTfLiteParser/TfLiteParser.cpp b/src/armnnTfLiteParser/TfLiteParser.cpp
index 7db5d85..125a763 100644
--- a/src/armnnTfLiteParser/TfLiteParser.cpp
+++ b/src/armnnTfLiteParser/TfLiteParser.cpp
@@ -670,6 +670,7 @@
m_ParserFunctions[tflite::BuiltinOperator_MAXIMUM] = &TfLiteParserImpl::ParseMaximum;
m_ParserFunctions[tflite::BuiltinOperator_MEAN] = &TfLiteParserImpl::ParseMean;
m_ParserFunctions[tflite::BuiltinOperator_MINIMUM] = &TfLiteParserImpl::ParseMinimum;
+ m_ParserFunctions[tflite::BuiltinOperator_MIRROR_PAD] = &TfLiteParserImpl::ParseMirrorPad;
m_ParserFunctions[tflite::BuiltinOperator_MUL] = &TfLiteParserImpl::ParseMul;
m_ParserFunctions[tflite::BuiltinOperator_NEG] = &TfLiteParserImpl::ParseNeg;
m_ParserFunctions[tflite::BuiltinOperator_NOT_EQUAL] = &TfLiteParserImpl::ParseNotEqual;
@@ -2214,6 +2215,77 @@
RegisterOutputSlots(subgraphIndex, operatorIndex, layer, {outputTensorIndexes[0]});
}
+void TfLiteParserImpl::ParseMirrorPad(size_t subgraphIndex, size_t operatorIndex)
+{
+ CHECK_MODEL(m_Model, subgraphIndex, operatorIndex);
+
+ TfLiteParserImpl::TensorRawPtrVector inputs = GetInputs(m_Model, subgraphIndex, operatorIndex);
+ CHECK_VALID_SIZE(inputs.size(), 2);
+
+ TfLiteParserImpl::TensorRawPtrVector outputs = GetOutputs(m_Model, subgraphIndex, operatorIndex);
+ CHECK_VALID_SIZE(outputs.size(), 1);
+
+ armnn::TensorInfo inputTensorInfo = ToTensorInfo(inputs[0]);
+
+ armnn::TensorInfo padTensorInfo = ToTensorInfo(inputs[1]);
+ BufferRawPtr bufferPtr = GetBuffer(m_Model, inputs[1]->buffer);
+
+ std::vector<unsigned int> padBuffer(padTensorInfo.GetNumElements());
+ ::memcpy(padBuffer.data(), bufferPtr->data.data(), padTensorInfo.GetNumBytes());
+
+ size_t step = 2;
+ armnn::PadDescriptor desc;
+ for (unsigned int i = 0; i < padTensorInfo.GetNumElements() / step; ++i)
+ {
+ desc.m_PadList.emplace_back(padBuffer[i * step], padBuffer[i * step + 1]);
+ }
+
+ const auto& operatorPtr = m_Model->subgraphs[subgraphIndex]->operators[operatorIndex];
+ const auto* options = operatorPtr->builtin_options.AsMirrorPadOptions();
+
+ if (options->mode == tflite::MirrorPadMode_REFLECT)
+ {
+ desc.m_PaddingMode = PaddingMode::Reflect;
+ }
+ else if (options->mode == tflite::MirrorPadMode_SYMMETRIC)
+ {
+ desc.m_PaddingMode = PaddingMode::Symmetric;
+ }
+ else
+ {
+ ARMNN_THROW_PARSE_EXCEPTION("PaddingMode must be either REFLECT or SYMMETRIC");
+ }
+
+ // If padding mode is Reflect then both paddings must be no greater than inputShape(i) - 1.
+ // If padding mode is Symmetric then both paddings must be no greater than inputShape(i).
+ auto inputShape = inputTensorInfo.GetShape();
+ auto padList = desc.m_PadList;
+
+ const unsigned int isReflect = static_cast<unsigned int>(desc.m_PaddingMode == PaddingMode::Reflect);
+ for(unsigned int i = 0; i < padList.size(); ++i)
+ {
+ if(padList.at(i).first > (inputShape[i] - isReflect) ||
+ padList.at(i).second > (inputShape[i] - isReflect))
+ {
+ ARMNN_THROW_PARSE_EXCEPTION("Padding values must be less (Reflect) or "
+ "equal (Symmetric) to the dimension size.");
+ }
+ }
+
+ auto layerName = fmt::format("MirrorPad:{}:{}", subgraphIndex, operatorIndex);
+ TensorInfo outputTensorInfo = ToTensorInfo(outputs[0], true);
+
+ IConnectableLayer* layer = m_Network->AddPadLayer(desc, layerName.c_str());
+ ARMNN_ASSERT(layer != nullptr);
+ layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo);
+
+ auto inputTensorIndexes = AsUnsignedVector(GetInputTensorIds(m_Model, subgraphIndex, operatorIndex));
+ RegisterInputSlots(subgraphIndex, operatorIndex, layer, {inputTensorIndexes[0]});
+
+ auto outputTensorIndexes = AsUnsignedVector(GetOutputTensorIds(m_Model, subgraphIndex, operatorIndex));
+ RegisterOutputSlots(subgraphIndex, operatorIndex, layer, {outputTensorIndexes[0]});
+}
+
void TfLiteParserImpl::ParsePrelu(size_t subgraphIndex, size_t operatorIndex)
{
CHECK_MODEL(m_Model, subgraphIndex, operatorIndex);
diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp
index 3d4fd65..512b87f 100644
--- a/src/armnnTfLiteParser/TfLiteParser.hpp
+++ b/src/armnnTfLiteParser/TfLiteParser.hpp
@@ -149,6 +149,7 @@
void ParseMaximum(size_t subgraphIndex, size_t operatorIndex);
void ParseMean(size_t subgraphIndex, size_t operatorIndex);
void ParseMinimum(size_t subgraphIndex, size_t operatorIndex);
+ void ParseMirrorPad(size_t subgraphIndex, size_t operatorIndex);
void ParseMul(size_t subgraphIndex, size_t operatorIndex);
void ParseNeg(size_t subgraphIndex, size_t operatorIndex);
void ParseNotEqual(size_t subgraphIndex, size_t operatorIndex);
diff --git a/src/armnnTfLiteParser/test/MirrorPad.cpp b/src/armnnTfLiteParser/test/MirrorPad.cpp
new file mode 100644
index 0000000..af0cbfdd6
--- /dev/null
+++ b/src/armnnTfLiteParser/test/MirrorPad.cpp
@@ -0,0 +1,138 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ParserFlatbuffersFixture.hpp"
+
+TEST_SUITE("TensorflowLiteParser_MirrorPad")
+{
+struct MirrorPadFixture : public ParserFlatbuffersFixture
+{
+ explicit MirrorPadFixture(const std::string& inputShape,
+ const std::string& outputShape,
+ const std::string& padListShape,
+ const std::string& padListData,
+ const std::string& padMode,
+ const std::string& dataType = "FLOAT32",
+ const std::string& scale = "1.0",
+ const std::string& offset = "0")
+ {
+ m_JsonString = R"(
+ {
+ "version": 3,
+ "operator_codes": [ { "builtin_code": "MIRROR_PAD" } ],
+ "subgraphs": [ {
+ "tensors": [
+ {
+ "shape": )" + inputShape + R"(,
+ "type": )" + dataType + R"(,
+ "buffer": 0,
+ "name": "inputTensor",
+ "quantization": {
+ "min": [ 0.0 ],
+ "max": [ 255.0 ],
+ "scale": [ )" + scale + R"( ],
+ "zero_point": [ )" + offset + R"( ],
+ }
+ },
+ {
+ "shape": )" + outputShape + R"(,
+ "type": )" + dataType + R"(,
+ "buffer": 1,
+ "name": "outputTensor",
+ "quantization": {
+ "min": [ 0.0 ],
+ "max": [ 255.0 ],
+ "scale": [ )" + scale + R"( ],
+ "zero_point": [ )" + offset + R"( ],
+ }
+ },
+ {
+ "shape": )" + padListShape + R"( ,
+ "type": "INT32",
+ "buffer": 2,
+ "name": "padList",
+ "quantization": {
+ "min": [ 0.0 ],
+ "max": [ 255.0 ],
+ "scale": [ 1.0 ],
+ "zero_point": [ 0 ],
+ }
+ }
+ ],
+ "inputs": [ 0 ],
+ "outputs": [ 1 ],
+ "operators": [
+ {
+ "opcode_index": 0,
+ "inputs": [ 0, 2 ],
+ "outputs": [ 1 ],
+ "builtin_options_type": "MirrorPadOptions",
+ "builtin_options": {
+ "mode": )" + padMode + R"( ,
+ },
+ "custom_options_format": "FLEXBUFFERS"
+ }
+ ],
+ } ],
+ "buffers" : [
+ { },
+ { },
+ { "data": )" + padListData + R"(, },
+ ]
+ }
+ )";
+ SetupSingleInputSingleOutput("inputTensor", "outputTensor");
+ }
+};
+
+struct SimpleMirrorPadSymmetricFixture : public MirrorPadFixture
+{
+ SimpleMirrorPadSymmetricFixture() : MirrorPadFixture("[ 3, 3 ]", "[ 7, 7 ]", "[ 2, 2 ]",
+ "[ 2,0,0,0, 2,0,0,0, 2,0,0,0, 2,0,0,0 ]",
+ "SYMMETRIC", "FLOAT32") {}
+};
+
+TEST_CASE_FIXTURE(SimpleMirrorPadSymmetricFixture, "ParseMirrorPadSymmetric")
+{
+ RunTest<2, armnn::DataType::Float32>
+ (0,
+ {{ "inputTensor", { 1.0f, 2.0f, 3.0f,
+ 4.0f, 5.0f, 6.0f,
+ 7.0f, 8.0f, 9.0f }}},
+
+ {{ "outputTensor", { 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f,
+ 2.0f, 1.0f, 1.0f, 2.0f, 3.0f, 3.0f, 2.0f,
+ 2.0f, 1.0f, 1.0f, 2.0f, 3.0f, 3.0f, 2.0f,
+ 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f,
+ 8.0f, 7.0f, 7.0f, 8.0f, 9.0f, 9.0f, 8.0f,
+ 8.0f, 7.0f, 7.0f, 8.0f, 9.0f, 9.0f, 8.0f,
+ 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f }}});
+}
+
+struct SimpleMirrorPadReflectFixture : public MirrorPadFixture
+{
+ SimpleMirrorPadReflectFixture() : MirrorPadFixture("[ 3, 3 ]", "[ 7, 7 ]", "[ 2, 2 ]",
+ "[ 2,0,0,0, 2,0,0,0, 2,0,0,0, 2,0,0,0 ]",
+ "REFLECT", "FLOAT32") {}
+};
+
+TEST_CASE_FIXTURE(SimpleMirrorPadReflectFixture, "ParseMirrorPadRelfect")
+{
+ RunTest<2, armnn::DataType::Float32>
+ (0,
+ {{ "inputTensor", { 1.0f, 2.0f, 3.0f,
+ 4.0f, 5.0f, 6.0f,
+ 7.0f, 8.0f, 9.0f }}},
+
+ {{ "outputTensor", { 9.0f, 8.0f, 7.0f, 8.0f, 9.0f, 8.0f, 7.0f,
+ 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f,
+ 3.0f, 2.0f, 1.0f, 2.0f, 3.0f, 2.0f, 1.0f,
+ 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f,
+ 9.0f, 8.0f, 7.0f, 8.0f, 9.0f, 8.0f, 7.0f,
+ 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f,
+ 3.0f, 2.0f, 1.0f, 2.0f, 3.0f, 2.0f, 1.0f }}});
+}
+
+}